Yield ManagementYield ManagementYield Enhancement and Process Control Strategies

for the Semiconductor Industry

S O L U T I O N SYield Enhancement and Process Control Strategies

for the Semiconductor Industry

VOLUME I ISSUE 2 AUTUMN 1998 $5.00 US

6 COVER STORY:LITHOGRAPHY DEFECTS —THE HIDDEN YIELD KILLERS

13 IDENTIFYING PROCESS DRIFT

WITH CD SEMS

25 INSPECTION IMPLICATIONS OF

A DESIGN RULE SHRINK

6 COVER STORY:LITHOGRAPHY DEFECTS —THE HIDDEN YIELD KILLERS

13 IDENTIFYING PROCESS DRIFT

WITH CD SEMS

25 INSPECTION IMPLICATIONS OF

A DESIGN RULE SHRINK

S O L U T I O N S

Autumn 1998 Yield Management Solutions2

C O N T E N T S

F e a t u r e s

C o v e r S t o r y

6 Lithography Defects — The Hidden Yield Killers

In today’s environment of rapidly shrinking geometries and increasing device complexity,minimizing defect density has become increasingly critical to maintaining high yields. For the lithography engineer, this means thatdefect density is now as important a concern as critical dimension and overlay metrology in the development and implementation of lithography processes.

Cover image by Luie Lopez,Stephen Marley Productions

Lithography

11 Stepper Focus Metrology and Analysis using a Phase Shift MaskPhase shift focus monitor reticle and analysis software enable a quantitative measure of the bestfocus position.

13 Identifying Process Drift with CD SEMsWhile critical dimension is the standard metric onwhich CD SEM monitoring is based, other andpotentially more sensitive metrics are available fromthe same tool.

16 Analysis of ESD-Induced Reticle DefectsESD damage to reticles can result in critical yieldlosses, but there are methodologies that can minimizethe potential for such damage.

Analysis

20 Image Management: A New Approach for YieldAnalysisAutomated storage and retrieval of images generatedby inspection, metrology and failure analysis toolscan expedite root cause analysis of yield excursions.

22 Yield Enhancement with Bitmap AnalysisReview of failing bit data is an essential tool forimproving yields in memory arrays, and an analysisof failing bit patterns can help pinpoint the cause ofbit failures.

Inspection

25 Inspection Implications of a Design Rule ShrinkDefect inspection systems and strategies are changing as a result of shrinking design rules, newtechnologies, materials and financial considerations.

29 Automatic Defect Classification: A ProductivityImprovement ToolADC minimizes cost of excursions by eliminatinginaccuracies and inconsistencies associated withmanual defect classification and review.

A U T U M N 1 9 9 8

20 2513

Metrology

37 Monitoring of Low Dielectric Constant Parylene Films usingSpectroscopic EllipsometryNew data collection and analysis algorithms are required to mea-sure thickness and refraction on new low dielectric constant films.

41 Tungsten Plug Measurement for CMP Development andProductionAutomated high-resolution profiler provides an effective method tomeasure tungsten plugs post-CMP.

Corporate

44 Bringing the Future into Focus

Excerpts from KLA-Tencor’s SEMICON West ’98 video, which featured interviews with industry leaders Mark Melliar-Smith, President and CEO of SEMATECH; Dale Harbison, Vice Presidentof Texas Instrument’s Semiconductor Group; and Sung W. Lee, President of Samsung Austin Semiconductor.

F e a t u r e s

S e c t i o n s

4 Editorial: An Opportunity for Growth

5 Business News

To complement and expand its Intelligent Line Monitor (ILM) solution, KLA-Tencor recently acquired DeviceWare, a provider of leading bitmap analysis software, and VARS Inc., a leadingsupplier of image archival and retrieval systems.

19 Industry Viewpoint: Bridging the Gap to 300 mm Wafers

The industry needs cost-effective strategies to facilitate the transitionto 300 mm wafers. According to Dan Hutcheson, VLSI Research,one of the most promising strategies is the use of bridge tools.

34 Yield Management Seminar Series

YMS at a glance.

35 Best of YMS

Inspection of Advanced OPC Reticles.

36 KLA-Tencor Autumn ’98 Trade Show Calendar

43 Q & A

KLA-Tencor’s Yield Management Consulting Group.

Autumn 1998 Yield

P r o d u c t N e w s

46 362Reticle Inspection System

AMRAY4000 Series Defect ReviewSEM Systems

47 Windows NT for Thin FilmMeasurement Tools

HRP-220High-Resolution Profiler

KLASS PSFPhase Shift Focus Monitor

Mana

Yield Management Solutions ispublished by KLA-Tencor

Corporation. To receive YieldManagement Solutions contactCorporate Communications at:

KLA-Tencor Corporation160 Rio Robles

San Jose, CA 95134Tel 408.875.4200Fax 408.875.4144www.kla-tencor.com

For literature requests call:800.450.5308

©1998 KLA-Tencor Corporation. All rights reserved. Material may not be

reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective

companies or organizations.

gement Solutions 3

Editorial

S O L U T I O N SYield Management

S E C T I O N S

EDITOR-IN-CHIEFRoberta Emerson

MANAGING EDITORJudy Dale

CONTRIBUTING EDITORSKern Beare Carol Johnson Kavitha Kannan Robert Mendoza

ASSOCIATE EDITORKevin Clover

EDITORIAL ASSISTANTS

Yield ManagementS O L U T I O N S

An Opportunityfor Growth

CORPORATE HEADQUARTERSKLA-Tencor Corporation160 Rio RoblesSan Jose, California 95134408.875.4200

INTERNATIONAL OFFICESKLA-Tencor France SARLEvry Cedex, France011 33 16 936 6969

KLA-Tencor GmbHMunich, Germany011 49 89 8902 170

KLA-Tencor (Israel) CorporationMigdal Ha’Emek, Israel011 972 6 6449450

KLA-Tencor Japan Ltd.Yokohama, Japan011 81 45 335 8200

KLA-Tencor Korea Inc.Seoul, Korea011 822 41 50555

Lars Ahntholz Petra DonnellyJanet Ely Holly Nielsen

ART DIRECTOR AND

PRODUCTION MANAGERShirley Short

DESIGN CONSULTANTCarlos Hueso

CIRCULATIONCathy Correia

KLA-Tencor Worldwide

It is too easy to look at the currentstate of the industry and see onlythe economic impact of the Asianfinancial crisis, the slowing demandfor semiconductor-based products,and the resulting closure or cancel-lation of fabs. But long-time indus-try watchers and experienced man-agement teams know that this isalso an opportunity for the industry.Just below the surface of this “doomand gloom” outlook lies tremendousmomentum toward the excitingnew technologies and developmentsrequired to meet the evolvingdemands of the semiconductorroadmap and the information age.

Now and in the future, yieldenhancement strategies and processcontrol improvements significantlyimpact the success of every fab.Achieving profitability continues todrive fast ramp speeds, reducedcosts and higher return on invest-ment. At the same time, technology

Autumn 1998 Yield M4

KLA-Tencor (Malaysia) Sdn. Bhd.Johor, Malaysia011 607 557 1946

KLA-Tencor (Singapore) Pte. Ltd.Singapore011 65 782 6788

developments, such as those discussed in this issue, will be criti-cal to the implementation of newprocesses and circuit designs. Phaseshift masks and other key lithogra-phy developments, automatic defectclassification, comprehensive yieldanalysis, and the measurement ofnew films and materials, will allplay an important role.

The most visionary companies willsee this period as an opportune timeto enhance their technologies, theirproducts and processes. The mostsavvy individuals will see this as atime to learn new technical skillsand gain expertise for when thecycle turns up again. This industrydownturn is an opportunity toexpand our technical horizons andestablish a new platform fromwhich to create again the kind ofextraordinary changes that thisindustry has been responsible forthroughout its history.

Roberta Emerson

Vice President, Corporate Communications

anagement Solutions

KLA-Tencor Taiwan BranchHsinchu, Taiwan011 886 35 335163

KLA-Tencor LimitedWokingham, United Kingdom011 44 118 936 5700

S E C T I O N S

BBuussiinneessss NNeewwss

Focus on Yield New bitmap analysis and image managementsolutions offer accelerated yield learning

KLA-Tencor recently acquired two pri-vately held companies to complementand expand its Intelligent Line Monitor(ILM) solution, which integrates auto-mated inspection, classification andanalysis capabilities for real-timeexcursion monitoring and acceleratedyield learning. DeviceWare, aprovider of leading bitmap analysissoftware, and VARS, Inc., a leadingsupplier of image archival andretrieval systems for semiconductorequipment, were acquired in June,1998.

Bitmap line monitor speedsfailure analysisThe DeviceWare acquisition willallow KLA-Tencor customers to system-atically collect and analyze electricalbitmap data, and then automaticallymerge that data with inline defectdata using the Klarity Defect DataAnalysis System. By being able toautomatically correlate bitmap failuresto physical defects, fabs can morequickly identify true yield-killingdefects for accelerated yield learning.“With this capability,” said GlynDavies, senior director of marketing,Yield Management Software Group,“we are essentially integrating auto-mated test equipment into our overallILM solution, enabling rapid and on-going feedback on the failure mecha-nisms of a device for faster resolutionof yield problems.”

The bitmap analysis system collectsbitmap data from a range of auto-mated test equipment — includingmemory testers, logic testers and

mixed signal testers — and then auto-matically translates the electricaladdresses of the failed bits into thecorrect physical locations on the die.In addition to sending the translatedbitmap data to Klarity for automaticcorrelation with inline defect data, theconverted bitmap data can also beautomatically analyzed for failed bitpatterns using powerful yet intuitivevisualization tools, including full waferbitmap viewing, wafer stacking, bindata overlay, die stacking and more.

KLA-Tencor’s new bitmap solution isdesigned for all manner of memory,including SRAM, DRAM and EEP-ROM. It can also be used in thegrowing embedded memory cachesof DSP, MPU, MCU and ASICdevices.

Image management addssynergy to inspection,metrology and analysisproductsImage management has become anincreasingly important part of thediagnostic process, providing criticalinformation about the nature andsource of yield-limiting process prob-lems. The acquisition of VARS, Inc.gives KLA-Tencor a comprehensiveimage management solution, addingsynergy to the company’s portfolio ofindustry-leading inspection, metrologyand analysis capabilities. KLA-Tencorhas worked closely with VARS for sev-eral years, developing data retrievaland archival capabilities for productssuch as the CRS Review Station andAIT Inspection System.

Autumn 1998 Yield

The VARS Image Management Systemstores and retrieves images generatedfrom a broad variety of on-line andoff-line equipment, including defectreview stations, scanning electronmicroscopes, metrology systems andfocused ion beam systems. Imagesand data are stored automatically ina single database and made quicklyavailable through powerful databasesearch engines. More than 60 sys-tems are installed in semiconductorfacilities worldwide.

Previously, fabrication plants usedPolaroid, video prints and other slowmeans of photography to documentchip defects and other anomalies.VARS revolutionized the imagingindustry by providing semiconductormanufacturers with a high-speed,high-capacity tool to display defectproblems on computer monitorsinstantly as they occur.

The VARS Image Management System.

Management Solutions 5

LITHOGRAPHY DEFECTS — THE HIDDEN

Autumn 1998 Yield Management Solutions6

SSttoorryyCover

YIELD KILLERS

Importance of Defect Reduction in the Lithography Module

by Ingrid B. Peterson, Ph.D.,KLA-Tencor Yield Management Consulting

ne of the most important chal-lenges in the implementation

and development of DUV andadvanced i-line lithography process-es is maintaining low-defect densityin order to minimize the impact onyield. As geometries shrink and chipsize increases, defect reductionbecomes increasingly critical. Thelithography engineer is now respon-sible for more than creating resistpatterns on wafers; defect density isnow just as important as criticaldimension and overlay metrology inthe development and implementa-tion of lithography processes.

Today’s lithography processes arevery complex, and most process flowshave twenty or more lithographysteps. Implementing these processessuccessfully requires attention toyield and device performance as wellas to critical dimensions and overlay.Lithography defects, therefore, canhave a great impact on wafer probeyields, preventing them from being100 percent, and thus impacting thecost and reliability of semiconductordevices. Even in the cases where lith-ography defects (equipment orprocess integration) appear to be cos-metic, the defects can have a 15-20percent impact on yield. Thesedefects are also very difficult todetect on product because they: 1)

O

have low topography; 2) opticallyappear as only a subtle color varia-tion; 3) are very small (<< 0.5 µm);and 4) in many cases, are not visibleunder optical review. Therefore,effective defect monitoring proce-dures need to be implemented(1,2)

and the defect inspection tool care-fully selected. Examples of some ofthese defects and their causes are pre-sented here in order to illustrate thenature of lithography defects,emphasizing their impact on yieldand the importance of using theappropriate pattern wafer inspectiontool to detect them. Also, this article discusses the importance oftest wafer monitors as a means ofdetecting these defects; however, thissubject is covered in more detail inReferences 1 and 2.

Autumn 1998 Yield

Figure 1. Example of a developer spot.

Low topography defects: developer spotsIn many fabs, a common problemthat frequently goes unnoticed is thepresence of developer spots, shown infigure 1. This defect is easily detect-ed on an unexposed, resist-coatedwafer that has been developed with astandard production recipe.Developer spots, caused by splash-back during the rinse cycle, are notvisible on bare-silicon wafers. This isa consequence of surface tension dif-ferences between a resist-coated

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wafer and a bare-silicon wafer.

Brightfield, narrow-band defectinspection tools are the best choicefor detecting developer spots sincethey are a low-topography, color-variation defect. The lack of scatter-ing edges on these defects preventsthem from being detected on dark-field laser light scattering inspectiontools. They vary in shape and size,from 1 to 20 µm in diameter; andthey occur on developer equipmentfrom different vendors. Possible

Figure 2. Wafer map showing the devel-

oper spots on the perimeter of the wafer.

anagement Solutions 7

Autumn 1998 Yie8

C O V E R S T O R Y

causes are poor exhaust in the devel-oper cup, developer cup design, andtype of developer nozzle. Thesedefects are commonly detected onthe perimeter of the wafer (see figure2). The light-colored spots are clus-tered defects and the dark-coloredspots are unclustered defects.

In-line monitoring of productionlots often shows that this defect typecan block non-aggressive etch steps,such as nitride and thin maskingoxides. An example of a defectblocking an etch step is shown in figure 3. In this example, thedeveloper spot was probably createdafter the wafer finished its developdrying cycle. This spot blocked thenitride etch and subsequently inhib-ited the growth of the field oxide.

Figure 3. Effect of a developer spot

on product.

l

Color variation defects: spotsThis general category of defectsincludes those that are generatedduring the coat process. Theydepend on the contact anglebetween the resist and developer andare residues generated by resist-developer interactions. Since thesedefects appear as color variations orstains on wafers, they are bestdetected by brightfield, narrow-band pattern wafer inspection tools.They are also best detected on resiston silicon test wafers, rather than onproduct wafers. The signal-to-noiseratio is very low on product wafersdue to the color variation contribu-tion from previous process levels anddefects from previous layers, causingthese defects to escape detectionduring after-develop inspect, ADI.

Figure 4. Spot defect type caused by

EBR splashback.

Figure 4 shows an example of a verycommon coat defect, EBR (EdgeBead Removal) splashback, whichleaves a stain on the wafer. The colorvariation represents resist thicknessvariations which cause CD variationsand pattern deformations on productand, therefore, impact yield.

d Management Solutions

The next example shows how verycosmetic-looking stains or spots canhave serious impact on yield byblocking contact or via openings.This defect type has been shown tocause yield losses up to 20 percent.The origin of the residue which caus-es the spots or stains varies. It can becaused by developer precipitates,resist-developer interaction or resistand developer surfactant bonding. Inmany cases the stain is so subtle itwill not be observed during opticalreview; it is detected only on bright-field inspection tools due to the highsensitivity of TDI (Time DelayIntegration) technology. Figures 5and 6 show this defect type blockinga contact opening.

Figure 5. Optical image of stain defect

blocking a contact ( from 2100 series

inspection system).

Figure 6. Results of a confocal microscope

scan of the defect in figure 5.

Figure 6 shows a confocal microscopescan of the blocked contact in figure5. As this scan clearly shows, the firsttwo contacts (left to right in figure5) are clearly open, the third contactis partially blocked, and the fourth iscompletely blocked.

The spatial distribution of this defecttype is very dense (as shown in

C O V E R S T O R Y

figure 7), radially outward, and fol-lows the pattern on the wafer. Thespatial distribution also is very usefulin identifying the defect sourcesbecause it gives clues to possiblemechanisms responsible for a partic-ular defect. In this case, it indicateshow this residue affected the waferduring the develop-rinse cycle.

Figure 7. Spatial distribution of the stain or

spot defect shown in figure 5.

E2 nozzle spatial distribution The next defect examples fall into avery characteristic spatial distribu-tion called the E2 nozzle spatial dis-tribution (shown in figure 8). The E2

nozzle is a proprietary means of dis-

Figure 8. E2 nozzle spatial distribution.

pensing developer used on TELtracks. This is a very clean type ofdispense; however, when it hasdefects, they tend to fall along astraight line, making it very easy todetect and trace back to the source. Itis important to point out that thedefect types which fall along thestraight line pattern occur on alldeveloper track equipment and arenot unique to the E2 nozzle means ofdispense. Only the linear distribu-tion is unique to the E2 nozzle.

The defect types seen with this kindof spatial distribution are: criticaldimension, CD variation, patternbridging, and extra pattern (shownin figures 9, 10 and 11).

Figure 9. Color variation defect.

Figure 9 shows an optical image of adefect that has the spatial distribu-tion of figure 8. The profile and CDof the contact features under the rosecolor are dramatically different thanthose under the green color. This is acolor variation defect detected onproduct after ADI and on test wafermonitors with a KLA-Tencor 2135.The test wafer monitors, resist pat-tern on silicon, provide much highersensitivity than the product inspec-tion. In the defect type pareto analy-sis chart, this defect was number onefor the test wafer monitor and num-ber eight for the ADI inspection onproduct, emphasizing the impor-tance of effective defect monitoring.

The residue causing the bridging ofthe pattern in figure 10 also has thespatial distribution of figure 8 andcan be caused by contamination ofthe developer dispense nozzle.

Autumn 1998 Yield

Figure 10. Residue defect.

Figure 11. Developer bubble defect.

Figure 11 shows another commondefect caused by the developmentprocess. This defect is a result of N2bubbles during the develop part ofwafer processing. These bubbles are aconsequence of supersaturation ofN2 in the developer liquid whichprevents the underlying area frombeing developed. The size of this

Management Solutions 9

C O V E R S T O R Y

defect varies from submicron diame-ter to as large as 10 µm.

The photo defects illustrated in thisarticle are ones that are usuallythought to be cosmetic; however, asshown by these examples, they canblock contacts, cause bridging, miss-ing or extra pattern and CD varia-tion. Because these defects are lowtopography, have low scattering crosssections, show color variations, or area consequence of resist film thicknessvariations, they are best detected bybrightfield, narrow-band patternwafer inspection tools, combinedwith effective test wafer monitorprocedures1, 2. Test wafer monitorsconsisting of resist pattern on siliconprovide much higher sensitivitiescompared to ADI on product.

The days are past when fab engineerscould concentrate on specific module

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parameters without considering thetotal impact on yield and productivi-ty3. In today’s highly competitivesemiconductor marketplace, both fabengineers and fab managers must beaware that lithography defects, evenseemingly cosmetic ones, can greatlyimpact a fab’s yield — and not onlythe right equipment, but also theright corrective actions must be inplace to prevent the catastrophicimpact on yield these defects can produce.

1 I. B. Ferreira, “Effective Defect Monitoring inPhoto and Etch.” KLA Yield Management Seminar,March 13, 1996.

2 I. B. Peterson, “Defect Reduction Methodology inthe Lithography Module.” KLA-Tencor YieldManagement Seminar, July 14, 1998.

3 Moshe E. Preil, Harry J. Levinson, “Yield-limitingIssues in Deep-UV Lithography.” MicrolithographyWorld, Spring 1998.

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About theAuthorDr. Ingrid B.Peterson joined KLA-Tencor’s YieldManagementConsulting Group in September 1995.Since then, she has developed and imple-mented yield management services in herarea of expertise at many customer fabs.Dr. Peterson previously was a staffprocess engineer in photolithography atSynergy Semiconductor and also at VLSITechnology where she helped drive defectreduction for all areas of the fab. From1987 to 1990, Dr. Peterson was a staffresearch scientist at the Max PlanckInstitute for Solid State Physics inStuttgart, Germany. Dr. Peterson earneda Ph.D. in Solid State Physics from theUniversity of California at Santa Barbarain 1987 and has published international-ly in several areas of Solid State Physics.

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LithographyF E A T U R E S

Stepper Focus Metrology andAnalysis Using a Phase Shift Mask

by Patrick J. Lord, Senior Product Marketing Manager and Michelle Zimmerman, Product Marketing Manager

Since the introduction of phase shifting masks, engineers studying this imaging technique have been aware that errors inthe phase of the mask (non-180 degree shifters) would cause asymmetries of the printed image as the image was defocused.These asymmetries would create a translational offset in the printed image as a function of the focus offset. The Phase ShiftFocus Monitor reticle is a tool which uses this effect for stepper diagnostic and calibration.1

The basic concept of the focus moni-tor reticle is simple and elegant. Abar-in-bar overlay target is written ona reticle. Both the inner and outerbars are printed at the same time,with part of the target phase shiftedby 90 degrees and the other partunshifted (figure 1). If the stepper isperfectly focused, the overlay errorwill be exactly zero in both x and y.If, on the other hand, there is a focuserror, the phase shifted half of theoverlay target will move relative tothe unshifted part; and the result isinterpreted as an overlay error whichis a direct measure of the focus error.Even though the method requires aone-time calibration between theactual focus and the overlay misregis-tration (figure 2), the linearity of thebehavior as presented in figure 3 is astrong advantage of the method. Asopposed to alternative solutions thatare quadratic in nature, the PSFmethod can easily detect small focuschanges about the optimal operatingpoint.

With the introduction of new analy-sis software, such as KLA-Tencor’sKLASS PSF, semiconductor manufac-turers have been quick to utilize thespeed and power of this new tech-nique. Unlike other focus techniques,which require qualitative estimates ofimage quality to determine the “best”

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focus position, the PSF method provides an operator-independent, quantitative measure of the best focusposition. In addition, the high throughput of overlaymeasurement tools compared to CD measurement systems such as SEMs makes it possible to measure the best focus at many positions within a lens field in a very short amount of time.

Figure 1. Typical phase shift mask focus target (courtesy of Benchmark

Technologies, Inc.).

Figure 2. Meander focus setup.

utumn 1998 Yield Management Solutions 11

F E A T U R E S

This new capability has allowedstepper engineers to apply the samemathematical rigor to focus analysiswhich has long been available forstudying overlay. Focus variationswithin the field and from field-to-field across a wafer can now be math-ematically modeled to determinelens tilt (figure 4), field curvature(figure 5), astigmatism (figure 6),wafer and chuck flatness (figure 7),the impact of lens heating and barometric pressure (figure 8), andother focus anomalies.

The speed of the overlay measure-ment tools also allow the engineer tomeasure several wafers to average outwafer flatness effects that would oth-erwise distort the data. The quanti-tative power of this technique is abreakthrough step in the analysis ofstepper focus. Used as a daily focusmonitor, it becomes an invaluablephase for any advanced process con-trol implementation targeting dosecontrol for improved critical dimen-sion performance.

Figure 3. Calibration linearity.

Figure 4. Field tilt analysis.

1 The Phase Shift Focus Monitor reticle is exclusive-ly available from Benchmark Technologies, Inc.

circle RS#027

Figure 5. Field curvature after removal of field tilt.

Figure 6. Lens astigmatism.

Figure 7. Wafer and chuck flatness.

Figure 8. Lens heating ef fects.

LithographyF E A T U R E S

Identifying Process Drift with CD SEMs

Getting more than critical dimensions from SEM linescans and images with correlation scoring

by David M. Goodstein, Applications Engineer

In situations where CD-only-based monitoring of process integrity proves inadequate, the CD SEM continues to provideessential monitoring capability through the use of linescan and image correlation metrics. This additional information isextracted from the same line scans and images acquired in the course of standard automated CD measurement.Consequently, there is almost no impact on throughput. The high sensitivity of these metrics to even small degrees of processvariability suggests they will play an important role in all demanding CD SEM-based process monitoring and controlapplications.

CD SEMs play an essential role in photolith-ography and etch process characterizationand monitoring. Post-develop (DI) and post-etch (FI) monitoring of device criticaldimensions (CD) as well as fast, thoroughcharacterization of processes and processequipment are routinely handled byadvanced high-throughput CD SEMs. Real-time process monitoring is especially impor-tant to catch yield-compromising processvariations as soon as possible, before a signifi-cant and costly fraction of in-process wafersare affected. While CD is the standard metricon which CD SEM monitoring is based,additional and potentially more sensitivemetrics are available from the very same tool.

To see why more sensitive monitoring met-rics might be necessary even at large designrules, consider the CD variation of an i-lineresist isolated line on metal as a function ofstepper defocus and exposure (figure 1). Witha nominal CD of approximately 540 nm (at 0 µm defocus, 190 mJ exposure), a DI moni-tor that flagged resist-line CD deviationsgreater than five percent would still allowsignificant process variation (figure 2).Process drift of this magnitude might wellimpact post-etch metal line CD and overallline integrity, compromising device perfor-mance and total yield. This can be avoided

with tighter process monitoring at the post-developstage, using non-CD-based metrics.

Limitations of CD-only monitoringIt should not be surprising that not all process drift can be identified by changes in critical dimension.Interconnects, gates, contacts and vias are fundamental-ly three-dimensional structures, and characterizingthem solely in terms of CD (which is itself a function of the measurement algorithm applied to the CD SEMimage or linescan) is necessarily a simplification. If adevice feature simply scales uniformly with processdrift, then CD is an adequate metric. However, this isoften not the case.

The limitations of CD-only characterization and moni-toring are evident in figure 3, where isolated end-of-linestructures are imaged by a CD SEM at 75kX magnifica-tion. Measurement linescans, acquired near the middleof the line, are also shown. The resist line printed at 1.2 µm defocus and 200 mJ exposure (bottom image)measures at 535 nm, a CD deviation of less than twopercent from nominal (543 nm). Such a line would passmost CD-only monitors, where process windows aretypically 10 percent of nominal. However, when com-pared to the line printed at optimal focus and exposure(top image), the non-optimal line clearly suffers fromreduced sidewall steepness (wider, but lower intensityedges) and variable resist thickness (bright fringes acrossthe line). These changes can lead to an appreciably

Autumn 1998 Yield Management Solutions 13

F E A T U R E S

different etch transfer function,which may unfavorably impact theresultant metal line and, therefore,the etch process yield.

The key to catching these types ofprocess variations is to monitor notonly feature CD, but a metric thatreflects overall feature fidelity aswell; such a metric should answerthe question: “How similar is the

Figure 1. Bosung plots of isolated line CD vs.

focus (in µm) for i-line resist on metal 1.

Figure 2. Wafer map showing deviation of

i-line resist on metal 1 isolated line CD from

optimal CD as focus and exposure vary. The

yellow field corresponds to optimal focus and

exposure, with a CD of 543 nm. The green

fields define the range of process conditions

that yield resist-line critical dimensions within

five percent of 543 nm.

Autumn 1998 Yield 14

feature under inspection to theoptimal one I am trying to manu-facture?” For CD SEMs, the mostaccessible metric of feature fidelityis linescan or image correlation,calculated against a reference oroptimal template. It utilizes thesame linescans and images that areacquired during the course of auto-

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mated measurement and has theadded advantage that, unlike CDmeasurement, it is an algorithm-independent metric of a feature’sfaithfulness to a standard.

The one-dimensional correlationbetween the non-optimal and optimal measurement linescans(bottom right), and the two-dimensional correlation between the non-optimal and optimal end-of-line images (bottom left), are displayed in figure 3. These low correlations (compared to thosein figure 4) should raise a red flagthat significant process drift hasoccurred, even though the CDs atthis process step remain in spec.

Further evidence of the potentialpower of correlation-based monitor-ing is shown in figures 5a and 5b,where image correlation, linescan

anagement Solutions

correlation, and CD correlation(defined as one minus the absolutefractional CD deviation from opti-mal) are plotted for varying defocusat optimal focus (figure 5a) andvarying exposure at optimal focus(figure 5b). In both cases, correlationscoring provides a more sensitivemeasure of process drift than CD.

The effect of establishing an 80 percent threshold (20 percentdeviation) on linescan correlation for this layer is shown in figure 6.Correlation scoring clearly facilitatesmore precise monitoring of processdrift than CD measurement alone.

Figure 3. A comparison of end-of-line images and measurement linescans from the isolated resist

lines of figures 1 and 2. Focus and exposure conditions are indicated in parentheses.

Optimal Field(0.0 µm, 190 mJ)

CD = 543 nm

Inspection Field(-1.2 µm, 200 mJ)

CD = 535 nm

Correlation

Fully automated correlation monitoring The power of correlation-basedmonitoring would be of little bene-fit if it could not be implementedwith the same level of automationand speed as CD-based monitoring.In fact, linescan and image correla-tion monitoring on the KLA-Tencor8100XP can be integrated seamless-ly into normal automated CD measurement, and provides:

• Real-time calculation, reportingand output to measurement data

F E A T U R E S

files of linescan and image corre-lations against user-defined optimal templates.

• Automatic acquisition of sub-optimal linescans and images,based on user-defined thresholds,for subsequent review.

This is accomplished with near-zero impact on throughput inautomation.

Correlation monitoring is, by nomeans, limited to the example dis-cussed here. Dense lines, contacts,other layers, and the smallest design

rules are all accommodated in the current implementation on the 8100XP. Depending on theapplication, acceptable correlationthresholds can be determined andsubsequently enforced in conjunc-tion with standard CD monitoring.When fully integrated into CDSEM-based, closed-loop advancedprocess control, correlation providesan even more powerful tool formaintaining lithographic processintegrity and achieving maximumyield. As device geometries contin-ue to shrink and process windowscontinue to narrow, correlationmonitoring, as well as other

Autumn 1998 Yield

Figure 6. Wafer map showing linescan corre-

lation score grouping as a function of focus

and exposure dose. The yellow field corre-

sponds to optimal focus and exposure. Taken

together, all colored fields define the range

of process conditions that yield at least 80

percent linescan correlation.

linescan- and image-based characterization methods,1 will be a critical part of every successful CD SEM-based yield monitoringsystem.

1 J.M. McIntosh, et. al., “Approach to CD SEMMetrology Utilizing the Full Waveform Signal,” SPIE Proc., 1998.

circle RS#009

Figure 4. A comparison of image and measurement linescans between optimal and near-optimal

resist lines. Note the significantly higher linescan and image correlations as compared to those

in figure 3.

Optimal Field(0.0 µm, 190 mJ)

CD = 543 nm

Inspection Field(-0.3 µm, 190 mJ)

CD = 558 nm

Correlation

Figure 5. a) Variation of isolated-line CD correlation (one minus absolute fractional deviation from

nominal), image and linescan correlation at optimal exposure (190 mJ) as a function of defocus.

b) Variation of isolated-line CD, image and linescan correlation at optimal focus (0.0 µm) as a

function of exposure dose.

Manag

The author wishes to thankBhanwar Singh and Bryan Chooof Advanced Micro Devices forproviding the initial impetus forthis investigation, as well as pro-viding the focus-exposure wafersused to generate these results.

ement Solutions 15

LithographyF E A T U R E S

Analysis of ESD-InducedReticle Defectsby Jim Reynolds, Reynolds Consulting

In semiconductor manufacturing, the effects of static charge are particularly critical in the photolithography area. The photoprocess involves step-and-repeat operations using reticles. A damaged reticle can result in thousands of defective products.Due to the small dimensions and non-conductive substrates on the reticle, electrostatic discharge (ESD) can occur, causingsignificant yield losses. The present study was made as the result of just such an occurrence. The observed production yieldloss was eventually traced to multiple ESD events, which caused pattern damage on the reticles. Some recommendations tothe problem of reticle ESD damage are proposed.

1

IntroductionReticle deterioration over time has longbeen a concern of the wafer lithographer.Since the advent of the wafer stepper in theearly 1980’s, events such as pellicle break-age, crystal growth under the pellicle, andelectrostatic discharge (ESD) have created alow incidence of extremely expensive prob-lems. The consequences of an undesiredchange on the image surface of a reticle cancause problems ranging from downgradedproducts to 100 percent yield loss. Isolatingthese losses to a damaged reticle can be verydifficult and time consuming. Many semi-conductor lithographers prefer periodicreinspection of reticles to the disastrouspossibility, however remote, of undetectedreticle damage. In 1997, a large Europeansemiconductor manufacturer observed theyield on an established product drop to zeropercent over a short period of time. Thisarticle is a discussion of that event and ofways to minimize the potential damage thatcan be caused by ESD.

Reticles and ESDStatic charge is most commonly generatedby triboelectric charging. Whenever twodissimilar materials are in contact and sepa-rated, a charge exchange occurs between thetwo surfaces, resulting in two oppositely

Autumn 1998 Yield Management Solution6

charged objects. Once an object becomes charged, itmay transfer its charge directly to another object.Induction charging can also occur when an isolatedconductive object is brought near another chargedobject, without actually touching it. At any time whentwo objects, with a potential difference large enough tobreak down the insolating path that separates them,come close together, current will flow causing an ESDevent.

As a practical matter with reticles, the sources of chargeare ubiquitous and the gaps over which discharge canoccur are small now and getting smaller. Charges canbuild up on garments, work surfaces, packaging mate-rials and air streams, just to name a few possibilities.Fab environments are normally dry with relativehumidity at 40 percent or below and rapidly movingair. The quartz substrates used on most photomaskshave a very low surface conductivity, allowing puddlesof charge to build up on different areas of the reticle.Voltage differences of 5-8,000V are not uncommon onthe surface of a reticle. The chrome which defines thepattern can conduct a high voltage to a region on themask where the electrostatic potentials are lower. Ifchrome, run at a high potential, comes into close proximity of another at a lower potential, the resultinghigh electric field gradient will cause ESD. When thishappens, extremely high temperatures are generatedwhich melt both chrome and, in some cases, quartz,causing an undesired modification of the pattern. Thisreticle damage can occur over time (with small ESDevents) and in varying degrees of severity.

s

F E A T U R E S

Case studyProduction yield losses at a major semiconductor manufacturer prompted the current investigation. Thecause was arduously traced back to one of the reticlesused in the photolithography process. We inspectedthe two-die reticle using a KLA-Tencor STARlight system and examined both the individual defects andthe pattern of defects.

Several levels of damage were discovered on this reticle.Figure 1 shows slight damage of the antireflective layerwhich lies on top of the chrome. This precursor to ESDwas visible on the STARlight, even though this sectionof the reticle would probably go undetected on a pat-tern defect inspection system and would print normal-ly. This level of damage can exist on a reticle that doesnot have additional damage, providing a means of earlyidentification of a reticle that is prone to more cata-strophic ESD.

Figure 1.

Figures 1-3. Progressive examples of ESD damage on advanced reticles.

Figure 2. Figure 3.

Figures 2 and 3 show regions of the same reticle withincreasing levels of ESD. Both show evidence of rapidcurrent flow, coupled with deformation of the chromeimage. This current has produced melting of both thechrome and quartz substrate. In figure 2, a small tailemerges from each side of the gap with a transmissionof around 72 percent, as measured on the STARlight.In figure 3, a bridge with 53 percent transmission isfound. Both of these cases would have produced bridg-ing when printed on a wafer. Figure 4 is an atomicforce microscope (AFM) rendering of the defect in figure 3, clearly showing the physical topology of theregion.

All three of these cases met the classic ESD require-ments. Long conductors came from a distant part ofthe plate, bearing the potential of a charged region. A small gap separates them from a relatively short conductor which bears the potential of the local region.

When the potential of the distant region approaches orexceeds the breakdown voltage, the ESD shown in figures 1-3 occurs.

Living with ESDAs long as photomasks are made of conductive chromeon non-conductive quartz substrates, the potential forESD exists. It is up to the reticle maker and user tominimize exposure to this problem and the damage itcan cause. The most direct method is to add conductiv-ity to the air surrounding the reticle. This can be donewith electronic air ionizers in front of the HEPA filterssupplying air to the workstations where reticles arehandled or used. Increasing the relative humidity asfar as possible (50-55 percent) provides additional protection. Even with these measures, the only way toprevent yield loss due to ESD on reticles is to reinspectthe reticles periodically using a STARlight or similarsystem.

circle RS#033

Figure 4. AFM rendering of the bridge defect shown in figure 3.

17Autumn 1998 Yield Management Solutions

Now that the world is movingbelow 0.18 µm, things are really going

to get ugly. To survive, you’llneed to see just what you’reup against.

That’s the idea behindour new 353UV, the industry’sfirst and only reticle inspec-

tion system for deep UV lithography.Thanks to a series of engineering

breakthroughs, its shorter wavelengthlets you see photomask patterns withthe high resolution needed for criticalUV inspections.

In fact, with unprecedented 0.15 µm sensitivity, the 353UV can discern the finest details on the most

complex photomasks, and uncoversubtle anomalies that otherwise couldn’tbe found. At the same time, it candetect whole new classes of defects thatare just now impacting yield.

Plus, by combining all this withadvanced new algorithms, the 353UVmakes it easy to capture even the mostsubtle defects on OPC and PSM reticles.

Now you can have the tools toview deep UV reticles with a startlingdegree of clarity — even though youmight not always like what you see.

For more information, please visitwww.kla-tencor.com/353uv.

We can’t promise you’ll like what you see on your reticles.

( But we can promise you’ll see it.)

Yield-killing OPC.

©1998 KLA-Tencor, Inc.

S E C T I O N S

Industry ViewpointBridging the Gap to 300 mm Wafers

By Dan HutchesonPresident, VLSI Research, Inc.

Is the transition to 300 mm wafers dead? Have the highcost of 300 mm tools and the current industry down-turn ended wafer-size transitions? No, but these factorshave caused the industry to look for more cost-effectivetransition strategies. One of the most promising strate-gies is the development of bridge tools.

The transition to 300 mm wafers has been identified as akey step in maintaining profitability in an era of shrinkinggeometries and increasing device complexity.Unfortunately, higher costs paired with the current downturnhave prevented the industry from simultaneously transition-ing to both 300 mm wafers and the 0.25, 0.18 or 0.15 µm device generations as previously expected. Thenext window of opportunity will occur around 2001-2004, coincident with the adoption of the 193 nm lithog-raphy tools needed to manufacture 0.13 and 0.10 µmdevices. If the industry misses that window, I believe it willbe the end of wafer-size transitions.

The shift to 300 mm may be even more difficult to accom-plish in 2001 than it would have been now, if it requiresextensive construction of new fabs. Although I expect theindustry to be in a strong upturn by that time, it will still befinancially strapped as it attempts to both increase capac-ity for existing generation products and finance the transi-tion to 0.13 geometries for advanced devices. It is, there-fore, critical that we find a low cost, low risk means of

A

facilitating this transition; and I believe bridge tools are thesolution.

To deliver on that promise, bridge tools must meet three key criteria. They must have the ability to handle either200 mm or 300 mm wafers with easy upgrades. For anygiven process, the 200 mm version of the bridge tool mustdeliver a combination of footprint and throughput thatresults in a smaller floor space requirement than that of theprevious generation of 200 mm tools. Finally, the cost ofownership for a 200 mm bridge tool at a particularprocess step must be less than that of the current genera-tion of 200 mm tools.

If the industry begins the shift to bridge tools now, it shouldbe able to surmount the key challenges I expect it to facein 2001. It will be able to respond quickly to increaseddemand for capacity by transitioning from 200 to 300 mmwafers without incurring massive construction costs. Inaddition, it will have production-proven 300 mm platformsthat will help speed the ramp to full yield for new 0.13 µmadvanced devices — a critical factor both in meetingdemand and increasing profitability.

G. Dan Hutcheson is president of VLSI Research, Inc.,a company specializing in market research and economic analysis of the semiconductor manufactur-ing industry.

utumn 1998 Yield Management Solutions 19

AnalysisF E A T U R E S

Image Management: A New Approach forYield Analysis by Bert Plambeck, Program Manager

As volumes of defect data are generated in the semiconductor manufacturing process, manufacturers look to sophisticatedsystems that can help extract meaningful information needed for rapid analysis and resolution of yield problems. Beingable to quickly determine the root cause of a yield excursion or a process problem is the essence of yield engineering. WhileSPC or pareto charts help yield analysis, review of images generated by the inspection, metrology or failure analysis toolsduring the fabrication process can help expedite the process of determining of the root cause of a yield excursion. With theaddition of the VARS image management system to its suite of yield enhancement solutions, KLA-Tencor enhances the capability of its inspection and metrology systems and increases the overall value of its solutions to customers.

A20

Image management is becoming anincreasingly important part of thediagnostic process, providing criticalinformation about the nature andsource of yield-limiting process problems. Defect images are valuablein process analysis. For instance, aCD SEM edge profile image illumi-nates information derived fromBosung curves, and overlay imagestaken across the wafer can visuallyquantify CMP process uniformity.Collecting images one at a time onpolaroids and storing them in bindersin the lab were helpful to yield engi-neers in the past. However, as time-to-information becomes ever morecritical to resolve yield problemsquickly, going through binders ofpolaroids and unorganized data filesto identify images associated with the defect under review has become a laborious and time-consuming exer-cise. Manual image storage methodsdo not facilitate easy informationaccess, information sharing or transferwithin or between fabs necessary for

utumn 1998 Yield Management Solutions

rapid resolution of yield problems. For images to bemeaningful, it is important that they are captured fromthe inspection and metrology tools, saved along withthe associated defect data and made available instanta-neously to engineers or the yield management system.

The VARS systemThe VARS image management system stores andretrieves images generated from a wide variety of on-line and off-line equipment including defect review stations, scanning electron microscopes (SEM),metrology equipment and focused ion beam (FIB) systems. With a large online capacity expandable tohold millions of images, it links all the image gatheringtools in the fab to a single database allowing economicalstorage and fast access and retrieval of images alongwith the relevant inspection data. User stations at eachimage-generating tool are utilized for image acquisitionand transfer to VARS’ central host for storage and distribution. Once stored, images can be reviewed one-at-a-time with a one-second retrieval time or as agallery of images created using user-defined search criteria. Images can be easily imported into reports andprinted in full color or black-and-white with printeroptions that allow the user to include image related dataon the image printout.

F E A T U R E S

Figure 1. VARS connectivity in a fab.

Figure 2. VARS user inter face.

Control Panel allows users to record or playback inone second, perform multiple parameter searches,display selected images in gallery format, imagetag list, view another station’s live video, enableautomatic data interface from other vendor’s inspec-tion tools.

Data Window shows user-definabledata structure which allows users to savedata associated with the defect imageunder review.

Image Window displays images select-ed by user for record or playback.

Whether within a single fab orbetween fabs located half a worldapart, VARS enables and enhancescommunication. Web access can beadded to the VARS host that allowsusers to access/download data andimages stored on the host using anInternet browser. Within seconds of addition of images to the VARSdatabase, they become available to any authorized person in thecompany via the Intranet or theInternet. Users can format theimage browser screen to displayimages and the associated defectdata. Access is controlled throughpassword protection. A key advan-tage which an image managementsystem provides is the transfer ofyield and process examples from anestablished fab to a remote fab. Ayield engineer can search a remotedatabase for defects that are similarto those appearing in the local line.When a match is found, the causeand corrective action can be deter-mined from engineering analysisdone previously, saving time andeffort.

Autumn 1998 Yield M

Imaging the futureImages will play an important rolein fabs in the future. Multiple toolsacross the fab are generating greaterand greater volumes of images —images, that when stored and managed efficiently, can providesolutions to current problems andopportunities for optimizing yield inthe future. As inspection, metrologyand yield enhancement systemsbecome fully integrated, images will add a new dimension to yieldmanagement — when available in real time, images will support, clarify and expedite the analysis of yield limiting problems. VARS is the springboard for creating a complete image management system for the fab of the future — a systemthat will enable better process visualization, whether the process is in a fab across the hall or an operation half the world away.

anagement Solutions 21

22

AnalysisF E A T U R E S

Yield Enhancement with Bitmap Analysis

by Ken Bernstein, Program Manager

Review of failing bit data collected by automated test equipment (ATE) is an essential tool used by engi-neers to improve the yield of memory arrays. While visual inspection of this data provides the engineer withthe locations of failing bits, analysis of the failing bit patterns can help pinpoint the cause of bit failures.

With the introduction of KLA-Tencor’sBitPower™ Analysis System, bitmapanalysis has transitioned from an off-line engineering function into an ongoing manufacturing process foryield improvement. With this system,bitmap data is collected during production test, failing bit patterns areautomatically extracted, and the data is passed to Klarity™, KLA-Tencor’sautomated analytical software module,where it is analyzed in conjunctionwith the physical defect data collectedat in-line inspection points. Suchanalysis helps correlate defects detectedearlier in the manufacturing process toan electrical failure identified at theend of the process. This bitmap linemonitor is illustrated in figure 1. Whenoff-line engineering analysis isrequired, KLA-Tencor’s BitPower System provides powerful bitmapreview software for full reproductionand visualization of failing bit data andtheir exact topological locations, thuspreserving the ability to view originaland absolute bit coordinates.

Autumn 1998 Yield Managemen

Bitmap line monitor step 1: Data collectionAs the first step in implementing the bitmap line monitor, theKLA-Tencor BitPower system collects raw electrical bitmap datafrom the ATE. Memory testers are the traditional source of bitmapdata; but with the memory content rising in non-memory devices,it has become increasingly common for logic and mixed signaltesters to have the ability to produce bitmap data. KLA-Tencor’sBitPower system can accept data from any of these sources.

Automatedtest

equipment

Automatedtest

equipment

Automatedtest

equipment

InspectionTool BitPower Analysis System

(a)

(b)

(c)

(d)Klarity Automated Decision Flow Analysis

Fab Wafer Sort

Figure 1. (a) KLA-Tencor’s BitPower system collects data from ATE. (b) Bitmap data

is converted from electrical to physical coordinates and bit patterns are extracted.

(c) Physical bit pattern data is transmitted to Klarity. (d) Klarity can analyze the bitmap

data in conjunction with other data sources.

t Solutions

F E A T U R E S

Bitmap line monitor step 2: Electrical-to-physical conversionIn order to understand the cause of an electrical failure of a die, it isimportant to pinpoint the exactlocation of the failure point on thatdie. Converting electrically failedbit data into meaningful, physicallycorrect coordinates has traditionallybeen a time-consuming and error-prone process due to complex inter-nal address scrambling of the mem-ory arrays. The BitPower systemprovides revolutionary new utilitiesthat allow the user to easily createdie models that perform the map-

ping between electrical addressingand physical coordinates. Any dietype can be modeled, includingthose with multiple on-board mem-ory arrays such as DSPs and micro-processors.

As the physical data is created, theoriginal electrical data is not dis-carded. Instead, it is compressed and saved to allow off-line manualanalysis of the bitmap data withBitPower’s Bitmap ReviewSoftware. Such analysis is oftenrequired to review optically invisi-ble defects that have resulted in theelectrical failure of a die. The soft-

Autumn 1998 Yie

ware allows the user to view failuresat the wafer level or the die level.The wafer-level bitmap viewer (figure 2b top image) is capable ofdisplaying the bitmap data acrossthe wafer. The die-level bitmapviewer (figure 2b lower image) pro-vides the more traditional die andsub-die-level bitmap representation.

Figure 2b. Top: BitPower’s wafer level bitmap viewer shows the location

of the electrical failures. Bottom: BitPower’s die/sub-die level bitmap

viewer lets the user precisely locate the positions of failing bits and to

view failing patterns at the bit level.

Figure 2a. Top: Physical wafer map from inspection sys-

tem. Bottom: Exploded view showing die level defects.

Figure 2. Conversion of physical defect data to topological location of a bit failure.

l

Bitmap line monitor step 3: Bit-pattern extractionAfter the bitmap data is convertedinto physically correct coordinates,it can be searched for patterns such

d Management Solutions 23

F E A T U R E S

CU

0

as single-bit failures, word-line failures, bit-line failures,etc. Each of these patterns provide clues to the potentialcause of the failure at specific process steps. For example,a paired bit failure may be indicative of a missing fieldoxide or a failing word-line could be indicative of miss-ing contacts.

Failing bit patterns vary by product. Circuit design, circuit layout, and process technology all play a part indetermining the likely patterns that occur in a memoryarray. The BitPower system allows the user to create custom pattern descriptions for each device type.

The final step: Automated analysisOnce extracted, the failed bit patterns are transmitted tothe Klarity automated yield analysis system for furtheranalysis and correlation to defect data obtained frominspection points. Klarity accepts the bitmap data fromthe BitPower Analysis System as it would from otherdata sources within a fab. The bitmap data can be incor-porated into Klarity’s unique Decision Flow Analysisrecipes for automated monitoring and analysis (figure 3).For example, recipes can be generated according to user-defined criteria to automatically trend failed bit classifi-cations, identify repeating failure patterns, identify bit

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failure excursionsand send notifi-cation of suchexcursions tointerested partiesin the fab automatically.

The combinationof BitPower dataand in-lineinspectionresults providesKlarity withpowerful infor-mation required to determine the relationship betweenin-line defectivity determined earlier in the process/line,and bit failure patterns extracted by BitPower fromelectrical tests at the end of the process. Based on corre-lation results, Klarity’s built-in use of conditionals andfilters allows selected wafers from a lot to be sent for further SEM review or failure analysis.This helps faster identification of the process zones contributing to yield loss, improves failure analysis effi-ciency and accelerates resolution of the yield problem.

Figure 3. Regular monitoring of failed bit pat-

terns extracted with BitPower can identify out-

of-control conditions.

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bit

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Lot 1 Lot in control

excursion from typical

For more information call 800.450.5308

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InspectionF E A T U R E S

Inspection Implications of a Design-Rule Shrink

by Mark Keefer, Technical Marketing Manager

The current semiconductor business environment has caused most semiconductor manufacturers to postponenew fab construction or expansion of existing fabs. However, competitive pressures require improved, morecost-effective manufacturing processes. One way to achieve higher revenue is to produce more die per wafer.As the transition to 300 mm wafers is delayed, alternative approaches to increase the number of die perwafer are occurring: decreasing the design rule of the circuits (linewidth “shrinks”) and product redesign(compaction). Two benefits can be realized — the increased circuit density results in increased capacity (number of die per wafer start), and shrinks can also improve device performance, which allows higher aver-age selling prices. Shrinks are cost-effective since they do not require an entirely new processing equipmentset (except photolithography). As minimum feature sizes shrink, IC manufacturers face an increasing chal-lenge to maintain and increase wafer yields and chip performance. New process technologies may have impli-cations for the existing metrology and inspection equipment. Since smaller feature sizes are susceptible to elec-trical faults induced by smaller defects, defect inspectors must become more sensitive.

Cost-effectiveness can be achieved in part byextending existing capabilities, rather thaninvesting in a completely new equipmentset. Defect inspection systems and strategiesare changing to support shrinking designrules, and to accommodate new technologiesor materials, as well as increased financialconsiderations. In-process wafers have moredie per wafer and, therefore, higher value,requiring optimal defect inspection andsampling plans to decrease the amount ofproduct at risk due to an undetected yieldexcursion.

Processing and defect inspectiontrends of linewidth shrinksThe 0.5 to 0.35 µm process shift is charac-terized by adoption of oxide CMP processingand use of i-line lithography on critical layers. Global planarization by CMP is anenabling technology for the transition to0.35 µm and below linewidths. The flatterwafer surface enables finer resolution ofdevice features by reducing the stepper

depth of focus requirement. However, new yield-limit-ing defect types introduced by the oxide CMP processinclude residual slurry, microscratches, and surfacevoids.

The 0.35 to 0.25 µm process shift is characterized byadoption of tungsten CMP steps, use of DUV lithogra-phy, new inter-layer dielectric (with low dielectric con-stant k) and interconnect materials, and shallow trenchisolation replacing LOCOS for tighter packing density.Additional defect types introduced by the metal CMPprocess include residual tungsten (puddles or stringers),recessed or cored plugs, and metal dishing and oxideerosion. The use of anti-reflective layers results in othernew defect types such as pinholes. Inspection trendsinclude the initial use of patterned wafer tool monitor-ing (reduced use of unpatterned monitor wafers), andinitial use of automatic defect classification (ADC) inproduction.

The 0.25 to 0.18 µm process shift will probably incor-porate an unprecedented number of material and pro-cessing changes. It will likely see some combination ofCu interconnects and low k dielectric materials in adual damascene architecture that replaces metal etch

Autumn 1998 Yield Management Solutions 25

F E A T U R E S

and oxide CMP with oxide pattern-ing and metal CMP low energyimplants for ultra-shallow junctions,and step-and-scan DUV lithographycoupled with resolution enhance-ment techniques. The increasedvalue of wafers in process may alterinspection strategies. More fabs willadopt patterned wafer tool monitor-ing and, also, introduce photolitho-graphy cell monitoring to providehigh sensitivity inspection andrapid feedback.

Inspection technologyenhancementsMany of the new processes in usetoday, such as CMP, result in newdefect types. Killer defects must bedetected with high confidence,which requires a clear distinctionbetween defect signals and “noise”induced by process variations, suchas film thickness variation and grainstructure. Brightfield imaginginspection systems compare gray-scale intensity levels from cell-to-cell or die-to-die and interpret dif-ferences as possible defects. Colorvariations that result from filmthickness variation result in achange in gray-scale levels. Thisnoise reduces the sensitivity of theinspection system by raising theminimum threshold level requiredto interpret a difference as a defect.Metal grain structures have thesame effect: creation of additionalnoise, potentially resulting in nui-sance defects. Laser scattering sys-tems also rely on detecting differ-ences between die-to-die compar-isons. Process variations that areunaccounted for result in having toset the detection thresholds higher,reducing inspection sensitivity.

Inspection system technology hasbeen developed to reduce the effectsof process noise on the inspectionprocess. Two key improvements areultra-broadband brightfield illumi-nation and Segmented Auto-Threshold (SAT). Using broadband

Autumn 1998 Yield M26

illumination rather than monochro-matic reduces the effects of colorvariation resulting from thicknessvariation. Not only does this resultin increased defect capture rate withlower nuisance defect counts, but italso results in more robust waferalignment. In some cases, the reduc-tion in color variation results in suf-ficiently increased defect capturerate that a larger pixel size can beused for inspection, increasing system throughput and loweringcost of ownership1.

SAT is an image processing tech-nique for die-to-die (random mode)inspections that increases sensitivityon wafers with grainy metal andcolor variations typically seen inCMP processes. SAT algorithmspartition the wafer image into mul-tiple segments based on mean andrange pixel values for each pixel(figure 1). Then, a different thresh-old value is applied to each seg-ment, and the threshold value isdynamically adjusted during theinspection. Lower thresholds areapplied to areas with lower noise,maximizing defect capture whilereducing nuisance defect counts. Ina metal etch inspection on grainymetal, the use of SAT to suppressnuisance defects resulted in severaltimes higher defect capture as com-pared to non-SAT inspection2.

Figure 1. The SAT algorithm segments the dif ferent images used in die-to-die processing based on

the mean and range value of each pixel. In the above example, two segments are used.

TDI Digitized Image Segmented Image

High capture of all yield-relevantdefect types alone is not enough.Defect detection must be comple-

anagement Solutions

mented by integrated classificationand analysis tools that quickly con-vert defect data into correctiveactions. IMPACT/ Online™ ADC,in production use, aids in processcharacterization and rapid identifi-cation of process excursions. Defectsare classified quickly and accurately,and the results are sent to defectdata management systems such asQuest/ Klarity for defect clustering,layer analysis, defect type trending,and SEM review sample selection.ADC greatly surpasses the speed

and accuracy of manual classifica-tion, and defect trending by defecttype reveals excursions missed whentrending by total random defectcount alone3. As linewidths shrink,smaller inspection pixels are used(since yield-limiting defects aresmaller), and trending by defecttype (rather than total defect count)reduces the number of lots at risk4.The ADC system uses brightfieldimage processing algorithms similarto the inspection equipment, so thedefects can be re-detected in spite ofimage differences introduced byCMP color variations.

Patterned wafer tool monitoringDefect inspection can be broadlydivided into three categories:process line monitoring, processequipment monitoring, and engi-neering analysis applications.Process line monitoring typically

F E A T U R E S

uses high-resolution brightfieldimaging systems on product orshort-loop patterned test wafers.Equipment or tool monitoring typi-cally uses darkfield laser scatteringinspection of unpatterned monitorwafers. An opportunity exists forcost reduction in the equipmentmonitoring area by inspecting product wafers. The NationalTechnology Roadmap for Semiconductors(NTRS) calls for a reduction in testwafers from 33 to 28 percent for the 0.25 µm to 0.18 µm technologygeneration5. Benefits of patternedwafer equipment monitoring are amore accurate representation of thetrue process (shows process integra-tion failures), cost savings by reduc-tion of monitor wafers, and the ability to use the same inspectionsfor device monitoring, which aids indefect source analysis and yield prediction6. Patterned wafer toolmonitoring also reduces processexcursion detection time, reducingthe amount of product at risk — animportant consideration for high-value wafers. Tool monitoring canalso improve process equipmentoverall equipment effectiveness(OEE), by optimizing the timebetween preventive maintenance.

Probe

Yiel

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Figure 2. Each new device generation requires that yield ramps become steeper and probe yields

at transfer from pilot line to production become higher. (Source: VLSI Research)

Required MonthsProduct current requiredyield rate of to reach

Product at transfer change 80% yield

1Mb DRAM 8% 7% 404Mb DRAM 10% 8% 32

16Mb DRAM 15% 14% 1864Mb DRAM 20% 16% 12

256Mb DRAM 45% 21% 6

Photo-cell monitoring The majority of capital investmentin a linewidth shrink is in pho-tolithography. Benchmarking the defectivity of new lithography technology is essential for fast yieldramps. The critical defects scalewith the design rule, requiring highsensitivity inspection. Defect evalu-ation for a new lithography processon product wafers is difficult due topattern complexity, previous layerdefects and process noise; and itbecomes more difficult with eachsuccessive mask layer. Back-end layers with multi-level metallizationand CMP thickness variations exac-erbate the problem. Use of a short-loop photo cell monitor (PCM)wafer avoids these issues. Siliconwafers are fully processed throughthe photo cluster — coat/expose/develop — using the same processconditions (resist and design rules),except that stepper focus and expo-sure settings are optimized for bare-silicon wafers. Photo cell monitorscan be inspected with high sensitiv-ity, due to low process and substratenoise, allowing higher defect cap-ture than is possible on after-devel-op inspection (ADI) productionwafers. High-resolution brightfield

Autumn 1998 Yield

inspection (small pixel size) is ableto detect photo defects such asdeveloper spots that are low topog-raphy and/or have subtle color varia-tions. The advantage of a photo cellmonitor, compared to individualphoto tool monitors, is that inspec-tion time is significantly reducedand fewer wafers are required.Sampling frequency can be deter-mined statistically, based on thenumber of excursions detected.Application of this technique hasrecently been described7.

Impact of product mix oninspection systems With the decline in DRAM pricesdue to overcapacity, many semicon-ductor memory manufacturers arediversifying their product mix toinclude logic devices to achievehigher profitability. Given the cost-sensitive nature of DRAM manufac-turing, inspection systems dedicatedto inspection of memory arrays weredeveloped that offer cell-to-cell(array mode) inspection only, with areduced selection of pixel sizes.Logic products have large areas ofthe die that are not repetitive cells,requiring the use of die-to-die (random mode) inspections for com-plete die coverage. Logic productdesign has been driven by intercon-nect complexity, leading to multiplelevels of metal and the use of CMPas the global planarization tech-nique. Inspection of logic devicesand/or devices processed using CMPbenefits from die-to-die mode andsuppression of process noise usingtechniques such as broadbandillumination and SAT algorithms.

Importance of fast yieldrampingControlling and reducing defect levels becomes more important aslinewidths decrease, for both devel-opment and production. Delays infinding and solving defect problemsduring development can delay the

Management Solutions 27

F E A T U R E S

product transfer to manufacturing.Figure 2 shows the importance ofyield ramping as a competitiveadvantage. As the industry moves tothe next linewidth generation, boththe initial production yield and theyield ramping rate are critical, espe-cially as DRAM profitability hasfallen severely8. Yield modelingilluminates the significant dollarsavings that can be achieved with afast, successful yield ramp (figure 3).Key to rapid yield improvement isthe rapid identification of yield-limiting systematic and randomdefects, so that engineeringresources can focus on fixing problems.

Revenue lost = $32 M6 monthsLearn rate/month = 24%

Revenue lost = $161 M12 monthsLearn rate/month = 13%

Revenue lost = $403 M18 monthsLearn rate/month = 9%

ENTITLEMENT YIELD: Do = 1.60/cm2

55%

50%

45%

40%

35%

30%

25%

20%

15%0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

PRESENT YIELD: Do = 1.60/cm2

ASP/Wafer [@ present Do] = $5,800

Wafer starts/month = 0.3K to 10K (12 months)

Wafer Dia = 200 mm Die area = 1.63 cm2

T I M E T O R E A C H E N T I T L E D Y I E L D ( M O N T H S )

PR

OB

E

YI

EL

D

(N

DP

W)

YIELD MODEL: SEEDS (α = 1.0)

Figure 3. Achieving competitive yield learning rates can potentially save hundreds of millions of dollars.

SummarySemiconductor manufacturers aredecreasing design rules to reducefabrication costs by producing more

Autumn 1998 Yield M28

die per wafer, and to increase prod-uct performance. With each tech-nology generation, it becomes moreimportant to achieve high yieldsquickly and sustain yield in manu-facturing to ensure profitability.Processing changes associated withlinewidth shrinks may requireinspection system enhancementssuch as broadband illumination,SAT, and ADC to extend the life ofinspection solutions. The increasedvalue of each in-process wafer mayforce rethinking inspection strate-gies, such as adopting patternedwafer tool monitors or implement-ing photo cell monitors.

1 Metteer, B. et al, “TI MSTC/DP1 Evaluation ofthe KLA-Tencor 2138”, proceedings of KLA-TencorYield Management Seminar, Austin, TX, 1997.

2 Garver, J., Keefauver, K., Tinker, M., ImprovedDefect Detection Performance at Metal andContact Etch Levels Using a New, Optical

anagement Solutions

Comparison, Segmented Auto-ThresholdTechnology, SPIE Vol. 3050, pp. 452-463, 1997.

3 Breaux, L., Kolar, D., “Automatic DefectClassification for Effective Yield Management”,Solid State Technology, Vol. 39 No. 12, pp. 89-96, 1996.

4 Shanthikumar, G., “Sequential and Bypass ADCSampling Models”, KLA-Tencor SEMICON/ WestADC Workshop, San Francisco, CA, 1998.

5 The National Technology Roadmap forSemiconductors, Semiconductor IndustryAssociation, San Jose, CA, pp. 117, 1997.

6 Jackson, J. and Usry, W., “Inspection of EtchLayers and Patterned Wafer Tool Monitoring Withthe AIT”, proceedings of KLA-Tencor YieldManagement Solutions Seminar, San Francisco,CA, 1998.

7 Phan, K. et al, A Methodology for theOptimization of an I-line Lithographic Process forDefect Reduction, SPIE Vol. 3332, pp. 309-320,1998.

8 Peters, L., “Speeding the Transition to 0.18 µm”,Semiconductor International, Vol. 21 No. 1, pp.61-70, 1998.

circle RS#012

InspectionF E A T U R E S

Automatic Defect Classification:A Productivity Improvement Tool

by Tony Esposito, IBM Corporation; Mark Burns, Scott Morell, KLA-Tencor; Eric Wang, Stanford University

Why should a semiconductor fab invest the time to review and classify defects on a wafer after the wafer has been inspect-ed? To add the additional step of classification in an already lengthy fabrication process is contradictory to manufactur-ing fundamentals unless it can be proven that the additional step can positively influence final yield. The extra informa-tion about the source of defects is an obvious benefit that defect review and classification provide. However, a method forquantifying the benefit of classification is required.

Traditionally, classification is done manually by a human operator after the wafer is inspected.Manual review and classification of defects offersdefect source information but carries with it sev-eral less-then-ideal side effects. From a manufac-turing standpoint, the extra processing stepincreases the total time it takes for a lot to workthrough the process flow. Classification requiresadditional employees and review tools on whichto do the review and classification. From an engi-neering standpoint, the information fed back byclassification is only useful if it is accurate andconsistent. In practice, a multitude of factorsimpact the accuracy of classification includingoperator experience, state of operator conscious-ness, consistencies from operator to operator, costof operator labor, the cost of review stations, andthe excessive queue time lots spend waiting forreview after in-line inspection. The ideal solutionis to place the task of classification with an auto-mated system that reduces or eliminates themajority of these negative side effects.

Beta evaluation of IMPACT/Online™ In a scientific approach to this task online, IBMinstalled a beta version of IMPACT/Online ADCon a KLA-Tencor 2132 defect inspector at IBMBurlington in order to collect data and analyzecosts. The system was trained to classify five dif-ferent production levels as part of the beta toolevaluation. The levels included: Trench Isolation,two metal levels, POLY on 64 Mb DRAM, andAfter-Develop Inspection or ADI (single layer

Autum

cluster tool daily monitor wafers using 64 Mbpitch). For each level, a minimum of 10 lots wereused to measure the performance of ADC againsta pre-defined set of metrics.

ADC performanceThe overall ADC performance of the five processlevels (figure 1) was measured and recorded. Eachof the ADC classifiers performed at or above theexpected levels for the beta evaluation.

Case study: ADI excursion monitorAt the time of this study, the production classifi-cation strategy for the ADI Excursion Monitorwas in transition from manual review and classifi-cation, to online automated defect classificationusing IMPACT. Therefore, the data collected forthis study includes classification data from boththe operators and ADC.

Figure 1. Beta performance of IMPACT/Online ADC.

Defect Standard Wafer 97% 100% 100%ADI Excursion Monitor 80% 89% 91%*4 Mb Metal 1 72% 80% 100%16 Mb Metal 1 77% 87% 99%64 Mb POLY 80% 80% 98%

Process/Level Accuracy Purity Redetection

*The lower-than-normal redetection for the ADI monitor is due to

nuisance defects. Subsequent to follow-on beta testing, the

inspection recipe was modified using Segmented Auto Threshold

(SAT), which reduced the nuisance defects and improved rede-

tection to greater than 95 percent.

n 1998 Yield Management Solutions 29

F E A T U R E S

Data collection procedureFor the purposes of this study, data and images fromADI wafers were chosen randomly across a two-weektime period. The accuracy and purity performance (figure 2) was calculated for the operators and ADCwith the expert classifications as the basis for compari-son. The ADC classifications are more in line with thoseof the expert than the classifications generated by thefive operators. This difference is indicated by the20+percent difference in accuracy and purity.

The pareto (figure 3) of defect classifications is orderedby expert classification and includes the classificationdata from all three sources: Expert, ADC and Manual.

The relative magnitude of the ADC classificationsmatch those of the expert classifier while the operatorcalls differ greatly in the SX (small defects) and the SF(Foreign Material on the Surface) class categories. Thisdifference was found to be consistent across the fiveoperators involved in the study. Other sources of manu-al classification errors were systematic. A single operatorconsistently classified SF defects as RR (Residual Resist)which suggests a need for additional training.

Correlation to yieldIBM’s PLY (Photo Limited Yield) methodology for linemonitor uses defect kill potentials to monitor the

Figure 2. Accuracy and purity numbers for ADC and manual classifica-

tions.

Figure 3. Pareto of ADI excursion monitor classifications.

ADC

Operator

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

PurityAccuracy

0.850.73

0.620.49

Perce

nt of

Def

ects

Class

ified

50%

40%

30%

20%

10%

0%SF SX NV IF BB IM RR MM OT

ExpertADCOperator

Autumn 1998 Yield Management Solutions30

impact of physical defects on die yield. The ADI defecttypes were consolidated into two groups (figure 4): a killer group which consists of defect types with a killpotential equal to 100 percent, and a non-killer groupwhich consists of all defect types with a kill potentialless than 100 percent. The highest kill potential in thenon-killer group was 35 percent with an average of lessthan 10 percent.

While the ADC classifications produce a similar split of non-killer versus killer defects, the operator classifica-tions favor the non-killer defect types. The more inac-curate operator classifications result in a systematicunder-estimation of the impact that the defects are having on electrical yield. This defeats the purpose ofthe in-line inspection in that elevated yield loss is notdiscovered until end-of-line electrical testing. By thistime, the manufacturing line may be full of substandardyielding material.

Time-to-resultsThe total time-to-results is defined as the time it takes to acquire data that an engineer can use to startappropriate defect reduction actions1. For manual orautomatic defect classification, the total time includes:

• the inspection time;

• the queue time between inspection and the reviewstation;

• the time required to load and align the wafers on areview station; and

• the time required to perform manual or automaticclassification3.

Figure 4. Killer and non-killer defect statistics for the ADI excursion

monitor.

Perce

nt of

Def

ects

Class

ified

80%

70%

60%

50%

40%

30%

20%

10%

0%Expert Operator ADC

KillerNon-killer

F E A T U R E S

The time-to-classification is a subset of the total time-to-results that ignores the inspection time.

The average total time-to-classification (figure 5) favorsthe ADC system by a factor of 50. With IMPACT/Online ADC, the classification immediately follows theinspection step which eliminates the queue time associ-ated with the manual classification.

Quantifying the benefits of defectreviewThe most obvious benefit of defect review is that it supplies information about the types of defects on asemiconductor wafer. The defect type informationassists the yield engineers in identifying the sources ofthose defects. However, to choose the optimal in-lineinspection and review sampling strategy, a method isneeded for quantifying the benefits of all availablestrategies. A cost-based inspection and review samplingmodel for mean-shift random defect excursions has been developed by the Competitive SemiconductorManufacturing (CSM) Automated Inspection FocusStudy Research Group6 and is the subject of reference3.This economic model may be applied in this case studyto quantify and minimize the total defect excursioncost, which consists of the out-of-control cost, the in-control cost, investigation cost, fixing cost and falsealarm cost3, 4, 5.

A simple view of the process control dynamics is used(figure 6) to describe the basic premise of the economicmodel2, 3, 4:

Figure 5. Average time-to-classification results of ADC versus the

operators.

Queuing 1 0Set up 0.15 0.01Image capture 0 0.0001Classification 0.034 0.0136Average Total (hours) 1.184 0.0237

Review Time Component Operator ADC

ADC

Operator

0 0.2 0.4 0.6 0.8 1 1.2

ClassificationImage captureSet upQueuing

Time to Classified Results (hours)

A

• The in-control cost is the product of the cost of baseline yield loss and the duration of time a processis in-control.

• The out-of-control cost is the product of the cost of yieldloss during an excursion and the duration of time theprocess is out-of-control. The time a process is out-of-control is the sum of the detection delay, the investi-gation time and the fixing time. Accurate and timelydefect review information will reduce this cost byreducing the detection delay and the time spentinvestigating the source.

• The cost of finding the root cause for an excursion isthe investigation or source identification cost. Again, accu-rate and timely defect review information will reducethis cost by reducing the time spent investigating thesource.

• The cost of implementing changes to return theprocess to an in-control state is the fixing cost.

• False alarm cost is the cost of reacting to an excursionwhen the process is actually in-control. The falsealarm cost is usually a combination of investigationand fixing costs.

The dominant cost in the total cost equation is typical-ly the out-of control cost. The electrical die yield ofwafers processed while out-of-control is typically lessthan the die yield of wafers processed while in-control.This loss of product means loss of revenue that theproduct would normally generate. To minimize thisrevenue loss, the amount of time a process runs in anout-of-control state must be minimized.

Excursion cost drivers — sensitivityanalysis of the economic modelInformation from in-line inspection sampling is used todetermine whether an excursion has occurred or not1.

Figure 6. Diagram of cost-based sampling model.

Detection DelayProcess

In-Control

ExcursionOccurs

ExcursionDetected

ExcursionFixed

Elementsof Cost

In-Control Cost Out-of-Control Cost

False Alarm Cost(investigation, fix)

Investigation Cost

Fixing Cost

utumn 1998 Yield Management Solutions 31

F E A T U R E S

The uncertainty in making this determination is mea-sured using two risk factors — alpha and beta — bothof which are based on the overlap between the in-con-trol and out-of-control defect distributions (figure 7).The beta risk is of primary concern since it determinesthe length of the detection delay (figure 6), which is theduration of time the process runs in an out-of-controlstate before it is detected by the in-line control system.The beta risk is represented by the percentage of theout-of-control distribution to the left of the statisticalprocess control (SPC) limit. By increasing the frequencyof in-line inspection, the accuracy of the defect classifi-cations, and the size of the review sample, the defectdistributions become more distinct and the overlapbetween the two is minimized. Minimal overlap trans-lates into reduced beta risk driven detection delaywhich reduces the cost of an excursion.

Comparing the benefits of various ADIexcursion monitor strategies The data collected for the ADI excursion monitor wasused to model the economic benefits of defect reviewand classification. The total detection delays includingthe review and inspection times are displayed for vari-ous ADI excursion monitor scenarios in figure 8. Theinspection portion of the ADC bars include the reviewtime associated with automated defect classification onan average ADI wafer.

The first two bars describe a theoretical scenario wherethe accuracy of classification for manual and automateddefect classification is perfect at 100 percent. The sec-

Figure 8. Total detection delay for various ADI excursion monitor

strategies.

Figure 7. Model of defect distributions — graphical representation

of beta risk.

In-ControlDistribution

Out-of-ControlDistribution

SPC Limit

Detec

tion D

elay (

hours

)

MDC(100%

accuracy)

ReviewInspectionBeta Risk

50

40

30

20

10

0ADC

(100%accuracy)

MDC(49%

accuracy)

ADC(73%

accuracy)

Autumn 1998 Yield Management Solutions32

ond two bars in the series compare manual defect classi-fication and ADC as measured in the case study. Notethe overwhelming contribution of the beta risk, whichaccounts for 90 percent of the total detection delay forall four scenarios.

As a key driver of beta risk and, therefore, detectiondelay (figure 9), the accuracy of defect classificationgreatly affects the cost of an excursion. Looking at theexcursion cost in terms of revenue lost per hour (figure 10) determines which in-line monitor strategy isoptimal for the ADI process. In the total cost equation(figure 6), source identification time and fixing timeplay a close second and third to the costs associated withbeta risk-driven detection delay.

Note that ADC, based on performance measured duringthe case study, is the most cost-effective classificationstrategy. By adopting ADC on the ADI excursion moni-tor, IBM can expect to save over $250 per hour in rev-enue versus the manual defect classification strategy.This equates to more than $42,000 per week of revenuesaved by implementing ADC at one in-line monitorlocation.

Figure 10. Revenue loss rate for various ADI excursion monitor strate -

gies.

Reven

ue Lo

ss ($/

hours

)

MDC(100%

accuracy)

FixingSource IDReviewInspectionBeta Risk

500

400

300

200

100

0ADC

(100%accuracy)

MDC(49%

accuracy)

ADC(73%

accuracy)

Figure 9. Beta risk driven detection delay versus classification

accuracy.

Dete

ction

Dela

y (h

ours)

70

60

50

40

30

20

10

0

100% 90% 80% 70% 60% 50% 40%

Accuracy %

F E A T U R E S

If you’re responsible for thin filmthickness measurements, you wantthem to be right. And you definitelydon’t want to be embarrassed by ametrology tool that decides to driftat a critical time.

That’s why perfectionists insiston VLSI’s suite of thin-film metrolo-gy standards. For silicon dioxideand silicon nitride. The broadestselection in the industry.

And now, oxide standards areavailable for 4.5nm and 7.5nm! It’s aVLSI exclusive.

So if you’re a metrology perfec-tionist, flaunt it! Call now for yourfree “Good Enough ISN’T” buttonalong with your free VLSI catalog...

VLSI Standards:(800) 228-8574. Or on the Internet:www.vlsistd.com

4 out of 5 Perfectionists Insist OnVLSI’s Thin Film Metrology Standards.

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ConclusionsUsing the excursion cost modelenabled IBM to quantify the bene-fits of classification. The exerciserevealed that classification, in gener-al, is a vital part of a cost-efficient,in-line monitor strategy. In addi-tion, classification metrics, such asthe accuracy and review time associ-ated with classification, determinethe cost of an excursion.

The key advantages in classificationaccuracy and time-to-results sub-stantiate the need for on-line ADC as a replacement for manual defectclassification on the ADI in-linedefect monitor. The revenue lossesassociated with excursions arereduced by an estimated $42,000per week by implementingIMPACT/Online ADC at the ADIin-line monitor location. The suc-cess at this process monitor, alongwith that of the entire beta evalua-tion, has motivated IBM to pursuethe implementation of more pro-duction monitors using IMPACT/Online ADC.

Future IBM interests include SEM-based ADC and ADC on laser-scat-tering defect inspection tools. Theoptical limitations of identifyingdefects < 0.35 um in size combinedwith the constant reduction in critical dimensions that come withnew process technologies favor anSEM-based ADC solution.

1 Louis Breaux and Dave Kolar, “Automatic DefectClassification for Effective Yield Management”,Solid State Technology, December 1996, pp. 89 -96.

2 Nurani, R. K., R. Akella, A.J. Strojwas,R.Wallace, M.G. McIntyre, J.Shield, I.Emami,“Development of an Optimal Sampling Strategyfor Wafer Inspection”, International Symposium onSemiconductor Manufacturing Proceedings, Tokyo,Japan, June 1994.

3 Wang, E.H., “An Integrated Framework forYield Learning in Semiconductor Manufacturing”,Stanford University Ph.D. Dissertation, May 1997,Chapter 3.

4 Wang, E.H. and D. Fletcher, “Optimal WaferInspection Strategy with Learning Effects”, ASMC,October 1996.

5 Nurani, R.K., R. Akella and A. J. Strojwas, “In-line Defect Sampling Methodology in YieldManagement: An Integrated Framework”, IEEETranscript On Semiconductor Mfg. 1996.

6 The Competitive Semiconductor Manufacturing(CSM) Automated Inspection Focus Study

The Measure

Research Group consists of professors and Ph.D.candidates from UC Berkley, Stanford andCarnegie Mellon Universities.

This article was first presented as a paper at theAdvanced Semiconductor ManufacturingConference and Workshop (IEEE/SEMI),Cambridge, MA., September 10-12, 1997.

circle RS#015

ment Standards for the Industry.

34

YMS2

YIELD

MANAGEMENT

SOLUTIONS

SEMINAR■

For additional information contact Janet

Ely via e-mail at janet.ely@kla-tencor.com

Autumn 1998 Yield M

Yield ManagementSeminar SeriesSince 1994, KLA-Tencor seminar series has provided customers with a valuable venue in which to share innovative ideas on how our products help solve manufacturing challenges. The new YieldManagement Solutions Seminars, YMS2, will focus on value-added,integrated solutions for yield management, and process control. Keytopics to be covered include CMP, Lithography, In-Line Monitoring and Yield Strategies.

This section of the magazine will highlight a paper from a recent seminar and preview the upcoming session. We encourage you toattend and participate in our new seminar series. Your comments and feedback are welcome at any time.

Call for papers

YMS2 is always interested in proven application ideas, solutions totechnical problems, new methodologies, and advanced techniques.The papers should focus on using KLA-Tencor tools and solutions toenhance yield through increased productivity and performance. Thepresentation does not have to be a formal published paper, just a synopsis of your testing and the results.

Topics of interest

Defect Inspection, Lithography, CMP, Film Measurement, and YieldManagement Strategies.

If you are interested, please contact Janet Ely via email atjanet.ely@kla-tencor.com.

YMS2 at a GlanceOctober 21 Austin, Hyatt Regency (during SEMICON Southwest)

December 3 Makuhari, Japan, New Otani Hotel (during SEMICON Japan)

February 23 Seoul, Korea, Inter-Continental Hotel (during SEMICON Korea)

March 17 Santa Clara, Westin Hotel (during SPIE)

April 14 Munich, Germany (during SEMICON Europa)July 13 San Francisco, ANA Hotel (during SEMICON West)

S E C T I O N S

anagement Solutions

Best of YMSS E C T I O N S

Inspection of Advanced OPC ReticlesDuring the July 1998 YMS2, DuPont Photomask (DPI) presented its evaluation of OPC techniques and the inspec-tion capabilities of KLA-Tencor’s new 353UV reticle inspection system. In the results, DPI emphasized the importanceof OPC technology and the 353UV’s superior ability to inspect these features

Simply defined, optical proximitycorrection (OPC) techniques consistof incorporating features in the pro-duction of photomasks that neutralizeoptical distortion when a semicon-ductor design pattern is transferredto silicon. The value and use ofOPC technology is growing becauseof the ongoing progression toincreasingly smaller semiconductordesign features. Semiconductor man-ufacturers are recognizing that OPCtechnology can extend the life of lith-ography steppers by extracting themaximum resolution performancepossible from their equipment.

OPC addresses many issuesOPC features range in complexityfrom simple edge jogs and line sizeadjustments to more complex, isolat-ed mixed-tone features that areembedded in both the clear andchrome areas of the photomask.Serifs and hammerheads — squaresand rectangles — are the most com-mon OPC features on the photomaskand are added to the end of adesign line to prevent corner round-ing and line-end shortening. Anothertechnique involves adding assist fea-tures that change the way designfeatures behave during the lithogra-

phy process. For example, someOPC software packages automatical-ly add scatter bars to isolated designfeatures, causing those structures toprint in the same manner as moredense design areas to produce auniform result during the semiconduc-tor manufacturing process. The fea-tures are too small to print during thelithography process, but preservedesign integrity by increasing the res-olution achieved by the stepper.

Monitoring the effects of OPCOPC features generated on a pho-tomask are usually between 20 and50 percent of the size of design features, requiring advanced produc-tion equipment to complete the man-ufacturing process successfully. Just as

Autumn 1998 Yield

properly implemented OPC featuresimprove the pattern accuracy,improper OPCs can create patterncomplications. For instance, a miss-ing or under-sized serif can causesignificant drawback, while over-sized serifs can result in bridging onthe wafer (figure 1).

Figure 1. An oversized OPC feature can result in bridging on the wafer pattern.

Inspection technology is beingpushed to new levels of functionalityby the use of OPC. Although thesefeatures are sub-resolution, they stillmust be inspected and verified. Aspart of a strategic alliance, DPI andKLA-Tencor are working closelytogether to test advanced photomaskinspection technology and new soft-ware algorithms that enable patternrecognition of advanced OPC fea-

Management Solutions 35

Best of YMSS E C T I O N S

KLA-Tencor Fall-Winter ’98 Trade Show Calendar

October 19-21 ITC – International Test Conference, Washington, DC, USA

November 4-6 SEMICON Taiwan, Taipei, Taiwan

November 16-17 VDE/VDI Conference, Munich, Germany

December 1-3 Fall MRS, Boston, MA, USA

December 2-4 SEMICON Japan, Makuhari, Japan

tures, as well as identify OPCdefects. Recently, DPI evaluated andcharacterized KLA-Tencor’s newUltraviolet UV inspection system, the353UV. During the evaluation, DPIengineers used both standard testplates and specially designed OPCreticles to characterize the new 0.18nm pixel inspection, AOP algorithm,and defect highlighting tools.

36

Figure 2. The 353UV significantly improves defect sensitivity over previous inspection systems.

353UV, AOP algorithm, 0.18 µm 351, APA algorithm, 0.25 µm

System evaluation The 353UV demonstrated improveddefect sensitivity on OPC features asa result of: 1) shorter wavelength, 2)

Autumn 1998 Yield M

smaller pixel size, and 3) improveddetection algorithms. Defects amongserifs, hammerheads and assist lineswere detected in isolated and densegeometries. Additionally, the 353UVsystem also showed improved sensi-tivity on UV-opaque defects and bet-ter resolution on DUV EA phase shiftmasks (figure 2). DPI engineers alsorealized that improved review toolsare required to accurately classify thesmaller defects. New review featuressuch as edge sharpening and pixeldisplacement helped to classify 50nm localized gate CD errors andprocess defects.

anagement Solutions

Inspection issues are closely linked toa photomask producer’s ability togenerate features with sufficient clarity. The better a feature image isresolved on a photomask, the easierit becomes to do pattern inspections,saving valuable cycle time. The inter-dependent nature of production andinspection technology ensures thatthe development process will beongoing, with advancements in production capabilities necessitatingnew developments in inspection technology.

MetrologyF E A T U R E S

Monitoring of Low Dielectric Constant ParyleneFilms using Spectroscopic Ellipsometry

by Carlos L. Ygartua, Process Module Manager; Duncan W. Mills, Staff Software Engineer; Clive Hayzelden, Senior Technical Marketing Manager

Parylene-F is one of the most promising materials for use as an intermetal dielectric at the 0.18 µm technology node. Dueto its anisotropic refractive index, however, parylene-F cannot be examined using conventional spectroscopic ellipsometrictechniques. In this article, the results of developing sophisticated data collection and analysis algorithms to determine thedifferences between in-plane and out-of-plane refractive indices are presented.

The development of new intermetal lowdielectric constant materials is a criticalrequirement for reducing parasitic capaci-tance and cross-talk in the increasingly fine-scale fabrication of semiconductor devices.Parylene-F (AF-4) offers a low dielectricconstant (<2.3), high thermal stability(>450oC) and ease of deposition1. Ideally,measurement techniques for parylene AF-4should be rapid, non-invasive, and similarto methods already in use for dielectric filmmonitoring. Spectroscopic ellipsometry (SE)has already achieved considerable accep-tance as a monitoring tool. To achieve wide-spread acceptance of AF-4 in high volumemanufacturing, however, it will be neces-sary to have methods and equipment forproduction monitoring of film thickness,uniformity, and refractive index. In thisarticle, a method is presented for simultane-ously measuring thickness, in-plane, andout-of-plane refractive indices of parylene.

The UV-12X0SE and ASET-F5 film thick-ness measurement tools use two technolo-gies: broadband (visible plus ultra-violet)Dual Beam Spectrometry (DBS), andSpectroscopic Ellipsometry (SE). KLA-Tencor measurement tools characterizefilms by providing reflectivity spectra andcalculating the values of film parameters —the thicknesses, t, refractive indices, n, andextinction coefficients, k — from the bestfit between theoretical and measured spec-tra. The DBS tool subsystem obtains themeasured spectrum, Rm(λ), that representsthe reflected light intensity as a function ofthe wavelength, λ. In the case of SE, the

A

reflected light is elliptically polarized. It can be repre-sented by two components: a p-component, Rp, withpolarization parallel to the plane of the incident andreflected beams, and an s-component, Rs, with polariza-tion perpendicular to that plane (figure 1). Rp and Rsare complex quantities, defined by their intensities, |Rp|and |Rs|, respectively, and their phase difference, ∆.

TanΨ and cos∆ are the standard ellipsometry parame-ters that describe the polarization state of the reflectedlight. They are defined by:

TanΨ is the ratio of the p- and s-component intensities,and cos∆ is the real part of the complex quantityexp(i∆). To properly analyze the uniaxial birefringentnature of these films, KLA-Tencor has developed andimplemented an algorithm designed to model theeffects of the ordinary and extraordinary refractive

next

nord

p s

Figure 1. Showing the s and p polarization states of the reflected light

together with the ordinary (in-plane) and extraordinary (out-of-plane)

refractive indices of the parylene.

Rp Rp

Rs Rs= .exp (i∆) = tan Ψ.exp(i∆)

utumn 1998 Yield Management Solutions 37

38

F E A T U R E S

indices (RI) upon the amplitudeand phase of the reflected signal.Fortunately, uniaxial films of theparylene type contain no in-planeanisotropy, so they cause no mixingof the two independent p and spolarization states. Consequently,the “traditional” tanΨ and cos∆parameters defined for isotropicfilms also apply to the presentanalysis.

Film depositionIn a typical parylene AF-4 deposi-tion process, the AF-4 dimer, octafluoro-[2,2]-paracyclophane, issublimed in a vaporizer and thesublimed gaseous dimer is passedthrough a pyrolyzer maintained at600ºC - 700ºC. The generatedmonomer, a,a,a’,a’-tetrafluoro-p-

Autumn 1998 Yield Management Solutions

xylylene polymerizes instantly onthe wafer giving parylene AF-4films. The vapor phase polymeriza-tion method at Novellus providesparylene AF-4 films with excellentuniformity and conformity on 200mm wafers. The deposited paryleneAF-4 films are semi-crystalline andthe polymer chains are composed of-[C6H4-CF2-CF2]- structure. Wehave measured both as-depositedsamples and samples that havereceived a 400ºC anneal in a nitro-gen atmosphere.

Ellipsometric analysis of severalparylene films, including PPX-N,PPX-C, and PPX-D has indicatedthat they are uniaxial, with anextraordinary refractive index nor-mal to the film surface, leaving twodegenerate ordinary refractive indiceslying in the plane of the film2. Thenature of the birefringence differsbetween the types of parylenes; asan example, PPX-D is positive uni-axial (nextraordinary > nordinary),whereas most parylenes are negative

DBS ReflectivityMeasured – DBS Model – DBS

0.70.60.50.40.30.20.1

300 400 500 600 700

SE Tan (Ψ)Measured – SE Model – SE

4321

300 400 500 600 700

SE Cos (∆)Measured – SE Model – SE

0.50.0-0.5

300 400 500 600 700Wavelength (nm)

Figure 2. SE and reflectivity spectra for as-deposited AF-4.

Thickness = 1075 nm.

nord next1.81.71.61.51.41.3

300 400 500 600 700

K vs nm

N vs nm

0.100.080.060.040.020.00

300 400 500 600 700

kord kext

Wavelength (nm)

Figure 3. Dispersion of the real (n) and imaginary (k) parts of the refractive

index for ordinary and extraordinary modes for the as-deposited sample.

nord(633 nm) = 1.5179 and next(633 nm) = 1.4217.

F E A T U R E S

uniaxial. Our analysis has indicatedthat AF-4, both as-deposited andafter-annealing, is negative uniaxial,with fairly pronounced birefrin-gence compared to other parylenes.

ResultsFigure 2 shows SE and DBS spectrafor as-deposited parylene AF-4 onsilicon, the reflectivity rapidly dropsto less than 10 percent at a wave-length of 272 nm and the SE spec-tra oscillations are damped out inthe 260-275 nm range. The varia-tion of n and k with wavelength areshown in figure 3. A strong absorp-tion peak at 272 nm is seen inagreement with the observed mini-mum in reflectivity. In the 300-750nm range, where k=0, nordinary andnextraordinary are essentially parallel,

Autum

with an offset of ~0.1. The unifiedSE plus DBS measurement resultsfor this sample match prism couplerindex measurements at 633 nm (nordinary = 1.53 and nextraordinary =1.42) and profilometer measure-ments (thickness ∼ 1030 nm).Figure 4 shows SE and reflectivityspectra for an annealed AF-4 samplewith a thickness of 915 nm. Thedispersion curves are shown in figure 5.

Table 1 shows a summary of measurement results for the as-deposited and annealed samples.The in-plane (nordinary) and out-of-plane (nextraordinary) refractiveindices of the as-deposited materialwere determined to be 1.5137 and1.4135, respectively. Followingannealing, the in-plane (nordinary)and out-of-plane (nextraordinary)refractive indices of the materialwere determined to be 1.5879 and 1.4170, respectively.

Figure 4. SE and reflectivity spectra for annealed AF-4.

Thickness = 915 nm.

DBS ReflectivityMeasured – DBS Model – DBS

0.60.50.40.30.20.1

300 400 500 600 700

SE Tan (Ψ)Measured – SE Model – SE

654321

300 400 500 600 700

SE Cos (∆)Measured – SE Model – SE

0.50.0-0.5

300 400 500 600 700Wavelength (nm)

nord next2.01.91.81.71.61.51.41.3

300 400 500 600 700

K vs nm

N vs nm

0.100.080.060.040.020.00

300 400 500 600 700

kord kext

Wavelength (nm)Figure 5. Dispersions of the real (n) and imaginary (k) parts of the refractive

index for ordinary and extraordinary modes for the annealed sample.

nord(633 nm) = 1.5879 and next(633 nm) = 1.4170.

n 1998 Yield Management Solutions 39

F E A T U R E S

THI

de

sof

As deposited Annealed

Ordinary Extraordinary Delta Ordinary Extraordinary Delta

thickness (nm) 1075 n/a n/a 915 n/a n/a

n(633nm) 1.5137 1.4135 0.1002 1.5879 1.4170 0.1709

k(265nm) 0.0349 0.0509 -0.0160 0.0370 0.0505 -0.0135

k(272nm) 0.0157 0.0696 -0.0539 0.0488 0.0671 -0.0183

Table 1. Summary of

measurement results.

SummaryKLA-Tencor found that the refrac-tive index (RI) dispersion for thetwo optical axes and the film thick-ness can be determined from cou-pling spectroscopic ellipsometry(SE) and normal incidencereflectance spectroscopy (DBS). Thenegative uniaxial optical anisotropy(nordinary - nextraordinary) is shown toincrease from 0.1002 to 0.1709 fol-lowing annealing at 400ºC. Themeasurement technique is suitable

N FILM SOFTWARE 2.xWORKSTATION

Off-tool data analysis andrecipe management

GEM/SECS softwarevelopment and training tool

OLSA 1.xOff-line spectral analysis

tware for recipe development,measurement simulation,

and analysis

For more information, circle RS#032 located

New Off-TIncreased Fil

for routine measurement of filmthickness and refractive indices ofparylene-F films deposited duringintegrated circuit processing.

AcknowledgmentsWe gratefully acknowledge our collaboration with James Stimmelland Devendra Kumar of NovellusSystems, Inc., San Jose, CA. Wewould also like to acknowledge thecontributions of the Specialty

on the business reply card or call (408) 875-7

ool Software Prodm Measurement P

circle RS#002

Coatings Systems Division of AlphaMetals, Inc. for providing the highquality cyclic dimer AF-4 startingmaterial used in this study.

1 M.A. Plano, D. Kumar and T.J. Cleary, TheEffect of Deposition Conditions on the Propertiesof Vapor-Deposited AF-4 Films. Mat. Res. Soc.Proc. Vol 476, 1997.

2 J.G. Gaynor and S. B. Desu, Optical Propertiesof Polymeric Thin Films Grown by Chemical VaporDeposition, J. Mater. Res., vol. 11, No. 1, Jan.1996.

RECIPE GENERATORAutomatic waferless recipe

creation using basic stepper andreticle database information

Recipe generation on a local tool or workstation database

LAPLINK™FOR NT

Remote control for diagnosticsand troubleshooting

996.

ucts forroductivity

MetrologyF E A T U R E S

Tungsten Plug Measurement for CMPDevelopment and Production

by Anna Mathai, Technical Marketing Engineer; Paul Sullivan, Software Manager; and Jason Schneir, Product Marketing Manager

Chemical Mechanical Planarization (CMP) processes are widely used in the semiconductor industry to enable multileveldevice processing and smaller device features. Process variations in CMP can lead to many failure modes. For example, mostmetal polishing processes lead to recessed metal features because of the differential polishing at the dielectric/liner/metal inter-face. In addition, changes in the process, such as the pH level of the slurry, polishing speed or conditioning of the pads willchange the plug recess. Plug recess needs to be carefully monitored since if it is too large, it will degrade the electrical con-nections between the vias and metal interconnects. This can lead to increased electrical resistance and limit the performanceof the integrated circuit.

CMP process sectors have commonly usedprofilers to measure the post-CMP pla-narization of the wafer. As the feature sizeof ultra large-scale integration technologydecreases, this introduces stringentrequirements on the spatial resolution ofthe CMP metrology tools. KLA-Tencor’sHigh-Resolution Profiler (HRP) isdesigned to monitor metal CMP processesin the fab, as is demonstrated here onmeasurements of tungsten plugs.

Measuring plug recessIn a production environment, it is criticalfor the plug recess measurements to bemade automatically on an entire cassetteof wafers without operator intervention.The HRP loads each wafer automaticallywith a pre-assigned orientation and usesoptical pattern recognition to locate anisolated plug to within a 10 x 10 µm area.Since CMP provides low optical contrast,edge enhanced pattern recognition modelsare used.

Next, the feature-find algorithm scans thestylus in the x-direction with a pre-assigned scan length (see schematic in fig-ure 1). If no plug is found that meets pre-set depth and width criteria, the stylussteps over a pre-assigned distance in the

A

y-direction and takes another x-scan (scans 1-3). In thisway, the stylus quickly locates the plug and then takes ascan in the y-direction (scan 4) to determine the centerof the plug. Then, a high-resolution image is acquired,positioning the isolated plug to within 0.5 µm of thecenter of the scan (shown by dotted lines). Figure 2shows an HRP high-resolution image of an isolatedtungsten plug.

Next, the data isanalyzed by theHRP advanced cus-tomizable measure-ment software,Answer!™ (see fig-ure 3). Answer!seamlessly integratessophisticated macroswritten in a high-level programminglanguage with theHRP software. This architecture enables KLA-Tencor toquickly develop custom macros for specific process mea-surement needs.

The Answer! plug recess algorithm thresholds the datato automatically find the plug and separate it from thebackground. Then, the algorithm extracts a representa-tive line profile through the plug. Finally, it segmentsthe data vertically, based on user-selectable parameters,in order to compute the plug recess and width.

Scan 4

Scan 1

Scan 2

Scan 3

Final high-resolution scan centered on feature

Figure 1. The HRP feature-find algorithm.

utumn 1998 Yield Management Solutions 141

F E A T U R E S

Figure 3. The HRP Answer! plug recess macro

automatically measures tungsten plug recess

and width.

Figure 2. HRP high-resolution image of 0.25

µm geometry isolated tungsten plug.

198 Angstroms

The new OMNIMAP® RS-100 delivers the feahave been asking for.

• Accurate edgefrom

•

•c

• Ec

The First Production300 mm ResistivityMeasurement System

Figure 4.

Automated mea-

surement repeata-

bility of an isolated

tungsten plug is

0.9 nm (1σ).

70

68

66

64

62

600 2 4 6 8 10

Trial number

Plu

g r

eces

s (n

m)

circle RS#

ResultsFigure 4 summarizes ten dynamicmeasurements on a single isolatedtungsten plug, with the waferunloaded and re-loaded betweenmeasurements. We found the plugrecess measurement to have excel-lent repeatability of 0.9 nm (1σ).

The measurement was repeated after12 hours and again after 48 hours,using the same stylus. The measure-ment was also repeated using twoother styli. Overall, we found theplug recess measurement to have

tures customers

measurement to 1 mm the conductive filmPowerful and easy to use Windows NT® platform

Full GEM/SECS HSMSompatibility and morexpanded sensitivity for highly onductive interconnects such as

copper and thick aluminum• Automated probe conditioner

• 3D uniformity maps• 200 mm and 300 mm configu• Meets SEMI safety and ergono

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Visit our website at www.kla-tenc

excellent long-term repeatabilityand to be insensitive to the stylusshape.

In process development, the HRPhas proven to be an invaluable char-acterization tool for CMP applica-tions, including post-CMP ShallowTrench Isolation (STI), tungsten andcopper CMP, and inter-level dielec-tric CMP. The HRP is used by bothsemiconductor manufacturers andCMP equipment manufacturers rou-tinely to qualify and monitor theperformance of CMP polishers.

028

rationsmic requirements

or.comcircle RS#003

S E C T I O N S

&AQAnswers to your questions from

KLA-Tencor’s Yield Management Consulting Group (YMC).

Q I already have yield engineering experts on staffin my fab; what value can aYield Management Consultingteam bring me?

A The KLA-Tencor YieldManagement Consulting group addsvalue to your yield improvementefforts in two ways. First, we maintaina unique bank of proprietary informa-tion captured from benchmarkingmore than 100 of the world’s topsemiconductor manufacturers. Thisinformation bank includes a highlyconfidential database of yield learn-ing rates and maximum achievableyields, as well as “best practices”identified throughout the semiconduc-tor industry. Using this database,Yield Management Consulting canhelp determine your fab’s yield poten-tial and which “best practices” canhelp you quickly achieve your yieldgoals. Second, when time-critical situ-ations occur in your fab, our team ofseasoned yield management profes-sionals can supplement the skill setsof your fab yield engineers to jointlyaddress your yield problems.

Q What expertise do your yield management consultants offer?

A Our Yield ManagementConsulting team is comprised of specialists with an exceptionallybroad-based set of yield manage-ment skills. They represent over 400collective years of wafer fab yieldengineering experience and state-of-the-art knowledge in interconnect andequipment technology.

Q What kinds of resultshave been seen from YMCwork?

A Accelerated yield learning ratescan translate into millions of dollars inadditional revenue. Results vary bycustomer situation; however, manycustomers have stated that they haverealized tens of millions of dollars insavings or revenue as a direct resultof yield improvements achieved withYield Management Consulting assis-tance.

Q Would Yield ManagementConsulting services benefitme even if I do not haveKLA-Tencor equipment orsoftware in my fab?

A Yes, Yield ManagementConsulting offers a set of services thatare not KLA-Tencor tool dependent.

Autumn 1998 Yield

Our Fab Yield Benchmark Study andStatistical Probe Yield Analysis useYield Management Consulting’s specialized consulting software andour proprietary databases. However,customers obtain the greatest benefitand value when KLA-Tencor inspec-tion tools, analysis software, andyield management consulting exper-tise are integrated to provide a com-plete solution to yield-limiting issues.

Q Are your services effective in new fab startups, as well as existing fabs?

A These services are very importantto the ROI for a new fab since thelonger it takes to ramp a new fab,the more revenue is lost. Becausetoday’s typical new fab investment is$1.5 billion, it is critical to maximizethe ROI by quickly ramping to entitledyields. Yield Management Consultinguses their suite of proven yield man-agement methodologies and servicesto help you achieve industry-leadingfab yield ramp rates to assure maxi-mum yield and ROI in the minimumamount of time.

circle RS#026

For more information, contact your local YMC group408.875.2696

Management Solutions 43

CorporateF E A T U R E S

Bringing the Future into Focus

Interviews with Industry Leaders

Mark Melliar-Smith,President and CEO of SEMATECH

Dale Harbison,Vice President of the Semiconductor Group at Texas Instruments

Sung W. Lee,President ofSamsung AustinSemiconductor

Autumn 1998 Yield Management Solutions44

A video shown at KLA-Tencor’sexhibit during SEMICON West 1998 featured interviews withindustry leaders Mark Melliar-Smith, President and CEO ofSEMATECH, Dale Harbison, VicePresident of the SemiconductorGroup at Texas Instruments, andSung W. Lee, President of SamsungAustin Semiconductor, on the chal-lenges and issues the industry facestoday. Below are excerpts from thisvideo:

KLA-Tencor: What do yousee as the most criticalchallenges the industrywill face in the next fewyears?

Melliar-Smith: I think managing com-plexity is probably the biggest chal-lenge this industry faces over the nextdecade. . . . Very often it will be hard-er to design a 100 million gate inte-grated circuit than it will be to make it.And very often, in a factory, theprocess control technology is more difficult than the process itself.

Harbison: Today, feature sizes areshrinking and demands on speed anddensity of the circuits are increasing.Post-optical lithography is a big chal-lenge, because EUV, Scalpel andother X-ray techniques are very expen-sive; at the same time, we've got cop-per, we've got low-k, we've got allthese things that are costing the indus-try large amounts of money.

Lee: Nowadays, prices are decreasingso fast we have to introduce our newproducts as quickly as possible. Ramp-upspeed is the most critical thing for us.

KLA-Tencor: What about theimpact of fast yield rampson profitability? How isthat driven by today’s eco-nomic environment?

Melliar-Smith: Fast yield ramps are cru-cial for a couple of reasons. The firsttends to be very close to home. It's whenyou've built a $2-billion fab and yourshareholders want a return on it. The onlyway to get a return on such a largeinvestment is to ramp it very quickly. Butequally important, your customers need afast yield ramp as well. Typically they'relooking for the highest technology andthey want it quickly, to help their productscome to market.

Lee: We‘ve already invested $1.5-billionhere in this fab, so if we delay the prod-uct, interest and depreciation will cost usalmost $10-million a month. How tobuild our fab fast, how to quickly rampour production, and how to enhance ouryield are the most important things.Speed means everything in this business.

KLA-Tencor: What does“yield management” reallymean? Why is it so impor-tant?

Melliar-Smith: The most important thing tounderstand about yield management isno surprises. It's not just a matter of data,it's a matter of reality. It's a matter of turn-ing the data into what actually is going

Autumn

on, inside the process or inside your fab.What we really need to do in yield man-agement is to look at the future, andwhere the process is at any point in time,to try to prevent the defects in the firstplace.

Lee: We have to heavily rely on the auto-mated inspection equipment and theautomated data collection systems tomake our decisions more correct.

Harbison: Predicting results is very impor-tant, and that's what we want the yieldmanagement tools to do. . . . That's whyit's so critical for us to have more auto-mated and more advanced yield man-agement tools, so that they can gatherthat raw data, massage it, digest it, andgive it back to the fab people in a formthat they can very quickly take action onand very quickly generate results.

KLA-Tencor: So what rolewill the industry play in thefuture?

Melliar-Smith: I think you're always ulti-mately limited by the human imaginationin almost anything that you do. We'vebeen able to facilitate whole new mar-kets, like cellular telephony, the Internet,the PC — all of those technologies essen-tially have been made possible, and certainly cost effective, by integrated circuits.

If you are interested in seeing this videoin its entirety, please circle reader service#29 on the BRC.

1998 Yield Management Solutions 45

Product News

362 Reticle Inspection SystemAn extension of the 300 Series platform, the 362 Automated ReticleInspection System now compares optical proximity correction (OPC) technol-ogy enhanced geometries on the photomask to a matching database. The 362is optimized for increased sensitivity on production OPC photomasks throughthe new AOP algorithm and improved database modeling, ensuring a closermatch between the optical and database images. In addition, data preparationand rendering speed improvements can reduce both cycle and inspection timesof advanced databases. The 362 also features defect review enhancementsresulting in improved defect classification of subtle mask pattern errors.Previous 300 Series systems can be field upgraded to the 362.

circle RS#017

AMRAY 4000 Series Defect Review SEM SystemsKLA-Tencor AMRAY Division’s 4000 Series Defect Review SEM systemsoffer the latest in SEM-based defect review and automatic defect classificationcapability for 0.18 µm process technologies and beyond. The 4000 series —offered in both 200 mm and 300 mm configurations — works in unison withKLA-Tencor’s Intelligent Line Monitor (ILM) System, automatically filteringoptically inspected and classified data, performing one-touch ADC, andupdating Quest™/Klarity™/VARS with both images and data. By usinginformation available from inspection and optical high-resolution defect cap-ture (HRDC), only critical defects are reviewed on the SEM. Moreover, auto-mated defect localization (ADL) provides hands-off automation for rapidly col-lecting high-magnification SEM images, improving SEM utilization and oper-ator productivity. All AMRAY 4000 series SEMs are fully compatible withIMPACT/Offline™ SEM ADC for hands-off automatic classification of SEMdefects. circle RS#031

Autumn 1998 Yield Management Solutions46

Windows NT® for Thin Film Measurement ToolsKLA-Tencor is the first to offer thin film measurement software which uses theWindows NT true multi-tasking and multi-thread operating system, result-ing in increased throughput and the lowest cost of ownership of any advancedthin film measurement system available. In addition to the film measurementsystem software, KLA-Tencor offers off-line software products that increaseoverall system productivity. These off-line products include: off-line spectralanalysis for recipe development and simulation, laplink for remote control anddiagnostics, and recipe generator for fast waferless recipe creation. The combination of the new software, operating system and off-line softwareproducts meets the advanced productivity requirements of thin film processcontrol.circle RS#032

HRP-220 High-Resolution ProfilerThe HRP-220 offers in-line surface measurement capabilities for meeting0.18 µm requirements and challenging applications such as metal and inlaidmetal CMP, and shallow trench isolation (STI), post-CMP. The HRP-220 canmeasure total wafer flatness with better than 1 nm vertical resolution. Thisunique capability builds on the HRP-200 platform which offers both thelong-scan capability, production-proven repeatability and ease-of-use of a sty-lus profiler, and the fine-area, high-resolution analysis and imaging capabili-ties of an atomic force microscope (AFM). The HRP-220 provides increasedproductivity and extended ease-of-use through its new customizable analysissoftware, Answer!, which automates monitoring of critical parameters. Inaddition, the HRP-220 capitalizes on the robustness and multi-tasking powerof Windows NT® architecture.circle RS#028

KLASS Phase Shift Focus MonitorThe KLASS Phase Shift Focus (PSF) Monitor™ software is an analysis pack-age designed to be used as part of a focus determination technique that takesadvantage of the correlation between image translation of a phase shifted over-lay target and stepper focus. Using a patented Phase Shift Focus Monitor testreticle available exclusively from Benchmark Technologies Incorporated, userscan quantify and consequently automate stepper focus determination in thefab. This software can be seamlessly integrated with the KLA-Tencor 5000series overlay measurement tools.circle RS#027

Autumn 1998 Yield Management Solutions 47

Some might think it

means to move slowly.

But in the world of silicon,

we see it as

a license to speed.

© 1998 KLA-Tencor, Inc.

On the tortuous road of yield management, we’re writing a new set of rules. One that moves well beyond die-per-wafer to define yield as a significant way to speed

time-to-market. Optimize silicon performance. Enhance productivity. And ultimately, have aprofound impact on both profitability and competitive advantage.

Admittedly, it’s a broader perspective than other companies take. And a critical one for thefabs of today and tomorrow. But it’s just what you’d expect from our singular focus on yieldenhancement, backed by over two decades of industry experience.

To put our integrated yield management technology to work for your company, please call1-408-875-4200, or visit www.kla-tencor.com.

You’ll see that we’ve got a better roadmap. And a faster way to get you there.