axilog: language support for approximate hardware design date 2015 georgia institute of technology...
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Axilog: Language Support for Approximate Hardware Design
DATE 2015
Georgia Institute of TechnologyAlternative Computing Technologies (ACT) Lab
Georgia Institute of Technology University of Minnesota UC San Diego
Amir Yazdanbakhsh Divya Mahajan Bradley ThwaitesJongse Park Anandhavel Nagendrakumar Sindhuja Sethuraman
Kartik Ramkrishnan Nishanthi Ravindran Rudra JariwalaAbbas Rahimi Hadi Esmaeilzadeh Kia Bazargan
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Approximate computingEmbracing error
• Relax the abstraction of near-perfect accuracy in general-purpose computing/communication/storage
• Allow errors to happen during computation/communication/storage– Improve resource utilization efficiency
• Energy, bandwidth, capacity, …
– Improve performance• Build acceptable systems from intentionally-made
unreliable software and hardware components• Avoid overkill and worst-case design
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Avoiding Worst-Case DesignApproximate Computing
Generality
PrecisionReliability
Determinism
Effici
ency
Perf
orm
ance
CostCost Physical Device
Circuit
Architecutre
Compiler
Programming Language
Application
Microarchitecture
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Goals
Design the first HDL for1) Approximate Hw
Design2) Approximate Hw
Reuse3) Approximate
Synthesis
Criteria
Approximate HDL shall be1) High-level2) Automated3) Backward compatible
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Safety in Hardware
Controller DatapathClock
Precise
Approximate
Precise
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Axilog Annotations
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Design Annotations
relax(relax_local)
restrict(restrict_global)
Reuse Annotations
approximate bridgecritical
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Design Annotations
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Relaxing Accuracy Requirementsmodule ripple_carry_adder(a, b, c_in, c_out, s)…
full_adder f0(a[0], b[0], c_in, w0, s[0])full_adder f1(a[1], b[1], w0, c_out, s[1])relax (s);
…
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Relaxing Accuracy Requirementsmodule ripple_carry_adder(a, b, c_in, c_out, s)…
full_adder f0(a[0], b[0], c_in, w0, s[0])full_adder f1(a[1], b[1], w0, c_out, s[1])relax (s);
…
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Scoping Approximation (relax_local)module full_adder
(a, b, c_in, c_out, s) …
relax_local (s);…
…full_adder f0 (…)full_adder f1(…)relax (s[0]);
…
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Scoping Approximation (relax_local)module full_adder
(a, b, c_in, c_out, s) …
relax_local (s);…
…full_adder f0 (…)full_adder f1(…)relax (s[0]);
…
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Restricting Approximation
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Restricting Approximation
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Restricting Approximation
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Restricting Approximation Globallymodule full_adder(a, b, c_in, c_out, s);
…approximate output s;relax (s);…
endmodule…restrict_global(s[31:0]);
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Restricting Approximation Globallymodule full_adder(a, b, c_in, c_out, s);
…approximate output s;relax (s);…
endmodule…restrict_global(s[31:0]);
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Reuse Annotations
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Outputs Carrying Approximate Semantics
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Critical Inputs…critical input reset;critical input clock;…
Next StateLogic
StateRegister
reset
clock
OutputLogic
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Bridging Approximate Wires to Critical Inputs …
and a1(s, a0, a1);relax (s);bridge (s);multiplexer m0(s, a0, a1,
out); …
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Bridging Approximate Wires to Critical Inputs …
and a1(s, a0, a1);relax (s);bridge (s);multiplexer m0(s, a0, a1,
out); …
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Baseline Synthesis Flow
Highest frequency with minimum power and area22
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Relaxability Inference Analysis
Identify the wires which are driving unannotated wires or annotated with restrict within the module under
analysis
Marks any wire that affects a globally restricted wire as precise
Identify the relaxed outputs of the instantiated submodules
Safe to approximate gates
Circuit under analysis with Axilog annotations
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Approximate Synthesis Flow
Axilog Code
AxilogCompiler
Safe toApproximate
Gates
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Measurements
Tools for Synthesis and Energy Analysis
• Synopsys Design Compiler• Synopsys Primetime
Timing Simulation with SDF back annotations
• Cadence NC-Verilog
Standard Cell Library
• TSMC 45-nm multi-Vt• Slowest PVT corner (SS, 0.81V, 0C) for baseline results
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FIR# lines: 113
Signal Processing
# AnnotationsDesign: 6Reuse: 5
InverseK# lines: 22,407
Robotics
# AnnotationsDesign: 8Reuse: 4
ForwardK# lines: 18,282
Robotics
# AnnotationsDesign: 5Reuse: 4
K-means# lines: 10,985Machine Learning
# AnnotationsDesign: 7Reuse: 3
Brent-Kung# lines: 352
Arithmetic Computation
# AnnotationsDesign: 1Reuse: 1
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BenchmarksArithmetic Computation, Signal Processing, Robotics, Machine Learning, Image Processing
Kogge-Stone# lines: 353
Arithmetic Computation
# AnnotationsDesign: 1Reuse: 1
Wallace Tree# lines: 13,928
Arithmetic Computation
# AnnotationsDesign: 5Reuse: 3
Neural Network# lines: 21,053Machine Learning
# AnnotationsDesign: 4Reuse: 3
Sobel# lines: 143
Image Processing
# AnnotationsDesign: 6Reuse: 3
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Energy Reduction
Brent
-Kun
gFI
R
Forw
ardK
Inve
rseK
K-mea
ns
Kogge
-Sto
ne
Wal
lace
Tre
e
Neu
ral
Sobe
l
Geom
ean
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
En
erg
y R
ed
ucti
on
Error ≤ 10%Error ≤ 5%
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Area Reduction
Brent
-Kun
gFI
R
Forw
ardK
Inve
rseK
K-mea
ns
Kogge
-Sto
ne
Wal
lace
Tre
e
Neu
ral
Sobe
l
Geom
ean
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
Are
a R
ed
ucti
on
Error ≤ 10%Error ≤ 5%
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10% Quality loss is nearly indiscernible to the eye Yet provides 57% energy savings
0% Quality Loss 5% Quality Loss 10% Quality Loss
Output Quality Degradation in Sobel
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Energy Reduction for Different PVT Corners
Brent-K
ungFIR
Forwar
dK
Inve
rseK
K-mea
ns
Kogge-Sto
ne
Wal
lace
Tre
e
Neura
l
Sobel
Geom
ean
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
En
erg
y R
ed
ucti
on
(SS, 0.81V, 125°C)(SS, 0.81V, 0°C)
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Axilog
54%
EnergySavings
1.9×
AreaReduction
2-12
CodeAnnotations
First HDL for Approximation• Design• Reuse• Automation• High-level• Backward-compatibility
http://www.act-lab.org/artifacts/axilog