HINDUSTHAN COLLEGE OF ARTS AND SCIENCECOIMBATORE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION SYSTEMS

STUDY MATERIAL

SUBJECT : DIGITAL PRINCIPLES AND APPLICATIONSCLASS : II – BSc ECSUNIT : III AND IV SEMESTER : IVSTAFF : S.SATHYADEEPA M.Sc., M.Phil.,ME

LOGIC CIRCUITS:Digital circuits are designed for two-state operation. The adjacent

two points on the load line namely saturation and cutoff are used for digital operation. Square wave input is given for digital operation and output voltages has only two states, either low or high. The gate is a digital circuit with one or more input voltages but only one output voltage. By connecting the gates in different ways, we can build circuits that perform arithmetic and other functions associated with the human brain. Because the gates simulate the mental processes, they are called logic circuits.TRUTH TABLE: It is a table which shows all the inputs and outputs possibilities for a logic circuit. It is also known as table of combinations. It gives what combinations of input will produce an output.LOGIC EQUATION: It gives a relationship between independent input binary variables and dependent output variables.GATES:

A Gate is defined as a logic circuit with one output and two or more logic inputs. The output signal occurs only for certain combination of input variables. The various logic gates are OR, AND, NOT, NAND, NOR and Exclusive OR gate etc. AND GATES:

AND gate has two or more logic inputs and single output. The AND gate has a high output only when all inputs are high. The AND gate is always represented by the standard symbol as given below. AND GATE:

The truth table for a two input AND Gate is given below

A B C

1

A

BC

0 0 00 1 01 0 01 1 1

C= A.B means that if ‘A’ is true and ‘B’ is true then ‘C’ will be true under any other condition ‘C’ will be false. This gate will provide +ve (1) on its output if and only if both ‘A’ and ‘B’ inputs are +ve (1). Under any other set of input condition the output will be –ve (0). AND gates can have any number of inputs.OR GATE:

The OR gate has two or more input signals but only one output signal. If any input signal is high, the output signal is high. If both inputs are low, the output is low. If either input is high, the gate with the high input conducts and the output is high. OR Gate:

Truth Table for Two Input OR Gate:

A B C0 0 00 1 11 0 11 1 1

The ‘OR’ Operator is indicated by using a +ve sign A+B=C means that if ‘A’ is true or ‘B’ is true. Then ‘C’ will be true. Under any other set of conditions ‘C’ will be false (0). This ‘OR’ operator is called an inclusive OR because it includes the case when both inputs are true. Logic expression for OR operation is Y=A+B+C+…..+NNOT GATE:

An NOT gate is a gate with only one input signal and one output signal. The output state is always the opposite of the input state. An inverter is also called a NOT gate because the output is not the same as the input. The output is sometimes called the complement(opposite) of the input. It is also called as complementary circuit or inverter. If the input is in state “1”, the output is in 0 state or vice versa. NOT Gate:

Truth table :

A Y0 11 0

The logic expression for NOT gate is Y= A’.The symbol for the NOT operator is the ‘overscore’ or ‘bar’

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A

BC

A Y=A’

NAND GATE: If a NOT Gate follows an AND Gate, the combination is called a NAND Gate and is symbolically represented as below:

A B

The truth table for NAND Gate is

A B Y0 0 10 1 11 0 11 1 0

The output of NAND gate is at “1” level if any one of the input is at “0” level. If all the inputs are “1” level the output will be at “0” levelNOR GATE: By combining OR gate and NOT gate we obtain NOR gate, OR gate followed by NOT gate gives NOR gate is symbolically represented as

In this gate the output is at “1” level only if all the inputs are at “0” level. For any other input condition the output is “0”. The logic expression for NOR gate is Y=A+B+C+......+N. The truth table is given as

A B Y0 0 10 1 01 0 01 1 0

BOOLEAN ALGEBRA: In 1954 George Boole invented a symbolic logic, known today as Boolean

algebra. It is an algebra where the variables are permitted to have one of only two possible values. The possible two values may stand for truth or falsehood of statement, ON or OFF states of a switch, or presence or absence of one of the two voltage levels. Thus Boolean-Variables are bi-valued or popularly known as binary in nature.

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Y=A.B

Y= (A+B+…….N)AB

Y

These binary variables are designed as “0” and “1”. Either of these binary variables are denoted by “Bit”. The word “Bit” is derived from binary digit. In logic circuits these “0” and “1” variables will represent voltage levels. These are two types of logic systems, namely positive and negative logic systems. Positive logic is a logic where Boolean variable “1” represents the most positive voltage level. Negative logic is a logic where “1” represents the most negative logic level.LAWS AND THEOREMS OF BOOLEAN ALGEBRA:

As in ordinary algebra, the commutative, associative and distributive laws are valid for Boolean algebra.Commutative laws: A + B = B + A A . B = B . AAssociative laws: A + ( B + C ) = ( A + B ) + C A . ( B . C) = ( A . B ) . CDistributive laws: A . ( B + C) = AB + AC Basic Relations valid for Boolean Algebra

OR ANDA + 0 = A A. 0 = 0A + 1 = 1 A. 1 = AA + A = A A. A = AA + A = 1 A. A = 0

BOOLEAN ALGEBRA RULES:1) 0 + A = A2) 1 + A = 13) A + A = A4) A + A = 15) 0 . A = 06) 1 . A = A7) A . A = A8) A. A’ = 09) (A’)’ = A10) A + B = B + A11) A . B = B . A12) A + ( B + C) = ( A + B) + C13) A(BC) = (AB)C14) A(B+C) = AB+AC15) A+AC = A16) A(A+B) = A+B17) (A+B) (A+C)= A+BC18) A+A.B = A+B19) XY+YZ+YZ=XY+Z

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Worked Examples: Simplify the given Boolean Expressions1) Y = A + A’B + C(A+B) = (A + B) + C (A+B) By applying rule 18 = (A + B) (1 + C) = A + B By applying rule 2So the simplified expression is Y=(A + B)2) Y = ( A’ + B) (A + B) = (A’ + B) A + (A’ + B)B By applying distributive law = A’A + BA + BA’ +BB By applying distributive law = 0 + BA + BA’ + BB By applying rule 4 = BA + A’B + BB By Rule 1 = A’B + BA + BB By Commutative Law = A’B + BA + B By Rule 7 = A’B + (A+1)B By Distributive Law = A’B + B = (A’+1) B By Distributive Law = BTherefore the simplified expression is Y=B3) Show that (A+B)’ (A’+B)’ = 0L.H.S : (A+B)’ (A’+B)’ = A’B’(A’+B)’ By DeMorgans Law = A’B.AB’ By DeMorgans Law = BA’. AB’ By Commutative Law = B’.0.B By Rule 8 = 0 = R.H.S (Right Hand Side)

KARNAUGH MAPS:Boolean algebra can be used to simplify the logiccircuits. However, it is

sometimes difficult because, there are no specific rules for predicting each successive step in the simplifying process. The map method provides a simple, straightforward procedure for simplifying Boolean functions. This method may be regarded as a pictorial arrangement of the truth table which allows an easy interpretation for choosing the minimum number of variables needed to express the function algebraically. The map method is known by the names KARNAUGH MAPS and Veitch Diagram.

Each combination of the variables in a truth table is called a minterm. So a funcation of n variables will have 2n minterms, equivalent to the 2n binary numbers obtained from n digits. Obviously a Boolean function will be equal to 1 for some minterms and 0 for others. The map is a diagram made up of squares, with each square representing one minterm. Therefore there will be 2n squares in the map, if the Boolean expression has n variables. The maps for functions of two, three and four variables are shown below:Karnaugh Map for two variables:

B’(0) B(1)A’(0) 0 1A(1) 2 3

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Karnaugh Map for three variables

Karnaugh Map for four variables

The combination of the variables represented by a square may be found byConcatenating the labels of the corresponding row and column. For eg, the first square in the 2 variable and table represents the minterm A’B’(00 in binary). The decimal equivalent is written the square for clarification. If a Boolean expression is given, let us now see how this map is used to simplify it. First find out the truth table for the given expression. Then put a 1 in the squares which represent the minterms producing a 1 in the truth table, and a 0 in all the remaining squares. By finding various patterns of the adjacent squares which are marked by a 1 and combing them, it is possible to derive a simplified form for the given expression. There are 3 max patterns of adjacent squares: pairs, quads and octets.PAIRS:

This pattern will contain two adjacent squares that have a 1. Anyone of the variables will be in complemented form, in one minterm and in uncomplemented form in the other represented by the two squares. So if these two minterms are combined the variable will drop out of the expression. Consider the following example.

In this table the 1s are horizontally adjacent. The first 1 represents the minterm A’B’ and the second 1 represents A’B. Obviously the variable B changes from complemented to uncomplemented form, and A remains in complemented form. So the variable B drops out. This can be explained algebraically as follows. The two minterms A’B’ and A’B will be comined as A’B+A’B , by distributive law it will reduce to A’(B’+B) and naturally the variable B drops out and the simplified expression becomes A’.

QUADS:

B’C’ B’C BC BC’00 01 11 10

A’(0) 0 1 3 2A(1) 4 5 7 6

C’D’ C’D CD CD’00 01 11 10

A’B’(00) 0 1 3 2A’B(01) 4 5 7 6AB(11) 12 13 15 14AB’(10) 8 9 11 10

B’(0) B(1)

A’(0) 1 1

A(1) 0 0

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A quad is a group of four adjacent 1s. They can be end to end in a single row or column, or in the form of a square. When you see a quad, always encircle it, because it leads to a simpler product. In fact, a quad means that two variables and their complements will drop out of the Boolean expression.

The four 1s in the column can be encircled and it form a quad and the expression becomes CD. We can prove algebraically as Y= A’B’CD + A’BCD + ABCD + AB’CD = A’CD(B’+B) + ACD (B’+B) = A’CD(1) + ACD(1)

= CD(A’+A) = CD So the simplified expression is CD.OCTET: An octet is a group of eight adjacent 1s. An octet will eliminate 3 variables from the Boolean expression. Consider the following map.

The simplified Boolean expression becomes B. This is because, the octet may be considered as two quads as follows.

C’D’ (00)

C’D (01)

CD (11)

CD’ (10)

A’B’(00)0 0 1 0

A’B(01)0 0 1 0

AB(11)0 0 1 0

AB’(10)0 0 1 0

C’D’(00)

C’D(01)

CD(11)

CD’(10)

A’B’(00)0 0 0 0

A’B(01)1

1 1 1AB(11)

1 1 1 1AB’(10)

0 0 0 0

C’D’(00) C’D(01) CD(11) CD’(10)

A’B’(00)

0 0 0 0A’B(01)

1 1 1 1AB(11)

1 1 1 1AB’(10)

0 0 0 0

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So the Boolean expression becomes BC’ + BC = BKARNAUGH SIMPLIFICATIONS: We saw that a pair eliminates a single variable. A quad eliminates two variables and an octet eliminates 3 variables. Therefore when simplifying a Karnaugh map, we should look for octets first, then for quads and then for pairs, as our objective is to find out an equivalent expression with as minimum number of variables as possible.Example : 1 Suppose after translating the truth table of a Boolean expression we get the following map.

As said earlier we look for octets. There are none so we look for quads. There are two quads we encircle them. Then we find that there is one pair, and encircle it. We get the map as follows.

By OR ing the expressions after eliminating the appropriate variables we get the simplified expression as follows Y = A’B’D + AC’ + CD’

C’D’(00) C’D(01) CD(11) CD’(10)

A’B’(00) 0 1 1 1

A’B(01) 0 0 0 1

AB(11) 1 1 0 1

AB’(10) 1 1 0 1

C’D’(00) C’D(01) CD(11) CD’(10)

A’B’(00) 0

1 1 1

A’B(01)

0 0 0 1AB(11)

1 1 0 1

AB’(10)1 1 0 1

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OVERLAPPING GROUPS: Assume that we have to simplify the following map

After encircling the octet, only a single 1 remains. So the map and the expression will becomes as Y = A + A’BC’D. Obviously this expression will require a relatively complex circuit. So the single 1 may be combined with its adjacent 1 , as shown below.

So the expression will become Y=A+BC’D. This is called overlapping of groups. In otherwords overlapping of groups means that the same may be used more than onceREDUNDANT GROUPS:

Redundant group is a group whose 1s are already used by other groups. Consider the following map.

First the quad is encircled

C’D’(00)

C’D(01)

CD(11)

CD’(10)

A’B’(00) 0 0 0 0

A’B(01) 0 1 0 0

AB(11) 1 1 1 1

AB(10) 1 1 1 1

C’D’(00)

C’D(01)

CD(11)

CD’(10)

A’B’(00) 0 0 0 0

A’B(01) 0 1 0 0

AB(11) 1 1 1 1

AB(10) 1 1 1 1

C’D’(00)

C’D(01)

CD(11)

CD’(10)

A’B’(00) 0 0 1 0

A’B(01) 1 1 1 0

AB(11) 0 1 1 1

AB(10) 0 1 0 0C’D’(00)

C’D(01)

CD(11)

CD’(10)

A’B’(00) 0 0 1 0

A’B(01) 1 1 1 0

AB(11) 0 1 1 1

AB(10) 0 1 0 0

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Next, the remaining 1s are grouped into pairs by overlapping

The simplified expression is BC + A’BC’ + A’CD + AC’D + ABCConsider this simplification

Since all the 1s are covered by the pairs. The simplified expression of the above diagram is A’BC’ + A’CD + AC’D + ABC. It contains one less product than the previous simplification STANDARD FORMS:

Two canonical forms of Boolean algebra are sum of minterms and product of maxterms where each minterm or maxterm must contain all the variables either complemented or uncomplemented. Another way to express Boolean function is in

C’D’(00)

C’D(01)

CD(11)

CD’(10)

A’B’(00) 0 0 1 0

A’B(01)

1

1

1 0

AB(11) 0 1

1 1

AB(10) 0 1 0 0

C’D’(00)

C’D(01)

CD(11)

CD’(10)

A’B’(00) 0 0

1 0

A’B(01)

1 1

1 0

AB(11) 0 1

1 1

AB(10) 0 1 0 0

10

standard form. In this configuration the terms that form the function may contain 1,2 or any number of literals. There are 2 types of forms1)Product Of Sums Method 2) Sum Of Products MethodPRODUCT OF SUMS METHOD: Sum Term: A sum term is a single variable or the sum of several variables. The variables may or may not be complemented. For example the term X.Y.Z is a product term X+Y is a sum term.Product – Of – Sums Expression : A product-of-sums expression is a sum term or several sum terms logically multiplied. This method is a complement of the sum of products method. That is in this method we will find different patterns of adjacent 0s instead of 1s. The remaining procedure is the same except that, the final expression will be complemented. Therefore the simplified expression will be in the form of product of sums. That is the expression will be a product of components which are sum of different variables. Let us solve the following map by product of sums method. C’D’(00) C’D(01) CD(11) CD’(10) A’B’(00)

A’B(01)

AB(11)

AB’(10)

In this map we have a quad and a pair of 0’s. We encircle them. C’D’(00) C’D(01) CD(11) CD’(10) A’B’(00)

A’B(01)

AB(11)

AB’(10)

So, the expression will become Y=A’D + AB’C’. Complementing this we getY = (A + D’) (A’ + B + C)

MAXTERMS: N variables forming an ‘OR’ term with each variable being primed or unprimed provide 2n possible combinations is called MAXTERMS. Each maxterm is obtained from an ‘OR’ term of the ‘n’ variable with each variables being unprimed with the corresponding bit is ‘0’ and prime if it ‘1’

X Y Z MINTERMS MAXTERMS 0 0 0 X’Y’Z’ X+Y+Z 0 0 1 X’Y’Z X+Y+Z’ 0 1 0 X’YZ’ X+Y’+Z 0 1 1 X’YZ X+Y’+Z’

1 0 0 1

1 0 0 1

1 1 1 1

0 0 1 1

1 0 0 1

1 0 0 1

1 1 1 1

0 0 1 1

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1 0 0 XY’Z’ X’+Y+Z 1 0 1 XY’Z X’+Y+Z’ 1 1 0 XYZ’ X’+Y’+Z 1 1 1 XYZ X’+Y’+Z’

Rules for obtaining the maxterms from the Karnaugh Map1)Fill in Karnaugh Map with 1’s and 0’s depending on the sum of minterm expression.2)For each zero in the square write the corresponding maxterm

Obtain the product of maxterms for the function f(A,B,C)= ∑(2,3,4,6). Draw the karnaugh map and find the maxterms. B’C’(00) B’C(01) BC(11) BC’(10) A’(0) A(1)

We get a function like this A’B’C’+A’B’C+AB’C+ABC find the complement of this we get the maxterm. So the corresponding maxterm isY= (A+B+C)(A+B+C’)(A’+B+C’)(A’+B’+C’)SUM OF PRODUCTS METHOD: Product Term: A product term is a single variable or the logical product of several variables. The variables may or may not be complemented. Sum-Of-Products Expression: A sum-of-products expression is a product term or several product terms logically added. The following are all sum –of-products expressions 1) X 2) X’Y’ + X’Y’Z’ 3) XY + Z 4) X+Y The following are product-of-sums expressions 1) (X+Y)(X+Y’)(X’+Y’) 2) (X+Y+Z)(X+Y’)(X’+Y’) 3) (X+Y)XSo far, we have been finding different patterns of adjacent 1’s in the map, dropped the appropriate variables, and then summed the remaining minterms. The result was in the form of sum of products. That is, the individual minterms were product of variables, and the final expression was a sum of these minterms. So, the method may also be called sum of products method.

Show the sum-of-products and products-of-sums Circuits for the Karnaugh Map C’D’(00) C’D(01) CD(11) CD’(10) A’B’(00)

A’B(01)

AB(11)

AB’(10)

The Sum-Of-Products Method:

C’D’(00) C’D(01) CD(11) CD’(10)

0 0 1 1 1 0 0 1

0 0 0 0

0 0 0 1

1 1 1 1

1 1 1 1

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A’B’(00)

A’B(01)

AB(11)

AB’(10)

We get Y= A + BCD’

The Product-of-Sums Method: C’D’(00) C’D(01) CD(11) CD’(10) A’B’(00)

A’B(01)

AB(11)

AB’(10)

We get Y = A’B’ +A’C’+A’DThen complement the answer we get product-of-sums So Y=A’B’+ A’C’ + A’D = (A+B)(A+C)(A+D’)So finally we get Y=(A+B)(A+C)(A+D’)Don’t Care Conditions: In some digital systems, certain input conditions never occur during normal operation, therefore the corresponding output never appears. Sometimes it doesn’t matter what the output is for a given minterm. It can be either 0 or 1. To indicate this, we use an X in both the truth table and in the map. As they can be considered as either 0 or 1, the X entries in a map may be used to our best advantage. That is, if a larger group can be formed by considering the Xs as 1s, we can make use of them; Otherwise, the Xs may be ignored. Consider the following map. C’D’(00) C’D(01) CD(11) CD’(10) A’B’(00)

A’B(01)

AB(11)

AB’(10)

We can form the groups as show in the following map. C’D’(00) C’D(01) CD(11) CD’(10) A’B’(00)

0 0 0 0

0 0 0 1

1 1 1 1

1 1 1 1

0 0 0 0

0 0 0 1

1 1 1 1

1 1 1 1

1 0 1 0

1 1 1 0

X X X X

X X X X

1 0 1 0

1 1 1 0

X X X X

X X X X13

A’B(01)

AB(11)

AB’(10)

Note that the some of the Xs are used in forming groups and others are ignored. It is obvious that the simplified expression is Y = CD + C’D’ + BDConvert to sum of products (AB +C) (B+C’) (AB +C) (B+C’) = ABB +ABC’ +BC + CC’ = AB + ABC’ + BC + 0 = AB ( 1+C’) +BC = AB + BC (SUM –OF- PRODUCTS)And B(A+C) PRODUCT-OF-SUMSDIGITAL CIRCUITS: Digital circuits can be broadly classified into two types

1) Combinational Circuit 2) Sequential CircuitCOMBINATIONAL CIRCUIT:

A combinational circuit is described as an interconnection of logic gates whose outputs always depend on the combination of inputs at any time, without regard to their previous states. A combinational circuit consists of input variables, logic gates and output variables. The logic gates accept signals from the inputs and generate signals to the outputs. A block diagram of a combinational circuit is shown below. The ‘n’ inputs and ‘m’ outputs, in many applications come from or go to storage registers associated with the combinational logic circuit. Combinational Logic Circuit

‘n’ inputs ’m’ outputs

Since each input binary variable can take two values (0 or 1), for the ‘n’ input variables, there are 2n possible combinations of binary input values. For each possible input combination, there is one and only one possible output combination. In otherwords, a combinational circuit can be described by ‘m’ Boolean functions, one for each output variable.SEQUENTIAL CIRCUIT:

The logic gates have a set of inputs and set of outputs. They have no memory or feedback path. To have such memory feature sequential logic circuits are developed. In sequential logic circuits the output conditions of present time are determined by both present and past input conditions. These circuits have feed back loops to maintain the past output. A flip flop circuit is a one such sequential logic circuit.MULTIPLEXERS:

Multiplexer means “many into one”. A multiplexer is a circuit with many input but only one output. By applying control signals, we can steer any input to the output.

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The figure below illustrate Multiplexer. The circuit has n input signals, m control signals and 1 output signal. ‘m’ Control Signals

----------

‘n’ input signals 1 output signal

Multiplexer also known as data selector. The output line is connected to the appropriate input line depending on the contacts of the control lines.

A 4 line to 1 line multiplexer is shown in the figure below. Each of the four input lines, I0 to I3 is applied to one input of an AND gate. Control line S0 to S1 are decoded to select a particular AND gate. The function table shown in the given table below shows the input-to-output path for each possible bit combination of the control lines.

A 4x1 MUX S0 S1 Y 0 0 I0

0 1 I1

1 0 I2

1 1 I3

The block schematic of the multiplexer is shown in the figure above. If we assume S1=1 and S0=0 and S1=1 , the AND gate associated with input I1 has two inputs. The value of the output is therefore equal to I1 itself. Thus there is a path from the selected input line to the output line. This is why a multiplexer (often abbreviated as MUX) is also called a data selector.

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I0

I1

I2

Y

S0

S1

DEMULTIPLEXER: Demultiplexer does the reverse function of a multiplexer. A demultiplexer means

one into many. A demultiplexer is a logic circuit with one input and many outputs. By applying control signals, we can steer the input signal to one of the output lines. Demultiplexer also known as data distributor. The circuit has 1 input signal, m control signals and n output signals. The selection of a specific output line is controlled by the ‘n’ selection lines. A 1 to 4 line Demultiplexer is shown below. The single input E has a path to all the 4 outputs, but the input information is directed to only one of the output lines as specified by the binary value of the two control lines A and B. When the S0S1=00, the upper AND gate is enabled while all other AND gates are disabled. Therefore, data bit D is transmitted only to Y0 output giving Y0=D

Truth Table if D is the input D S1 S0

S1 S0 Y0 Y1 Y2 Y3

0 0 D 0 0 00 1 0 D 0 01 0 0 0 D 01 1 0 0 0 D

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I3

Y1

Y2

SEQUENTIAL LOGIC:The outputs of the digital circuits considered so far are dependent entirely on the

inputs, if the input changes, the output also changes. Digital computers, however need to store binary numbers in what are called memory elements. A flip-flop is one such circuit. The combinational circuit ie., the outputs at any instant of time depend entirely on the inputs present at that time. Although every digital system is likely to have combinational circuits, most systems encountered practice also include memory elements, ie., where outputs depend also on the previous inputs. Such a circuit is called a sequential circuit. A flip-flop is a basic circuit for storing information in a digital machine. There are many fundamental types of flip-flops. All these flip-flops have the following two characteristics which are common to all flip-flops

1) The flip-flop is a bistable deviceIe.,a circuit with two stable states. The flip-flop circuit can remember, or store, one binary bit of information. It responds to inputs. If an input causes it to go to 1 state, it will remain there and remember a 1 until some signal causes it to go the 0 state. Similarly once placed in 0 state, it will remain there until told to go to the 1 state. This single characteristics is the basis for information storage in the operating or calculating sections of a digital computer.2)The flip-flop has two output signals, one of which is the complement of the other.

RS FLIP-FLOP:Each flip-flop is given a name. Convenient names are letters, such as X or Y or A

or B, or letter number combinations such as A1 or B2. The flip-flop in the figure given below is called X. It has two outputs, the X output and the X’ ouptut. The X and X’ output lines are always complements, that is , if the X output line has a 1 signal the X’ output line has a 0 signal and if the X output line has a 0 signal, output line X’ has a 1 signal. The state of the flip-flop is taken to be the state of the X output. Thus if the output line X has a 1 signal on it, we say that “flip-flop X is in the 1 state”. Similarly, if the X line contains a 0 signal , we say that “flip-flop X is in the 0 state”

There are two input lines to the RS flip-flop. These are used to control the state of the flip-flop. The rules are as follows

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Y3

Y4

1) As long as both input lines S and R carry 0 signals, the flip-flops remains in the same state, that is, it does not change state.

2) A 1 signal on the S line (the SET line) and a 0 signal on the R line cause the flip-flop to “set” to the 1 state.

3) A 1 signal on the R line (the RESET line) and a 0 signal on the S line cause the flip-flop to “reset” to the 0 state.

4) Placing a 1 on the S and a 1 on the R lines at the same time is forbidden. If this occurs, the flip-flop can go to either state (This in effect, an ambiguous input in that it is telling the flip-flop to both SET and RESET at the same time).

The flip-flop actually has two outputs, defined in more general terms as X and X. It should be clear that regardless of the value of Q, its complement is Q .There are 2 inputs to the flip-flop defined as R and S. The input/output possibilities for this RS flip-flop are summarized in the truth table

R S Q Action0 0 Last Value No Change0 1 1 SET1 0 0 RESET1 1 ? FORBIDDEN

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RS FLIP-FLOP WITH NOR GATE:

RX

XS

A flip-flop circuit can be constructed from two NAND gates or two NOR gates. The flip-flop circuit using NAND gate is shown below.RS FLIP-FLOP WITH NAND GATE:

S Q

Q

R

TRUTH TABLE

R S Q1 1 LAST STATE1 0 10 1 00 0 ?(FORBIDDEN)

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The NAND gate is different from that for the NOR gate. A low on any input to a NAND gate will force its output high. Thus a low on the S input will set the latch(Q=1 and Q’=0). A low on the R’ input will reset it (Q=0). If both R’ and S’ are high, the flip-flop will remain in its previous state. Setting both R’ and S’ low simultaneously is forbidden.CLOCKED RS FLIP-FLOP:

The basic flip-flop or RS flip-flop as it stands is an asynchronous sequential circuit. By adding gates to the inputs of the basic circuit, the flip-flop can be made to respond to input levels during occurrence of a clock pulse. The clocked RS flip-flop shown in the figure below.

Consists of a basic NOR flip-flop and two AND gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (abbreviated CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs is allowed to reach the basic flip-flop. The set state is reached with S=1, R=0 and CP=1. To change to the clear state, the inputs must be S=0, R=1 and CP=1. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate ie., either state may result, depending on whether the set or the reset input of the basic flip-flop remains a 1 longer before the transition to 0 at the end of the pulse. In order to overall function of the RS flip-flop , a square wave signal is included in the circuit (i.e., two AND gates) called clock, which is used to enable or disable the circuit. When the CLK is high then the circuit is enabled. When the CLK is low then the circuit I disabled. When CLK=1 and it works as RS flip-flop. According to its input it will have its states.D FLIP-FLOP:

In the RS flip-flop, when both the inputs R and S are simultaneously high, output Q cannot be predicted. This race condition should be avoided ie., R and S should not be high simultaneously. Also there are 2 inputs R and S. To store a high bit, S should be high, to store a low bit, you need a high R. Generation of two signals to drive a flip-flop is a disadvantage in many applications. Furthermore, the forbidden condition of both R and S high may occur inadvertently. A modification of the RS flip-flop is a new kind of flip-flop, a circuit that needs only a single input line.

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R

S

Q

Q

CP (CLOCK PULSE)

There are two types of D flip-flop, the unclocked one and clocked one. The unclocked type is shown below and its truth table.

The D input goes directly to the S input and its complement to R. Hence both S and R cannot simultaneously go to 1. The output Q takes on the value of D. Thus it may be noted that the D flip-flop sets or resets as D goes high or low.

The circuit of a clocked D flip-flop is shown below. In this a clock signal, CLK has been added so that the flip-flop will be enabled (or be active) only when the clock is high(1). CLOCKED D FLIP-FLOP

When the clock is low, both AND gates are disabled, any change in D will not be transmitted to Q or Q will remain in its last state. When the clock is high, both ANDgates are enabled. In this case, it will function similar to an unclocked D flip-flop. The logic symbol of a clocked D flip-flop and its truth table are shown below:

CLK D Q COMMENT0 X Last State No Change1 1 1 Set1 0 0 Reset

Thus Q follows the value of D while the clock pulse is high. This type of flip-flop is called a “D type latch” and is widely used for temporary storage of data in counters, digital voltmeters etc. It receives its name from its ability to transfer data into a flip-flop.JK FLIP-FLOP:

A JK Flip-flop is a refinement of the RS flip-flop in that the indeterminate state of the RS type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop(note that in JK flip-flop the letter J is for set and the letter K is for

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D Q

CLK Q

S Q

R Q

D

CLK

D S Q

R Q

clear). Flip-flops can be used to build counters and JK flip-flop is ideal for such purposes. J and K are called the control inputs because they determine the output when the clock is high. As AND gates are used, changes at the output will take place when a positive clock pulse is applied. It is called Positive edge triggered flip-flop.

K Q

CP

J

Q

Logic DiagramTruth Table:

CLK J K Q COMMENT*X 0 0 Last Value No Change** 1 0 1 Set

0 1 0 Reset1 1 Toggle --------

*Any value **Positive edgeWhen both J and K inputs are low, whatever be the level of the clock, output

remains at the previous value. Changes will take place only when J and K is non-zero and at the positive edge of the clock. During the positive edge of the clock input the following changes in J and K will alter Q as below:* When J=1, K=0 ; bottom AND gate is disabled and hence Q=1** When J=0, K=1; top AND gate is disabled and Q=0*** When J=1,K=1 in this case, it is possible to set or reset the flip-flop.

If Q is high, the lower AND gates posses a RESET signal during the next positive edge of the clock, making of low. On the other hand, a low Q means Q’=1. The top AND gate passes a SET signal during the next negative edge of the clock, making Q to high. Thus, during each positive edge of the clock, Q changes the state from low to high and high to low ie., toggling. “Toggle” means to switch from one state to the other state. The following figure show the logic symbols for positive edge triggered and negative edge triggered JK flip-flops respectively. A negative edge triggered JK flip-flop is similar to positive edge triggered one , the change will take place during the negative edge of the clock.

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Logic symbols of JK flip-flop:

Positive Edge triggered JK flip-flop Negative Edge triggered JK flip-flop

JK MASTER SLAVE FLIP-FLOP:

The figure shows one way for making a JK Master Slave flip-flop. It provides another way to avoid racing. It consists of two JK flip-flops, connected in cascade as shown. The first is a positive edge triggered one, another is negative edge triggered . To begin with the master responds to its J and K inputs before the slave. If J=1 and K=0, the master sets on the positive clock edge. The high Q output of the master drives the J input of the slave, so when the negative clock edge hits, the slave sets, copying the action of the master. If J=0, K=1 the master resets during the positive edge of the clock and the slave also resets during the negative clock edge. If the master J and K are high, its outputs starts toggling, the slave follows it. Regardless of what the master does, the slave copies it. JK flip-flop is a main counting device.T FLIP-FLOP: The T flip-flop is a single input version of the JK flip-flop. The figure below shows a clocked T flip-flop the “T” standing for the toggling characteristic of the flip-flop. When input T is high (ie., 1) and when the clock pulse occurs, the output Q changes or toggles to its complement value.

The truth table is given below. T Q(t) Q(t+1)0 0 01 0 10 1 11 1 0

Each incoming clock signal alternatively sets and resets the output Q, the flip-flop toggles and it takes two triggers to complete one cycle. The output therefore has half the frequency of the input.DECODERS:

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J Q

Clk

K Q

J Q

Clk

K Q

J Y

Clk

K Y2

J Q

clk

K Q

Digital data processing requires the conversion of digital information into equivalent analog information or decimal information or memory addressing etc. For these purpose decoders are used. A binary information in ‘n’ bits is capable of representing upto 2n distinct elements. A decoder consists number of logic gates and selects a single input for a particular combination of inputs. A decoder with n inputs would require 2n gates and provide 2 n outputs will be selected. A decoder is a device that takes a binary word and energises a particular output line based upon the contents of that word. Thus a binary input from ‘n’ input lines can be converted to a maximum of 2 n

output lines. The block diagram represents a typical decoder.

1 1

2INPUT 2 OUTPUT

3

A binary code of ‘n’ bits is capable of representing up to 2 n distinct elements of the coded information. A decoder converts binary information from n input bits to a maximum of 2 n unique output lines.A decoder for 2 input lines A1,A2 and 4 output lines Q1,Q2,Q3 and Q4.

Decoder with 2 inputsA2 A1

Q1

Q2

Q3

For each combination of input lines, only one output will be at high level as given in the truth table

A1 A2 Q1 Q2 Q3 Q4

0 0 1 0 0 0

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...DECODER

8

1 0 0 1 0 00 1 0 0 1 01 1 0 0 0 1

ENCODERS: An encoder is a combinational logic circuit which produces a reverse operation from that of a decoder. An encoder has 2n(or less) input lines and n-output lines. The output lines generate the binary code for the 2n input variables. An encoder operates with number of inputs. At any time only one of its inputs will have a logic level. SHIFT REGISTERS AND ITS TYPES:

A register capable of shifting its binary information either to the right or to the left is called a shift register. The logical configuration of a shift register consists of a chain flip-flop connected in cascade, with the output of one flip-flop connected to the input of the next flip-flop. All flip-flops receive a common clock pulse that causes the shift from one stage to the next. The figure shows a shift register. This circuits accept information from some input source and then shifts this information along the chain of flip-flops, moving it one flip-flop each time a positive-going clock signals occurs.SHIFT REGISTER WITH WAVEFORM

CLOCK

X3INPUT

CP1 CP2 CP3 CP4 CP5

INPUT

X1

X2

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S X1

R X1

S X2

R X2

S X3

R X3

X3

The figure shows a typical sequence of input signals and flip-flop signals in the shift-register. The input value is taken by X1 when the first positive going clock signal arrives. Anything in this and the remaining flip-flops is shifted right at this time. We have assumed that all the flip-flops are initially in their 0 states. In the figure, the input waveform is at 1 when the first clock occurs, so X1 goes to the 1 state.

When the second positive going signal occurs, the input is at 0; so X1 goes to the 0 state, but the 1 in X1 is shifted into X2. When the third clock edge appears, the input is at 1; so X1 takes a 1, the 0 previously in X1 is shifted into X2, and the 1 in X2 goes into X3. This process continues. The values in X3 are simply dropped off the end of the register.

Each flip-flop takes the value in the flip-flop on its left when the shift register is stepped. The reason is as follows: If, for instance, X1 is in the 1 state; then its X output line is a 1 and thus the S input of X2 will be a 1; and the X’ output of x, will be a 0, and so the R input of X2 will be a 0. This causes X2 to take its 1 state when the clock pulse occurs. A 0 in X1 will cause X2 to go to 0 when the clock pulse occurs, and the reason for this should be analyzed.

This is one problem that could occur if certain design precautions were not taken with the flip-flops. If the race problem occurs it is handled by designing the flip-flops so that they take the value at their inputs just as the clock positive-going edge occurs and not slightly after the clocks rise time.

Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines what goes into the leftmost flip-flop during the shift. The serial output is taken from the output of the rightmost flip-flop prior to the application of a pulse. Although this register shifts its content to the right. A unidirectional shift register can function either as a shift-right or as a shift-left register.RIPPLE COUNTERS: A counter is a register capable of counting the number of clock pulses that have arrived at its clock input. In its simplest form it is the electronic equivalent of a binary odometer. Since the clock pulses occur at known intervals, the counter can be used as an instrument for measuring time and therefore period or frequency. There are basically two different types of counters-synchronous and asynchronous. The ripple counter is simple and straightforward in operation and construction and usually requires a minimum of hardware. It does, however, have a speed limitation. Each flip-flop is triggered by the previous flip-flop, and thus the counter has a cumulative settling time. Counters such as these are called serial or asynchronous. An increase in speed of operation can be achieved by use of a parallel or asynchronous counter. Every flip-flop is triggered by the clock ( in asynchronous) and thus settling time is simply equal to the delay time of a single flip flop.

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ASYNCHRONOUS COUNTERS: A binary ripple counter can be constructed by use of clocked JK flip-flops. The figure below shows three Master-Slave, JK flip-flops connected in cascade. The system clock, a square wave, drives flip-flop A. The output of A drives B, the output of B drives flip-flop C. All the J and K are tied to +Vcc. This means that each flip-flop will change state (toggle) with a negative transition at its clock input. When the output of a flip-flop is uses as the clock input for the next flip-flop, we call the counter a ripple counter or asynchronous counter. The A flip-flop must change states before it can trigger the B flip-flop, and the B flip-flop has to change states before it can trigger the C flip-flop. The triggers move through the flip-flops like a ripple in water. The waveforms below show the action of the counter as the clock runs. The flip-flops are all initially reset to produce 0 outputs. If we consider A to be the least-significant bit(LSB) and C the most-significant bit (MSB), we can say the contents of the counter is CBA=000. Every time there is a negative clock transition, flip-flop A will change states. Thus at point a on the time line, A goes high, at point b it goes back low, at c it goes high, and so on. A acts as the clock for B, each time the waveform at A goes low, flip-flop will toggle. Thus at point b on the time line, B goes high; it then goes low at point d and toggles back high again at point f. Since B acts as the clock for C, each time the waveform at B goes low, flip-flop C will toggle. Thus C goes high at point d on the time line and goes back low again at point h. Three-bit Binary Ripple Counter

+Vcc

clock

WAVEFORMS:

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A B c

J A

K A

J B

K B

J C

K C

TRUTH TABLE:

Clock Transitions

C B A

0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 10 0 0 0

SYNCHRONOUS COUNTER:Due to overall propagation delay time, Ripple Counters (asynchronous counters)

are too slow for some applications. To overcome, this we use synchronous counters. A synchronous counter is constructed using the +ve edge triggered flip-flops. Here, clock pulses drive all flip-flops in parallel because of the simultaneous clocking.

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Clock

A

B

C

The least significant flip-flops has its J and K inputs tied to a high voltage; therefore it responds to each positive clock edge. But the remaining flip-flops can respond to the positive clock edge only under certain conditions.

SYNCHRONOUS COUNTER

A shown in the figure above the Q1 flip-flop toggles on the positive clock edge only when Q0 is a 1. The Q2 flip-flop toggles only when Q1 and Q0 are 1s. And the Q3

flip-flop toggles only when Q2, Q1 and Q0 are 1s. In other words, a flip-flop toggles on the next positive clock edge if all lower bits are 1s. Here is the counting action. A low CLR resets the counter to Q = 0000. When the CLR line goes high, the counter is ready to go. The first positive clock edge sets Q0 to get Q=0001. Since Q0 is now 1, the Q1 flip-flop is conditioned to toggle on the next positive clock edge.

When the second positive clock edge arrives Q1 and Q0 simultaneously toggle and the output word becomes Q=0010. The third positive clock edge advances the count by 1: Q=0011. Because Q1 and Q0 are now 1s, the Q2, Q1 and Q0 flip-flops are conditioned to toggle on the next positive clock edge. When the fourth positive clock edge arrives Q2, Q1

and Q0 toggle simultaneously, and after one propagation delay time the output word becomes Q = 0100. The successive Q words are 0101, 0110, 0111 and so on up to 1111 (equivalent to decimal 15) . The next positive clock edge resets the counter, and the cycle repeats. The advantage of a synchronous counter is its speed.

RING COUNTER:Ring counter uses words that have only a single high bit. In the figure below

illustrates a ring counter built with D flip-flops. The Q0 output sets up the D1 input, the Q1 output sets up the D2 input and so on. Therefore a ring counter resembles a shift-left

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+VCC

register because the bits are shifted left one position per positive clock edge. But the circuit differs because the final output is fed back to the D0 input. This kind of output is called rotate left; bits are shifted left and fed back to the input.

When CLR goes low then back to high, the initial output word is Q = 0001. The first positive clock edge shifts the MSB into the LSB position, the other bits shift left one position. Therefore, the output word becomes Q=0010. The second positive clock edge causes another rotate left and the output word changes to Q=0100. After the third positive clock edge, the output word is Q=1000. The fourth positive clock edge starts the cycle over because the rotate left produces Q=0001. The stored 1 bit follows a circular path, moving left through the flip-flop until the flip-flop sends it back to the first flip-flop. This is why the circuit is called a ring counter.

RING COUNTER

CONTROLLED COUNTER : The figure below illustrates controlled counter. A low COUNT disables all flip-flops. When COUNT is high, the circuit becomes a synchronous counter each positive clock edge advances the count by 1. COUNT = 0 disabled. COUNT = 1 enabled.

COUNT

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CONTROLLED SYNCHRONOUS COUNTERMOD –3&5 COUNTER: The figure below shows a way to build a modulus-10 ( or MOD-10 counter). The circuit counts from 0000 to 1001, as before. However on the tenth clock pulse, the counter generates its own clear signal and the count jumps back to 0000. In other words, the count sequence is Q = 0000 = (0), Q = 0001 = (1), Q = 0010 = (2), Q = 0011= (3), Q = 0100 = (4) Q = 0101 = (5), Q = 0110 = (6), Q = 0111 = (7), Q = 1000 = (8), Q = 1001 = (9) Q = 0000 = (0). The modulus of a counter is the number of output states it has. Example : A 4-bit Ripple counter has a modulus of 16 distinct states from 0-15. By changing the design, we can produce a counter with any desired modulus. The mod-10 counter is otherwise known as a divide-by-10 circuit or decade counter.

MOD –3 COUNTERHigh

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MOD – 10 counter circuit 0 – 9 (10 states)

D C B A CLK0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 40 1 0 1 50 1 1 0 60 1 1 1 71 0 0 0 81 0 0 1 9

DOWN COUNTER: All the counters discussed so far have counted upward toward higher numbers. The figure below illustrates a down counter; it counts from 1111 to 0000. Each flip-flop toggles when its clock input goes from 1 to 0. This is equivalent to an uncomplemented output going from 0 to 1. For instance, the Q1 flip-flop toggles when Q0 goes from 0 to 1. A preset signal generated elsewhere is available in either uncomplemented or complemented form; PRE goes to all circuits with an active-high preset; PRE goes to all circuits with an active-low preset. Initially, the preset signal PRE goes low in the figure below, producing an output word of Q =1111(15) UP AND DOWN COUNTER:

When PRE goes high, the action starts. Q0 toggles once per clock pulse. A positive toggle means a change from 0 to 1. A negative toggle means a change from 1 to 0. The

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first clock pulse produces a negative toggle in Q0; nothing else happens: Q=1110(14). The second clock pulse produces a positive toggle in Q0, which produces a negative toggle in Q1: Q=1101(13). On the third clock pulse, Q0 toggles negatively, and Q=1100(12). On the fourth clock pulse, Q0 toggles positively, Q1 toggles positively, and Q2 toggles negatively: Q=1011(11). The circuit is counting down from 15 to 0. When it reaches 0, Q=0000. On the next clock pulse, all flip-flops toggle positively to get Q=1111 and the cycle repeats.

DECADE COUNTER-APPLICATIONS: In presettable counter, the count starts at a number greater than zero. The count begins with P3P2P1P0, a number between 0000 and 1111. To start the analysis, look at the LOAD control line. When it is low, all NAND gates have high outputs; the preset and clear inputs of all flip-flops are inactive. In this case, the circuit counts upward. The data inputs P3 to P0 have no effect because the NAND gates are disabled. When the LOAD line is high, the data inputs and their complements pass through the NAND gates and preset the counter to P3P2P1P0. As an example suppose, the preset input is P3P2P1P0=0110. Because of the two left NAND gates, the low P3 produces a high preset and a low clear for the Q3

flip-flop this clears Q3 to 0. By a similar argument, the high P2 set Q2, the high P1 sets Q1,

and the low P0 clear Q0. Therefore the counter is preset to Q=0110. When LOAD returns to low, the circuit reverts to a counter. Successive clock pulse produce Q=0111 , Q=1000Q=1001 up to a maximum count of Q =1111. The next clock pulse resets the counter to Q=0000. When LOAD is low, the circuit counts when LOAD is high, the counter presets to P3P2P1P0.

DECADE COUNTER

P3 P2 P1 P0

load

high

CLK

33

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