Back-End Firmware Status

12 Oct 2012

Lynn Wood, Ryan Conrad, Craig Bookwalter

1

Back-End Structure

2

FINESSE FPGA Requirements

SCROD interface

Support 2 fiber channels

Receive data from fiber

Pass data to FIFO

Support new data interface (data from SCROD)

Support new data interface (commands to SCROD)

DSP interface

Identify data packets to be delivered to DSP

Pass and receive data to/from DSP

Support simple handshaking (“buffers full”)

Other

Read/write registers from PC1

3

FINESSE DSP Requirements

FPGA Interface

Receive data from FPGA*

Store data in SDRAM ring buffer*

Pass results back to FPGA

Algorithms

Calculate Q for packet

Calculate T for packet

* Assumes that existing DSP code is acceptable

4

PC1 (COPPER CPU) Requirements

Interface with FINESSE

Monitor FIFO status

Read data from FIFOs

Send SCROD commands to FINESSE

Write support library for acquisition code

Data handling

Send FIFO data to PC2*

Read CAMAC data via USB**

Other

Send trigger clear to NIM bin**

* Assumes that NFS has acceptable data transfer rates

** Assumes that soon-to-arrive USB PMC card works

5

PC2 (COPPER Server) Requirements

Interface with PC1*

Boot COPPER CPU

Receive data from PC1

Save data to disk

* Assumes that NFS has acceptable data transfer rates

6

Challenges #1 and #2

USB support on PC1

Required for CAMAC readout and NIM trigger clear on PC1

Assumes that PMC USB card will provide support for PC1

Backup plan:

Send commands to PC2 to perform these operations

Data transfer from PC1 to PC2

Current plan assumes that (already-present) NFS is sufficient

Backup plan:

#1: hang USB drive on PC1 (but that depends on USB support)

#2: simple client/server to stream data to PC2 (meshes with backup for USB)

PMC card arrives next week, will test immediately

Simple client/server architecture design already being implemented

7

Challenge #3

DSP implementation

Assumes previous code for ring buffer will work (it should)

Not required for CRT day 1 (but required for CRT)

If necessary, can bypass DSP and dump out raw data

FPGA interface is under development now

Active DSP development starts next week (dev kit arrival)

Preliminary waveform analysis code also exists

8

Resources at PNNL

Personnel

Lynn Wood (scientist) – firmware, software

Ryan Conrad (engineer) – firmware

Eric Choi, Hardeep Mehta (engineers) – firmware

Craig Bookwalter (postdoc) – software

Equipment

Two SCRODs

COPPER-II crate with CPU (PC1)

One DSP_FIN FINESSE board

COPPER server (PC2)

9

Backup slides

10

USB

CRT Electronics

11

S

S

S

S

S

iTO

P b

ar

Sci

Fi

DSP_FIN A

DSP_FIN B

DSP_FIN C

COPPER

CPU

(PC1)

CAMAC crate

Ethernet

TOF NIM

FTSW

Fiber

PCI

TTL

COPPER

server

(PC2)

Ethernet

USB

USB

CRT Electronics Currently at PNNL

12

S

S

S

S

iTO

P b

ar

Sci

Fi

DSP_FIN A

DSP_FIN B

DSP_FIN C

COPPER

CPU

(PC1)

COPPER

server

(PC2)

Fiber

PCI

Ethernet

S

CAMAC crate

TOF NIM

FTSW USB

TTL

CRT Assumptions, Data Flow

When an event occurs:

Trigger will occur in NIM logic, fed to FTSW

FTSW will send trigger to SCRODs

SCRODs will send data to FINESSE

FINESSE will process data through DSP and put into COPPER FIFO

PC1 (COPPER) will read data from FIFO and send to PC2 (COPPER server)

PC1 (or PC2) will also read CAMAC data via USB and send to PC2

PC1 will send TTL signal to NIM bin to clear trigger

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