backplane design and optimization using 28nm fpgas

© 2011 Altera Corporation - Public

Backplane Design and Optimization Using 28nm FPGAs Technology Roadshow 2011


Agenda

Backplane Challenges 28-nm Transceiver Architecture & Signal Integrity

Features Simulation Tools, Models and Flows 10GBASE-KR Backplane Design Example Backplane Solutions Summary

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10+ Gbps Backplane Design Challenges

3


Backplane Applications Enterprise switching

- Line card and switch fabric- Core switch- Aggregation- Cross-bar applications- Shared memory architecture

Access boxes- DSLAM, PON- T1, E1, cable

Proprietary backplanes/midplanes Time-slot interchange (TSI) Transport

- Next-generation Ethernet switching- Types of transport

ROADMOTN WDMMSPP

Broadcast switching- Serial digital interface (SDI) aggregation

4


10GBASE-KR Backplane Electrical

TX- Eye mask

Channel- Channel description- Insertion loss- Return loss

RX- Jitter Tolerance- Return loss

System- BER =< 1E-12

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28-nm Transceiver Architecture & Signal Integrity Features

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Stratix V Transceiver Block Architecture Up to 66 full-duplex transceivers

at 14.1 Gbps Scalability and flexibility with

continuous bank of transceivers with complete PMA and PCS per channel

Multiple transmitter (TX) PLL sources- More LC oscillators- Programmable LC tuning range- Multipurpose fractional PLLs (fPLLs) for

additional TX clock source Analog PLL-based CDR per

receive channel Advanced TX and receiver (RX)

equalization for 14.1-Gbps backplane support- Including 10GBASE-KR

Optimized PCS / Hard IP for multiple protocol support

Additional 28G transceivers

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.

.

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Transceiver PMA

Transceiver PMA

Transceiver PMA

Transceiver PMA

Transceiver PMA

Transceiver PMA

Transceiver PMA

Transceiver PMA

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Frac

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LC T

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Transceiver PMA

Transceiver PMA


Dedicated Circuitry for Advanced Signal Conditioning LC PLL for sub-ps transmit jitter Analog-PLL CDR for improved jitter tolerance 4-tap pre-emphasis and linear equalization for 14.1-Gbps backplane applications Advanced signal conditioning including 5-tap DFE and ADCE

- Mitigate backplane losses and crosstalk Targeted 10GBASE-KR and CEI-11G electricals

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Backplane Channel:Including 10GBASE-KR

Pre-Emphasis EQ CDR

Analog CDRLinearEqualizer

DFE

+

-Rx

ADCE

TX RX

LC TX PLL

© 2011 Altera Corporation - Public9

Arria V FPGAs Offer Up to 36 Full-Duplex Transceiver Channels with PCS and PMA

Scalability and flexibility through a continuous bank of transceivers

Complete physical medium attachment (PMA)+ physical coding sublayer (PCS) per channel

Unused channels can be utilized as clock multiplier unit (CMU) PLLs

Flexible transmit clock sources enable up to 24 independent data rates in a single device

Transmit Clock Source Maximum Number

Data Range (Gbps)

CMU PLL 12 0.6 – 6.375

fPLL 12 0.6 – 3.75

CMU PLL 6 0.6 – 10.3125

.

.

.

.

Clo

ck N

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orks

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Transceiver PMA

Transceiver PMA

Transceiver PMA

Transceiver PMA

Transceiver PMA

Transceiver PMA

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Arria V Transceiver Architecture

© 2011 Altera Corporation - Public10

Altera 28nm Transceiver SummaryTransceiver SI Feature Arria V Stratix V

Transmit Equalization (pre-emphasis) Main tap Main tap, 2 post tap, 1 pre-tap

Receive Equalization(Continuous Time Linear Equalization)

1 stage (4 dB)around 6.25 Gbps

4 stage (20dB)Programmable bandwidth up to 12.5 Gbps

Adaptive Dispersion Compensation Engine (ADCE) N/A

Up to 12.5 Gbps

Decision Feedback Equalization (DFE) N/A 5-tap with auto adaption

Backplane Support Up to 30” at 6.375 Gbps Up to 40” at 14.1 Gbps

Optical Module SupportSFP+

Short Reach (SR) Long Reach (LR) requires external EDC chip

Full compliance (SR, LR and LRM) for SFP+

EyeQ N/AVertical & horizontal eye (12.5 Gbps)Serial bit checker for unknown data pattern

On-Die InstrumentationJitter Injection / Stress

N/A Jitter modulation of transmitter & receiver


Simulation Tools, Models and Flows

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Transceiver Simulation Models Altera’s suite of transceiver

design tools - Evaluate performance in custom

application- Run “What if” simulations for

early analysis- Create design constraints in

layout and design- Run in-system verification for

board bring-up and live debug

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HSPICE full circuit models IBIS-AMI behavioral models

- Fast simulation- Analog and algorithmic description

of all major transceiver components- Analysis of millions of bits


PELE – Pre-emphasis/Equal Link Estimator

Optimize the equalization coefficients for the transceiver Early estimate of link performance Inputs: Channel / settings

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Backplane

TXmodel

RXmodel

Customer provided S-parameters

PELE

Coefficients


Simulation Model Comparison

HSPICE IBIS-AMI PELE

Accuracy High High/medium Medium

Time consumption Hours to days Minutes to hours Minutes

Corner model availability Full Full TT/NormV/85C

Flexible data inputs Yes Yes PRBS-7/10

Link to other devices Yes Yes No

EDA tool requirement Synopsys HSPICE Yes, independent NA

Simulation platform requirement

64-bit Linux, 8 GB memory

EDA-tool dependent

32-bit system, 1 GB memory

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HST Jitter and BER Estimator Custom characterization

- Quickly and accurately estimate system link reliability (BER)

- Utilize customer-specific channel (S-Parameter)

- Run statistical analysis using characterization data

Margin analysis- TX- RX- Channel

Reduction of system cost- Cost-effective alternatives for the

same system performance

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Currently Available for Stratix IV and V FPGAs


Link Simulation Flow – Early Stage

Use generic S-parameter file - From backplane model provider, EDA

simulation tool extraction or VNA measurement

Use PELE/JBE to see if the selected device compensates channel losses using pre-emphasis or equalization, or both

Check to see if the eye opening meets the protocol requirements or device requirements

Proceed to device selection

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Device Selection(TX and RX)

Generic S-Parameters

(model provider/fab)

PELE/HST JBE

Eye MaskRequirements

Yes

No


Link Simulation Flow – Design Phase

Device selection Channel design

- Further analysis

Pre-emphasis and/or equalization settings selection

Fine tune/validate settings - HSPICE- IBIS-AMI behavioral models

Use JBE to include the statistical data

Use the transceiver toolkit to verify and debug

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Channel Design

Extract BackplaneS-Parameters

PELE

EDA Simulations(Fine-tune/Validate Settings)

Include StatisticalData (RJ)?

Eye MaskRequirements

Board Design

Use Transceiver ToolkitDebug/Verification

HST JBE

Yes

NoNo

Yes


10GBASE-KR Backplane Design Example

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PELE ConfigurationOptimization

MethodTX

Pre-emphasis RX CTLE

1 Manual Auto

2 Auto Auto

3 Auto Manual

4 Manual Manual

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Standalone mathematical tool- Requires MATLAB run-time library

Inputs - Data rate- VOD

- Backplane- TX pre-emphasis setting- RX equalization setting

AC gain (CTLE) DC gain DFE

Outputs- Deterministic eye opening at TX, RX,

and post equalization- Optimal pre-emphasis and

equalization setting

Optimization Method DFE

1 Disable

2 Auto

3 Manual

Stratix V GXPELE Tool

Auto/ManualMode

Backplane (*.s4p)

Data Rate

VOD

Pre-emphasis

Equalization

Eye Opening


PELE ConfigurationOptimization

MethodTX

Pre-emphasis RX CTLE

1 Manual Auto

2 Auto Auto

3 Auto Manual

4 Manual Manual

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Standalone mathematical tool- Requires MATLAB run-time library

Inputs- Data rate: 10.3125 Gbps- VOD : 1000 mV- Backplane:

“30inches_2connectors_backplane.s4p” - TX pre-emphasis setting: Auto- RX equalization setting

AC gain (CTLE) : Auto DC gain: 4 (0-8 dB) DFE: Auto

Outputs- Deterministic eye opening at TX, RX,

and post equalization- Optimal pre-emphasis and

equalization setting

Optimization Method DFE

1 Disable

2 Auto

3 Manual

Stratix V GXPELE Tool

Auto/ManualMode

Backplane (*.s4p)

Data Rate

VOD

Pre-emphasis

Equalization

Eye Opening


PELE Simulation (30” link @10.3125G)

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LinearEqualizer

DFE

+

-Rx

ADCETX


PELE Simulation Output

Refer to Stratix V user guide on PELE instructions PELE output results:

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0.75 UI = deterministic eye opening1- 0.75 UI = 0.25 UI = non compensated jitter

Starting point for optional simulation analysis


10GBASE KR Requirements

1. TX Jitter Characteristics- RJ < 0.15 UI, DJ < 0.15, DCD < 0.035 - Overall TJTX < 0.28 UI = 27ps @ 10.3125 Gbps

2. Channel Characteristics- Insertion loss < 25dB @ 5.15625 GHz

3. Altera RX Requirements – Post EQ- Eye width > 0.6 UI- Eye height > 100mV

4. RX Jitter Tolerance Requirements- SJ > 0.115, RJ > 0.13, DCD > 0.130

5. System Performance- BER = 1E-12

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10GBASE-KR channelTX RX EQ CDR

1 2 3 4

5


Transmitter 10GBASE-KR transmit jitter

requirements - RJ < 0.15 UI, DJ < 0.15, DCD < 0.035 - Overall TJTX < 0.28 UI = 27ps @ 10.3125

Gbps PELE Eye opening @ TX output

- TX TJ = 1- Eye opening at TX output = 1-0.92313 = 0.07687 UI < 0.185 UI (DJ + DCD)

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TX RX


Backplane Channel

Channel:- Length: 30” - Connectors: 2

Loss @ 5.15 GHz:- Approx -20dB

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10GBASE-KR Insertion loss spec: < 25dB @ 5.15625 GHz

TX RX


Receiver RX Jitter Tolerance Requirements

o SJ > 0.115, RJ > 0.13, DCD > 0.130o Altera data sheet and characterization report

Altera RX Requirements at 10.3125Gbpso Deterministic eye opening

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X1_eyeY_eye

X2_eye

Above 5 Gbps without DFE:X1_eye = 0.4 UIX2_eye = 0.6 UIY_eye = 100 mV

Above 5 Gbps with DFE:X1_eye = 0.5 UIX2_eye = 0.7 UIY_eye = 100 mV

CTLE Eye Height CTLE Eye Width DFE Eye Height DFE Eye Width

Requirement 100 mV 0.60 UI 100 mV 0.70 UI

Actual 326 mV 0.74 UI 352 mV 0.75 UI

TX RX


System Performance

PELE analysis is a deterministic simulator Jitter and BER Estimator (JBE) incorporates

random jitter components of transmitter and receiver through characterized data- Early version (EAP) of Stratix V JBE is based on Stratix IV data- Final version will incorporate actual silicon measurement

JBE will determine Bit Error Ratio performance of link

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TX RXTX


Jitter and BER Estimator Tool

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JBE Configuration Steps

1. Setup global parameters - Target BER- Data Rate (Gbps)- Test Pattern

2. Link configuration- Analysis mode

selection/eye mask setup

- Options: Full Link, TX, RX

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Step1

Step 2


JBE Configuration Steps

3. Configure TX settings

4. Configure RX settings

5. Input the non-equalized channel DJ from PELE simulation output - “1 – Eye opening”

post equalization- May add margin to

this number to account for cross-talk

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Step 3 Step 4

Step 5


Link Analysis: Full Link Mode

Full link simulation shows that the link meets the BER target of 10-15

Margin analysis

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Backplane Solutions

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10GBASE-KR Backplane PCS

Auto-negotiation Link Training Forward Error Correction

MoreThanIP offers a complete PCS solution for 10GBASE-KR applications for Stratix V

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Connectors

Major component of link reliability Evaluation of link includes

- Insertion Loss- Return Loss- Crosstalk

Advanced EDA simulationtools

Hardware analysis

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Stratix V 5-Tap Decision Feedback Equalizer

Improves signal-noise-ratio (SNR) With CTLE, addresses

pre-cursor and post-cursor ISI Mitigates the effects of crosstalk Automatically adapts to PVT conditions

35

LinearEqualizer

DFE

+

-Rx

ADCE

Z-1

Z-1

Z-1

Z-1

Z-1

C1

C2

C3

C4

C5

_From linear equalizer

To CDR


Stratix V FPGA EyeQ Eye Viewer

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View receiver signal margin with Altera’s EyeQ® eye viewer Complete vertical and horizontal reconstruction of eye opening Uninterrupted data path for live debug capability

Minimize board bring up / debug time with Dynamic reconfiguration and EyeQ

Tx RxLossy medium

Pre-Emphasis EQ CDR

EyeQ®


Summary

Link simulation flow enabled through Altera simulation tools and models

10GBASE-KR backplane system performance achieved

Altera offers complete solution for 10+ Gbps backplane analysis and design

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Stratix V FPGAs offer the optimum platform for 10Gbps+ backplane

systems

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the United States and are trademarks or registered trademarks in other countries.


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Backplane Design and Optimization Using 28-nm FPGAs

backplane design and optimization using 28nm fpgas

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