badass tutorial unit 6 adders subtractors

Upload: djpsychoscientz

Post on 18-Oct-2015

26 views

Category:

Documents


0 download

DESCRIPTION

Adders and subtractors. Great tutorial!!!

TRANSCRIPT

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    1/23

    Ms Sandhya Rani Dash

    MODULE 6: ARITHMATIC CIRCUITS AS COMBINATIONAL LOGIC

    Structure

    6.1 Introduction6.2 Objectives

    6.3 Adders6.3.1 Half adders

    6.3.2 Full Adders6.3.3 Carry LookAhead Adders

    6.3.4 BCD adder6.4 Subtractor

    6.4.1 Half subtractor6.4.2 Full Subtract or

    6.4.3 2s complement sub tractor6.5 Binary Multiplier

    6.6 Unit Summary

    6.1 INTRODUCTION

    As we know a digital system consists of two types of logic circuits, namely

    combinational and sequential. A combinational circuit consists of logic gates whose out

    puts at any time are determined directly from the combination of inputs withoutdepending upon the history of past inputs. In a sequential circuit, the output at any time

    depends on the present input values well as the past output values. The arithmetic circuit

    such as adders, subtractors, multipliers, dividers are the examples of combinational

    circuits.These arithmetic and logic circuits are mostly used in digital computes and

    calculators which contain logic gates and flip-flops that adds, subtract, multiply and

    divides by any numbers.

    In this unit different kinds of arithmetic circuits such as adders, subtractors, multipliers,

    dividers are introduced.

    7.2 OBJECTIVES

    After going through this unit you will be able to:

    i) Define arithmetic circuits

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    2/23

    ii) Describe the function of a half adders and draw half adders logic diagramsiii)Describe the function of a half adders and draw full adders logic diagrams using

    half adders

    iv)Design the circuitry required to use a full adder as a BCD adderv) Describe half and full sub tractorsvi)Develop logic circuitry and construct half and full subtractor

    6.3 Adders

    Adders are important in many types of digital system in which numerical data are

    processed. The fundamental study of digital systems is the understanding of basic adder

    operations. The most basic arithmatiic operation is the addition of two binary digits.

    There are two types of adders

    1. Half adders2. Full adders

    6.3.1 Half adder

    The arithmetic circuit which perform the addition of two binary digits, giving a sum bit

    and a carry bit is called half adder. It is the simplest combinational circuit.

    The truth table of the half adder consists of two inputs A and B an\d two out puts sum (S)

    and carry ( C ) is given below:

    Input Output

    A B S C

    0 0 0 0

    0 1 1 01 0 1 0

    1 1 0 1

    The simplified Boolean expression for the two outputs can be obtained directly from the

    truth table as,

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    3/23

    _ _

    S= AB + AB

    C= AB

    The above expressions can be implemented as follows:

    A half adder can therefore be realized by using one XOR gate and one AND gate as

    shown in the figure above.

    6.3.2 Full adder

    It is the second category of adder. It is a combinational circuit that performs the

    arithmetic sum of three input bits and generates a sum out put and an out put carry. The

    full adder is designed for multibit addition purposes. The block diagram and truth table of

    a full adder is shown below.

    Cin

    S

    A

    Cout

    B

    (Block Diagram of Full Adder)

    FULL ADDER

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    4/23

    Input Output

    A B Cin S Cout

    0 0 0 0 0

    0 0 1 1 0

    0 1 0 1 00 1 1 0 1

    1 0 0 1 0

    1 0 1 0 1

    1 1 0 0 1

    1 1 1 1 1

    The full adder shown in the above figure adds to inputs A, B, and input carry C in (carry

    from the previous lower significant portion). The variable S represents the sum of three

    input variables and Cout gives the output carry.

    Since there are three inputs, so there are eight possible input combinations and for each

    case the capital S and Coutvalues are listed in the truth table. So, the logic expression for

    S and Coutfor which the output is 1 can be written as:

    _ _ _ _ _ _

    S= ABCin+ ABCin + ABCin + ABCin

    By simplifying we will get

    S= A B Cin

    ______ __ _ ___________ _ _Cout = ABCin+ ABCin+ ABCin+ ABCin

    _ _ _ _ _ _

    = BCin( A + A) + ABCin+ ABCin_ _ _ _

    = BCin+ ABCin+ ABCin

    Now, add the ABCin term twice for further simplification we have_ _

    Cout = BCin+ ABCin+ ABCin+ ABCin + ABCin_ _

    Cout = BCin+ ACin( B + B) + AB( Cin+ Cin)

    Cout = BCin+ ACin+ AB

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    5/23

    From the above simplified expression of S and Cout, the logic diagram of the full adder

    can be constructed by using two X-OR gates, three AND gates and one OR gate as

    follows:

    6.3.3 Carry-look-ahead-adder

    In case of n-bit parallel adders, the sum and carry outputs will be delayed due to the

    propagation delays of gates through which the signal are passing. It slowers the speed of

    addition process. So a carry-look-ahead-adder is used for speeding up the addition

    process by eliminating the carry delay that by reducing the number of gates through

    which a carry signal must propagate.

    The carry-look-ahead-adder is based on the principle of looking at the lower order bits of

    the aguend and addend if a high order carry is generated. The output carry is produced

    either by carry generation or by carry propagation.

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    6/23

    To explain this operation, let us consider the truth table of full adder.

    Row Input Output

    A B Cin S Cout

    0 0 0 0 0 0 No carrygenerationi.e, Cout=0

    1 0 0 1 1 0

    2 0 1 0 1 0

    Carry

    propagationi.e, Cout= Cin

    3 0 1 1 0 1

    4 1 0 0 1 0

    5 1 0 1 0 1

    6 1 1 0 0 1Carry

    generation

    i.e, Cout=17 1 1 1 1 1

    In rows 0 & 1, the carry output is always 0 and independent of carry input, while in rows

    6 & 7, the Cout is always 1 and independent of C in. These are known as carry generate

    combinations and is represented by Gi. This function indicates as to when carry out

    would be generated by the full adder.

    In rows 2, 3, 4 & 5, the carry output is equal to carry output. i.e, C out= 1, only when Cin=

    1. These are carry propagate combinations and is represented by Pi

    From the truth table the G i can be expressed as the AND function of the two iput bits

    corresponding to 6thand 7

    throws as follows:

    _Gi= Ai BiCin + Ai BiCin

    _Gi= Ai Bi(Cin + iCin)

    Gi= Ai Bi

    Similarly, the carry propagation condition occurs when either both of the i/p bits are 1. So

    Pi can be expressed as the OR function of the inputs A and B.

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    7/23

    _ _Thus Pi= Ai Bi + Ai Bi

    = Ai BiConsider the addition of two 4 bit binary numbers A (A3A2A1A0) and B (B3B2B1B0).

    The unit carry output of the ithstage can be expressed in the form of GiPi and Ci-1which

    is the unit carry output of the (i-1)th

    stage as follows:

    Ci(Cout) = Gi+ PiCi-1

    Where Ci-1 for LSB stage is Cinwhich is assumed to be 0. In a 4-bit binary adder four

    stages of addition are required to add A0B0, A1B1, A2B2, A3B3 Therefore, for i= 0, 1, 2, 3

    The Cis are given by

    C0= G0+ P0Cin------

    Where G0= A0B0; P0= A0 B0and Cin= 0

    C1= G1+ P1C0

    = G1+ P1(G0+ P0Cin)

    = G1+ P1G0+ P1P0Cin

    Where G1= A1B1and P1= A1 B1

    C2= G2+ P2C1

    = G2+ P2 ( G1+ P1G0+P1P0Cin)

    = G2+ P2G1 + P2P1G0 + P2P1Cin-------

    Where G2= A2B2and P2= A2 B2

    C3= G3+ P3C2

    = G3+ P3( G2+ P2G1+P2P1P0Cin)

    = G3+ P3G2 + P3P2G1 + P3P2P1G0+ P3P2P1P0Cin-------

    Where G3= A3B3and P3= A3 B3

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    8/23

    The sum of A & B is given by

    S= C3S3S2S1S0

    Where Si= Ai BiCi-1 for i = 0, 1, 2, 3

    i.e. S0 = A0 B0 CinS1= A1 B1 C0

    S2= A2 B2 C1

    S3= A3 B3 C2

    Using the above equation, a 4-bit carry look ahead adder can be realized as shown in the

    figure

    From the above diagram one can easily understand that the addition of two 4-bit numbers

    can be done by a bit carry look ahead adder in a four gate propagation time. The Coutof

    each full adder stage is dependent only on the initial input carry (C in), its generate and

    propagate conditions and the generate and propagate condition of the preceding stages.

    Since each of the Giand Pi functions can be expressed in terms of inputs A and B to the

    full adders, all of the output carries are immediately available (except for gate delays) and

    there is no need to wait for a carry to ripple through all of the stage before a final result is

    achieved. Thus the carry look ahead adder speeds up the addition process.

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    9/23

    6.3.4 BCD adder

    A BCD adder is circuit that adds two BCD digits in parallel and produces a sum digit

    which is also in BCD. As we know that BCD uses four bits to represent a decimal no. as

    shown in the table.

    Legitimate BCD Numbers

    0 0 0 0

    0 0 0 1

    0 0 1 0

    0 0 1 1

    0 1 0 0

    0 1 0 1

    0 1 1 0

    0 1 1 1

    1 0 0 0

    Forbidden Numbers

    1 0 0 1

    1 0 1 0

    1 0 1 1

    1 1 0 0

    1 1 0 1

    1 1 1 0

    1 1 1 1

    1 0 0 1

    1 0 1 0

    A1lthough legitimate BCD numbers must stop at nine, there are six more counts before

    all four columns are full. These six numbers i.e. the numbers greater than 9 are called

    forbidden numbers. In BCD addition, care must be taken to compensate for these six

    forbidden states.

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    10/23

    A BCD adder circuit must include the following steps.

    i) Add two 4-bit BCD numbers using ordinary binary addition .

    ii) If the 4- bit sum is equal to or less than 9, the sum is in proper BCD form and no

    correction is needed.

    iii) If overflow occurs during an addition or if one of the forbidden states occur (if the

    sum is greater than 9) as a result of an addition , then 6 (0110) must be added to the result

    to flip through the unwanted states. In the above table shown, let us add 7 with 5. The

    result is 1100(12). To flip out of the forbidden states, count 6 more. The answer is 0010

    or 2 with a carry to the next column. When you reach 1111, the next count is 0000 and a

    carry has occurred.

    Example: Add 3 plus 5

    Solution: 0 0 1 1(3)

    + 0 1 0 1(5)

    1 0 0 0

    There is no overflow and the result is a valid BCD number. So no correction is required.

    The answer is 8.

    Example -2: Add 8 plus 5

    Solution: 1 0 0 0

    + 0 1 0 1

    __________________

    1 1 0 1

    There is no overflow but the result isnt a valid BCD number. So 6 must be added to

    compensate for the six forbidden numbers.

    1 1 0 1

    + 0 1 1 0

    __________________

    1 0 0 1 1

    The answer is 13.

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    11/23

    Example -3: Add 8 plus 9

    Solution: 1 0 0 0

    + 1 0 0 1

    __________________

    1 0 0 01

    The result is a valid BCD number but there was overflow So 6 must be added to

    compensate for the forbidden states.

    1 0 0 0 1

    + 0 1 1 0

    __________________

    1 0 1 1 1

    The answer is 17.

    To convert a binary adder into a BCD adder , logic must be provided that will produce a

    signal when 6 should be added to the result of an addition. The carry out of the binary

    adder can be monitored to see if overflow resulted.

    The BCD adder for adding two BCD coded decimal digits using two 7483 ICS is as

    shown in the figure.

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    12/23

    In the above BCD adder,

    the two BCD digits, together with the input carry, are first added in the top 4-bit binary

    adder to produce the binary sum. The bottom 4-bit binary adder is used to add the

    correction factor to the binary result of the top binary adder.

    The outputs of the top adder (Z3Z2Z1Z0and Cout) are checked to ascertain whether the

    output is greater than 9 by AND- OR gate combinations. If correction is required, then a

    0110 is added with the output of the top adder. Now the bottom adder output forms the

    BCD result (S3S2 S1 S0) with carry output.

    Note:

    1. When the Output carry is equal to zero, the correction factor equals zero.

    2. When the Output carry is equal to one, the correction factor is 0110.

    The output carry generated from the bottom binary adder is ignored, since it supplies

    information already available at the output-carry terminal.

    A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output

    carry from one stage must be connected to the input carry of the next higher-order stage.

    Self Check Exercise 1

    Q. No 1. Answer the following questions selecting most appropriate alternatives out ofthe four alternatives given in each question

    a) A half adder is characterized by

    i) two inputs and two outputs

    ii) three inputs and two outputs

    iii) two inputs and three outputs

    iv) two inputs and one outputs

    b) A full adder is characterized by

    i) two inputs and two outputs

    ii) three inputs and two outputs

    iii) two inputs and three outputs

    iv) two inputs and one outputs

    c) The outputs to a full adder A=1,

    B=1, Cin=0. The outputs are

    i) S=1, Cout=1

    ii) S=1, Cout=0

    d) A 4-bit parallel adder can add

    i) Two 4-bit binary numbers

    ii) Two 2-bit binary numbers

    iii) Four bits at a time

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    13/23

    iii) S=0, Cout=1

    iv) S=0, Cout=0

    iv) Four bits in sequence.

    e) A half adder can be constructed from

    i) two X-NOR gates only

    ii) one X-OR & one OR gate with their

    outputs connected in parallel.

    iii) one X-OR & one OR gate with their

    outputs connected in parallel

    iv) one X-OR & one AND gate.

    f) Parallel adders are

    i) combinational logic circuits

    ii) sequential logic circuits

    iii) Both of these

    iv) None of these

    g) In which of these following adder

    circuits the carry look ripple delay is

    eliminated.

    i) Half adder

    ii) Full adder

    iv) Parallel adder

    v) carry- look -ahead adder

    h) Which of the following adder

    circuits can add three or more bits at a

    time.

    i) parallel adder

    ii) carry- look -ahead adder

    iii) carry- sense -adder

    iv) full adder

    Q. No 2. Determine the sum and output carry (C) of a half adder for each set of i/p bits.a) 0 1 b) 0 0 c) 1 0 d) 1 1

    Q. No. 3. Describe the working of a half adder

    Q. No 4. What is the difference between a half adder & a full adder. Design a full adder

    circuit using only NOR gates

    Q. No. 5. Design a full adder circuit using only NAND gates.

    Q. No. 6. How does the carry -look-aheadadder speed up the addition process?

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    14/23

    6.4 Subtractors

    The subtractors are the combinational circuits that subtracts 2-bits and produces their

    differences. The subtraction process can be accomplished by taking the complement of

    the subtrahend and adding it to the minuend. By this method, the subtraction becomes

    and addition operation which requires full adders for its machine implementations. As

    there are half and full adders, there are half and full subtractors.

    6.4.1 Half subtractor

    An arithmetic circuit used for the subtraction of two bits is refe to as half subtractors. It

    has two inputs X (minuend) and Y (subtrahend). And two outputs D (difference) and B

    (borrow). The LSB of the subtrahend is subtracted from the LSB of the minund during

    the subtraction of one binary number from the other. The logic symbol and the truth table

    of a half subtractor is shown below:

    X

    D

    Y B

    (Block Diagram of Half Subtractor)

    Input Output

    X Y D B0 0 0 0

    0 1 1 1

    1 0 1 0

    1 1 0 0

    From the above truth table, the logical expressions for the difference D and borrow B areobtained as

    HALF

    SUBTRACTOR

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    15/23

    _ _

    D= XY + XY = X Y_

    B= XY

    From the above equation, a half subtractor can be realized by using an X-OR gate, a

    NOT-gate and an AND-gate as shown below:

    6.4.2 Full subtractor

    A logic circuit that perform subtraction involving 3-bits namely; minund, subtrand and

    borrow from the previous stage is known as full subtractor. Full subtractor is required for

    performing multi-bit subtraction. The liogic symbol and the truth table of a full subtractor

    is shown below.

    X

    D

    Y

    Bout

    Bin

    (Block Diagram of Full Subtractor)

    FULL

    SUBTRACTOR

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    16/23

    Input Output

    X Y Bin D Bout

    0 0 0 0 0

    0 0 1 1 1

    0 1 0 1 10 1 1 0 1

    1 0 0 1 0

    1 0 1 0 0

    1 1 0 0 0

    1 1 1 1 1

    From the above truth table the logic expression for D and Bout is given as_ _ _ _ _ _

    D= XYBin+ XYBin + XYBin+ XYBin

    Simplifying the above expression_ _ _ _ _

    D=Bin(XY + XY ) + (XY + XY) Bin_______ _

    = (X Y)Bin+ (X Y)Bin

    D= X Y Bin

    Similarly,_ _ _ _ _

    Bout = XYBin+ XYBin + XYBin+ XYBin

    The equation for Boutcan be simplified using K-map as shown in the figure

    .

    _ _Now, Bout = XY + XBin + YBin

    Using the above simplified expressions, a full subtractor can, therefore, be realized using

    X-OR gates and AOI-gates as shown below:

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    17/23

    6.4.3 2 Complement addition and subtraction using parallel adders

    2 Complement Adder/Subtractions

    Q. Design a circuit that will use a 7483 IC to add the 4-bit number B 4,B3,B2,B1 to the 4-

    bit number A4,A3,A2,A1 and to subtract B4,B3,B2,B1 from A4,A3,A2,A1 by using 2s

    complement method for subtraction.

    The 2s complement system is used to represent the negative numbers for subtraction

    both the addition and subtraction operations of signed numbers can be performed using

    only the addition operation, if we use the 2s complement form to represent negative

    numbers.

    2 Complement Addition

    To perform the 2s complement addition process, the 7483 IC, 4-bit parallel adder is used

    as the 2s complement adder circuits, which is as shown below:

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    18/23

    Now let us take an example of addition of -4 and +7.

    The -4 is represented in its 2s complement form as 1100, where the left must bit 1 is the

    sign bit; +7 is represented as 0111, with the left must bit 0 is the sign bit. These numbers

    are stored in their corresponding registers A and B. The 4-bit parallel adder produces the

    sum outputs 0011, which represents +3. The output carry C 4is 1, but discarded in the 2s

    complement method.

    2Complement Subtraction

    As we know in the 2s complement method, the subtrahend is changed to its 2s

    complement form and then added to the minund. The sum outputs of the adder circuit

    represent the difference between the minund and subtrahend.

    For subtraction of the two numbers, the subtrahend is stored in the register B and must be

    2s complemented before it is added to the minuend stored in the register A. Then the

    complemented numbers B3 B2 B1 B0 is fed to the adder along with A3 A2 A1 A0. The

    initial carry input Co= 1 instead of 0 and is added to the LSB of the adder. For forming its

    2s complement. The output S3S2S1S0represents the result of the subtraction operation.

    The sign bit of the result S3 indicates whether the result is negative or positive.

    The carry out C4 is again discarded. The arrangement q is complement subtractor as

    shown below:

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    19/23

    A 4-bit adder/subtractor circuit that can perform both addition and subtraction in 2s

    complement form is shown below:

    ____

    When the ADD/SUB level is HIGH, the circuit performs the addition of the numbers___

    stored in registers A and B. When the ADD/SUB level is LOW, the circuit subtracts the

    number in register B from the number in register A.

    The operation is described as follows:

    ___

    When ADD/SUB = 1

    1. AND gates 1, 3, 5 & 7 are enabled, allowing B0B1B2& B3 to pass to the OR-gate as 9,

    _ _ _ _

    10, 11, & 12. AND gates 2, 4, 6, & 8 are disabled, blocking B0, B1, B2& B3from

    reaching the OR-gates 9, 10, 11, & 12

    2. The levels B0to B3pass through the OR gate to the 4-bit parallel adder, to be added to

    the bits A0to A3. The sum appears at the outputs S0to S3___

    3. ADD/SUB =1 causes no carry into the adder,

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    20/23

    ___

    When ADD/SUB = 0

    1. AND gates 1, 3, 5 & 7 are disabled, blocking B0B1B2& B3 from reaching the OR-

    _ _ _ _gates 9, 10, 11, & 12 AND gates 2, 4, 6 & 8 are enabled allowing B0, B1, B2& B3 to pass

    to the OR-gates

    2. The levels B0to B3pass through the OR-gates into the 4-bit parallel adder, to be added

    to bits A0to A3. The Coos now 1. The number in register B is converted to its 2s

    complement form

    3. The difference appears at the outputs S0to S3

    Circuits like the adder/subtractor of the above figure are used in computers because they

    Provide a relatively simple means for adding and subtracting signed binary numbers.

    Self Check Exercise 2

    Answer the following questions.

    7) Design a half subtractor circuit using only NOR gates.

    8) Design a full subtractor circuit using only NOR gates.

    9) What are the advantages of complement arithmetic?

    10) Draw the logic diagram of an 8-bit BCD adder. Use the BCD adder to add 9 and 7.

    Hint:The sum from the first adder is 0000 with a 1 out on C4which generates the ADD 6

    signal and the carry to the next stage. The answer is 16

    6.5 Binary Multiplier

    The multiplication operation can be carried out by multipliers using partial product

    addition and shifting method. In a binary multiplier, instead of adding all the partial

    products at the end, they are added two at a time and their sum accumulated in a register

    called accumulator register.

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    21/23

    Now to understand the multiplication process using partial product addition & shifting

    method, consider the multiplication of two 4-bit binary numbers 1110 & 100, as an

    example.

    1 1 1 0 Multiple

    X 1 0 0 1 Multiplier

    _____________________________

    1 1 1 0 Partial Product 1

    0 0 0 0 Partial Product 2

    0 0 0 0 Partial Product 3

    1 1 1 0 Partial Product 4

    ____________________________________________

    1 1 1 1 1 1 0 Result

    From the above multiplication process, one can easily understand that if the multiplier bit

    is 1, then the multiplicand is simply copied as a partial product; if the multiplicand bit is

    0, then the partial product is 0, Whenever a partial product is obtained, it is shifted one bit

    to the left of the previous partial product. This process is continued until the entire

    multiplier bit is checked and then the partial products are added. This multiplication

    process i.e, multiplication partial product addition and shifting can be implemented usingthe block diagram as shown below

    Multiplier Register

    Multiplicand Register

    In the above diagram the four-bit multiplier is stored in register Y (Y0Y1Y2Y3); the 4-

    bit multiplicand is stored in register M (M3, M2, M1, M0), and the X register (X4, X3, X2,

    X4 X3 X2 X1 X0Y3 Y2 Y1 Y0

    4-bit Parallel Adder

    M3 M2 M1 M0

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    22/23

    X1, X0) is initially cleared to 00000. Hear to perform multiplication, the least significant

    bit of the multiplier bit (Y0) is checked. Whether it is 0 or 1. If Yo= 1, the number in the

    multiplicand register M is added with the least significant 4-bits of X register (X3, X2, X1,

    X0;X4is to store carry in addition process) and the combind x and Y register is shifted to

    the right by 1-bit without performing any addition. This process has to be repeated four

    times to perform 4-bit multiplication. Now the multiplication result (R7R6R5R4R3R2R1

    R0) will be available in X and Y registers.

    Self Check Exercise 3

    Answer the following questions.

    11) Design a parallel binary multiplier that multiplies a 4-bit number

    B= B3B2B1B0by a 3-bit no. A= A2 A1A0to form the product C=C6C5C4C3C 2C1C 0

    Hint: this can be done with 12 gates two 4-bit parallel adder. The AND gates are used to

    form the products of pairs of bits. The partial products formed by the AND gates are

    added with the parallel addition.

    6.5 Unit Summary

    In this unit, we havediscussed about different arithmetic and logic circuits, which contain

    logic gates and flip-flops that add, subtract, multiply & divide binary numbers.

    Now let us focus about some important points ;

    1. A half adder is an arithmetic circuit that adds two binary digits.

    2. A half sub tractor is an arithmetic circuit that subtracts one binary digit from another.

    3. A full adder is an arithmetic circuit that adds two binary digits and a carry, i.e.3 bits.

    4. A full sub tractor is an arithmetic circuit that subtracts one binary digit from another

    considering a borrow.

    The look- aheadcarry-adder speeds up the process by eliminating the ripple carry.

  • 5/28/2018 Badass Tutorial Unit 6 Adders Subtractors

    23/23

    Answer to Check Your progress

    Q. No 1

    a) i b) ii c) iii d) i

    e) iii f) i g) iv h) iii

    Unit End Exercise

    1. Design a 4-bit carry -look-aheadadder by using a 4-bit parallel adder.

    2. Describe the operations performed by the following arithmetic circuits.

    a) Half adder b) full adder c) Half subtractor

    d) Full subtractor e) carry- lookaheadadder

    3) What is the need of arithmetic circuits?

    4) Design a full adder circuit using only NOR gates. What relation has it to the half adder

    circuit?

    5) Design the logic diagram of a circuit for addition/subtraction.

    6) Use the BCD adder to add 9 & 3.