Balancing control of paralleled full-bridge converters in high-current gradient amplifiers for MRI applications

Misha Kumar1, Laszlo Huber1, He Huang2, Zhiyu Shen1, and Hongyuan Jin2

1Delta Electronics (Americas) Ltd., 5101 Davis Drive, Research Triangle Park, NC 27709, US 2Delta Electronics (Shanghai) Co. Ltd., 182 Minyu Road, Pudong, Shanghai, 201209, China

Abstract – To achieve a high current (>500 A) in gradient amplifiers, two full-bridge (FB) converters are paralleled such that each FB converter carries equal share of the gradient-coil current. However, achieving equal current sharing is very challenging because it requires perfect synchronization between the gate pulses of the paralleled FB converters. To achieve equal current sharing, coupled inductors with a large value of magnetizing inductance LM can be added between the paralleled FB converters. However, a large value of LM requires large volume of the coupled inductors. In this paper, to achieve equal current sharing, a combined hardware-software approach is proposed in which, coupled inductors with a small value of LM are used along with a balancing control. Detailed analysis of causes of unequal current sharing between paralleled FB converters is provided. In addition, digital control of two paralleled FB converters with the proposed balancing control is described in details. Finally, simulation and experimental results obtained without and with the proposed balancing control for two paralleled FB converters with 75-A and 400-A maximum gradient-coil currents are presented.

I. INTRODUCTION Magnetic Resonance Imaging (MRI) systems provide

highly detailed images of the soft tissues of the human body by generating short-term spatial variations in the magnetic field strength across the human body. These fields, referred to as gradient magnetic fields, are produced by the gradient coils, through which large currents are applied repeatedly in a carefully controlled pulse sequence [1]. These large currents are generated by gradient amplifiers. For high performance MRI systems, a gradient amplifier is required to supply the gradient coil with trapezoidal current pulses with a high peak value >500 A, fast slew rates up to 3A/µs, high steady precision of less than 1% and low current ripple of less than 0.1% of the peak value of the current [2].

In order to achieve fast slew rates of the gradient-coil current, a high voltage (~1000 V) is required across the gradient coil. Usually, stacked structures of full-bridge (FB) converters are used, where the FB converters are connected in series. The benefits of using stacked structures of FB converters are that each FB converter can be implemented with lower voltage-rating devices (e.g., 600/650 V), and that interleaved control of stacked FB converters can be implemented to achieve high ripple frequency and, therefore, low ripple of the gradient-coil current. The stacked FB

converters are supplied from equal or unequal dc sources [3]-[6].

To achieve high peak values of the gradient-coil current (>500 A), IGBTs have been used in the past [3]. However, the IGBTs, in comparison to the new wide-bandgap (WBG) devices, such as SiC and GaN, suffer from a high on-resistance and high switching losses. Currently, the market availability of discrete WBG devices with current ratings >500 A and voltage ratings of 600/650 V is very limited. For current ratings >500 A, only WBG power modules with a typical voltage rating of 1200 V are available, but they are not cost effective. One approach to achieve high peak value of the gradient-coil current is to parallel lower current rating discrete WBG devices (e.g., ten 50-100-A devices). However, connecting too many discrete devices in parallel increases the asymmetry in their layout, resulting in more unequal parasitic inductances in both the gate drives and power loops and, therefore, unequal current sharing. Another approach to achieve high peak value of the gradient-coil current is to parallel FB converters such that each FB converter carries equal share of the load current [7]-[8]. However, achieving equal current sharing with paralleled FB converters is very challenging because it requires perfect synchronization between the gate pulses of the paralleled FB converters [7]. The lack of equal current sharing between the paralleled FB converters can cause one FB converter to carry more current than its maximum current rating, resulting in damage of the FB switches. In [7], equal current sharing is achieved by adding coupled inductors between two paralleled FB converters. With the coupled inductors, the current sharing error is equal to the magnetizing current of the coupled inductors if the leakage inductance is negligible. It should be noted that equal current sharing can be achieved only with a very large magnetizing inductance of the coupled inductors. However, larger magnetizing inductance requires larger volume of the coupled inductors, which significantly increases the total volume of the gradient amplifier. In [8], equal current sharing is achieved by employing state-space feedback control, where each filter inductor current is controlled to follow half of the gradient coil current reference. However, the state-space feedback control, which requires sensing of four filter inductor currents and two capacitor voltages, is generally complex to design and implement.

In this paper, for equal current sharing between two paralleled FB converters, a combined hardware-software approach is proposed. In fact, in addition to employing coupled inductors between two paralleled FB converters, a

978-1-7281-4829-8/20/$31.00 ©2020 IEEE 1222

current balancing control is introduced. The circuit diagram of the gradient amplifier implemented with two-stacked, two-paralleled FB converters with coupled inductors is shown in Fig. 1 [9]. The gradient amplifier in Fig. 1 is designed for a peak gradient-coil current of 900 A. The equal dc input voltages of 400 V are selected to be able to use cost-effective 450-V energy storage capacitors. Each FB converter is designed to carry a peak current of 450 A. In a single FB converter, each switch is implemented with a parallel connection of five SCTW90N65G2V SiC (90 A/650 V) devices from ST. The switching frequency is 40 kHz. The magnetizing inductance LM of each coupled inductor in Fig. 1 is approximately 2 µH. This relatively small value of LM is selected for an acceptable volume of the coupled inductors. With this design, without the balancing control, the coupled inductors will saturate when the magnetizing current increases above 110 A. However, with the proposed balancing control, the magnetizing current of the coupled inductors will always be well below 110 A, resulting in a very good current sharing between the two paralleled FB converters.

This paper is organized as follows. First, a detailed analysis of causes of unequal current sharing between the paralleled FB converters is provided. Second, the digital control of two paralleled FB converters is described, which includes the gradient-coil current control and the balancing control. Finally, simulation and experimental results obtained without and with the balancing control for two-paralleled FB converters with 75-A and 400-A maximum gradient-coil currents are provided.

II. CAUSES OF UNEQUAL CURRENT SHARING BETWEEN PARALLELED FULL-BRIDGE CONVERTERS

The unequal current sharing between the paralleled full-bridge converters occurs when the magnetizing currents

iM11=i11-i12 and iM12=i13-i14 (see Fig. 1) are not zero, which is the result of non-zero voltages across the corresponding coupled inductors. A continuous non-zero voltage across the coupled inductors will result in continuously increasing magnetizing currents, which will eventually saturate the coupled inductors. In a practical circuit, a non-zero voltage across the coupled inductors is caused by mismatched impedances in the paths of the primary- and secondary-side currents and/or by mismatched delays of the gate drives of the switches on the primary and secondary side of the coupled inductors. The mismatch in the delays of the gate drives of the switches can be minimized by properly designing the gate drive circuits. However, it is difficult to minimize the mismatch of the impedances in the paths of the primary- and secondary-side currents, and therefore, this mismatch is the major cause of the unequal current sharing. Fig. 2 shows the circuit diagram of two-paralleled FB converters with resistances Rp1 and Rp2 that emulate the mismatch of impedances in the paths of the primary- and secondary-side currents of the coupled inductors between paralleled legs a11 and a12, and paralleled legs b11 and b12, respectively. Using Kirchhoff’s voltage law in Fig. 2, it can be obtained,

𝑣 𝑣 𝑣 𝑣 𝑖 ∙ 𝑅 (1) and

𝑣 𝑣 𝑣 𝑣 𝑖 ∙ 𝑅 . (2) Assuming that there are no mismatches in the gate drive

delays between the switching pulses, va11n = va12n, vb11n = vb12n. Then, it follows from (1) and (2),

𝑣 𝑣 𝑖 ∙ 𝑅 (3)

Lgc

R gc R C

C F

L F 2

R L 2

L F 2

R L 2

V ab

a

b

V gc

V dc

S ap11

a 11 b 11

V dca 21 b 21

a 12 b 12

a 22 b 22

V 12

V 23i 23 i 24

S an11

S bp11

S bn11 S bn12

S bp12 S ap12

S an12

S bn22

S bp22 S ap22

S an22

S ap21

S an21

S bp21

S bn21

i gc

i 14

i 12

i 13

i 11

V 13

V 22i 22 i 21

i Lf

V 11i M11 L M

V 14

L M i M12

i Lf

V 21i M21 L M

V 24i M22

L M

i Lf

V400

H180

m28

H7.2

F6.1

2

m5

H2LM

V400

H7.2 m5

Fig. 1. Circuit diagram of 900-A gradient amplifier implemented with two-stacked two-paralleled FB converters operating with equal dc input voltages of 400 V.

1223

and 𝑣 𝑣 𝑖 ∙ 𝑅 . (4) Since for the coupled inductors, v11=v12 and v13=v14, the voltages across the magnetizing inductances are obtained as 𝑣 𝐿 ∙ (5) and 𝑣 𝐿 ∙ . (6) It can be seen from (5) and (6) that magnetizing current iM11 will continuously increase with a slope proportional to i12 and magnetizing current iM12 will continuously decrease with a slope proportional to i13. Eventually, the continuously increasing/decreasing magnetizing currents iM11/iM12 will not only saturate the coupled inductors but they may also cause one FB converter to carry more current than the maximum current rating of its devices. Therefore, a balancing control must be implemented to prevent saturation of the coupled inductors and to achieve equal current sharing.

III. BALANCING CONTROL The goal of the balancing control is to make the dc value

of magnetizing currents iM11 and iM12 equal to zero. This can be achieved by controlling the average value of the voltages across the coupled inductors over a switching period Tsw to be equal to zero, i.e.,

〈𝑣 〉 〈𝑣 〉 〈𝑣 〉 〈𝑣 〉 0. (7) Then, it can be obtained from (1) and (2),

〈𝑣 〉 〈𝑣 〉 〈𝑣 〉 〈𝑖 〉 𝑅 (8) and 〈 𝑣 〉 〈 𝑣 〉 〈𝑣 〉 〈𝑖 〉 𝑅 . (9) It follows from (8) and (9) that the balancing control can be achieved by modulating leg voltages va11n, va12n and vb11n, vb12n so that their average values over a switching period satisfy (8) and (9). Voltages va11n, va12n and vb11n, vb12n are modulated by adjusting the duty-cycle of the switches in the corresponding legs.

Fig. 2. Circuit diagram of two-paralleled FB converters with resistances Rp1 and Rp2 that emulate mismatches of impedances in path of primary and secondary-side currents of two coupled inductors.

Lgc

R gc R C

C F

L F 2

R L 2

L F 2

R L 2

V ab

a

b

V gcV dc

S ap11

a 11 b 11 a 12 b 12

V 11V 12

i Lf

S an11

S bp11

S bn11 S bn12

S bp12 S ap12

S an12

i gc

V 14

i 14

i 12

i 13

i 11

V 13

L M

L M

R p1

R p2

i M11

i M12

p

n

i Lf

CURRENT REFERENCE

FEEDFORWARD

FPGA

IgcKcs

Ie v ctrKADCcs

ADCCURRENTSENSOR

FEEDBACK CONTROLLER

CONTROLLER

Igc*

Igcref* VFF*

t Tclk

Iref*

Kcsm KADCmcs

ADC

MAGNETIZING CURRENTSENSOR

BALANCING CONTROLLER

IM11*

Kcsm KADCmcsIM12*

Vbal1

Vbal2 BALANCING CONTROLLER

IM12

GENERATOR

VFDBK*

Imax*

I12

I11

IM11

I13

I14

GRADIENT-COIL CURRENT CONTROL

BALANCING CONTROL

Cpk2

Cpk

2

*

DPWM

Sap11

Sbp11

San11

Sbn11

v ctra

v ctrb

Vbal1

v ctra1

Vbal2

v ctra2

v ctrb1

Vbal1

v ctra

v ctrb2

Vbal2

v ctrb

Sap12

Sbp12

San12

Sbn12

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*- denotes digital values

Fig. 3. Block diagram of digital control of two-paralleled FB converters.

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IV. DIGITAL CONTROL OF TWO-PARALLELED FULL-BRIDGE CONVERTERS

The block diagram of the digital control of the two paralleled FB converters in Fig. 2 is shown in Fig. 3. The controller has two main parts: the gradient-coil current control and the balancing control. The gradient-coil current control is implemented with a combined feedforward and feedback control. The feedforward control is the main control, whereas, the feedback control corrects the errors due to the non-perfect models and variations of models’ parameters [10]. For the balancing control, the sensed magnetizing currents -iM11 and iM12 are the inputs of the balancing controllers whose outputs vbal1 and vbal2 are used to adjust the control levels at the output of the gradient-coil current control. The balancing control is implemented with a PI controller. It should be noted that each magnetizing current is sensed with one Hall-effect current sensor by passing the primary and secondary winding of the coupled inductors in the opposite directions through the current sensor. Therefore, only two additional current sensors are required for the balancing control of two paralleled FB converters.

To better illustrate the control of the two-paralleled FB converters, the control timing diagram is shown in Fig. 4.

The switching pulses for switches Sap11 and Sap12 are generated by comparing the triangular carrier of peak value Cpk to the level shifted control signals vctra1= Cpk/2+vctr +vbal1 and vctra2 = Cpk/2+vctr -vbal1, respectively. Similarly, the switching pulses for switches Sbp11 and Sbp12 are generated by comparing the triangular carrier to the level shifted control signals vctrb1= Cpk/2-vctr +vbal2 and vctrlb2 = Cpk/2-vctr -vbal2, respectively. It should be noted in Fig. 4 that the outputs of the balancing controllers vbal1 and vbal2 are negative. The negative values of vbal1 and vbal2 make vctra2>vctra1 and vctrb2>vctrb1. As a result, the width of switching pulse for switch Sap12 is larger than that for switch Sap11 and the width of switching pulse for switch Sbp12 is larger than that for switch Sbp11. As seen in Fig. 4, the difference in the width of switching pulses Sap12 and Sap11 results in a voltage va12a11 between the legs “a12” and “a11” such that its average value over a switching period is equal to i12Rp1 which satisfies (8) to achieve the balancing control for the coupled inductors between legs “a12” and “a11”. Similarly, the difference in the width of switching pulses Sbp12 and Sbp11 results in a voltage vb12b11 between the legs “b12” and “b11” such that its average value over a switching period is equal to i13Rp2 which satisfies (9) to achieve the balancing control for the coupled inductors between legs “b12” and “b11”.

The digital control is implemented with the Cyclone V FPGA from Altera [11].

Triangular Carrier

v a12a11 t

t

pkC

+vctr

S ap11 t

S bp12t

V bal2

T sw

V bal1

V ctrla1

V ctrla2

V bal1

S ap12t

V ctrlb2

V ctrlb1

S bp11t

V bal2

C pk2

C pk2

-v ctrC pk

2

V ctrla =

V ctrlb =

v b12b11 t

0 v dc

0 v dc

i 12 R p1

i 13 R p2

Without Balancing Control

With Balancing Control

Fig. 4. Timing diagram of control of two-paralleled FB converters.

GBC (s)î M11d̂

TB

PLANTDPWM

POWER STAGE

GiMd(s)

BALANCING CONTROLLER

CSmKADCmcsK

ADC MAGNETIZING CURRENT SENSING GAIN

pkm C

2V

GBPL (s)

Vbal1^

ctra = 0V̂

+

+ -a12a11

(s)

Fig. 5. Continuous time small-signal block diagram of balancing control loop.

0

-100

[dB]

-50

T B (s)

GB PL(s)

GB C(s)

50

100

1 10 100 1k 10kFreq [Hz]

0 [deg]

-90

T B (s)

GBPL(s)

GBC(s)

90

180

fc=4.5kHz

PM90o

fZ =265Hz

Fig. 6. Balancing controller design for Imax = 400 A, Vdc = 400 V.

1225

V. DESIGN OF BALANCING CONTROLLER The balancing control is designed in the continuous time

domain by using SimplisTM simulations. To simplify the design, the mismatch of impedances is created only between legs “a12” and “a11”, i.e.,Rp1 ≠ 0 , whereas, the impedances between legs “b12” and “b11” are perfectly matched, i.e., Rp2 = 0 . As a result, only one balancing controller, that controls magnetizing current iM11, is required. The continuous-time small-signal block diagram of the balancing control loop is shown in Fig. 5. This block diagram is obtained from the block diagram of the digital control of two-paralleled FB converters in Fig. 3. In Fig. 5, da12a11 is the duty cycle between legs “a12” and “a11” defined as da12a11 = va12a11/vdc, GiMd(s) is the power-stage transfer function from duty-cycle da12a11 to magnetizing current -iM11, GBC(s) is the balancing controller transfer function, and 2/Cpk is the gain of the digital pulse width modulator (DPWM). From Fig.5, the plant transfer function GBPL is obtained as

𝐺 𝑠 ∙ 𝐺 𝑠 ∙ 𝐾 ∙ 𝐾 . (10) Bode plots of transfer functions GBPL(s) and GBC(s), as well

as the loop-gain transfer function

𝑇 𝑠 𝐺 𝑠 ∙ 𝐺 𝑠 , (11) obtained with Simplis simulation at maximum gradient-coil current Imax= 400 A, input voltage Vdc= 400 V, and Kcsm=8ꞏ103, KADCmcs=32767/4.096, Cpk=626 are presented in Fig. 6. The balancing controller is implemented with PI compensator, i.e.,

𝐺 𝑠 𝐾 , (12) where, KI = 2fzKP and fz is the zero of the PI compensator. The balancing-loop bandwidth fc = 4.5 kHz and phase margin PM ≈ 90O. The gain of the compensator at frequency fc is

|𝐺 𝑓 | | | 1.465 ∙ 10 56.68dB. (13) From (12) and (13), proportional gain KP is obtained as

𝐾 | | 1.462 ∙ 10 , (14)

whereas, integral gain KI=2fzKP = 2.44, where fz = 265 Hz

It should be noted that the balancing-loop bandwidth fc = 4.5 kHz is very close to the 8-kHz bandwidth of the gradient-coil current control loop, which is obtained following the design procedure from [10]. However, the balancing-loop bandwidth should be well below the gradient-coil current control loop bandwidth (e.g., less than 1/8) to prevent an interaction between the two loops. In fact, the balancing controller is redesigned for 500-Hz balancing-loop bandwidth and key simulation waveforms corresponding to those in Fig. 7(b) are shown in Fig. 8. It can be seen in Fig. 8 that during a trapezoidal gradient current pulse, iM11 increases to ~45 A, which is significantly larger than ~8 A obtained with the 4.5-kHz balancing-loop bandwidth. Therefore, finally, the 4.5-kHz balancing-loop bandwidth is selected for proper current sharing between the two paralleled FB converters.

It should also be noted that the 8-kHz gradient-coil current feedback-loop bandwidth is designed for two-paralleled full-bridge converters. However, when two or multiple two-paralleled FB converters are connected in series, as shown in Fig. 1, with interleaved control of the series-connected converters, the feedback-loop bandwidth can be increased above 8 kHz. In fact, with interleaved control, the apparent switching frequency at the input of the output LC filter is increased and, therefore, the feedback control bandwidth can also be increased. Furthermore, with interleaved control, the ripple frequency of the gradient-coil current is increased and, therefore, the output LC filter can be redesigned to have a higher corner frequency, and therefore, the feedback loop bandwidth can be increased. As a result, the feedback loop will be well separated from the balancing loop.

For the implementation of the balancing control in the discrete-time domain, average current control is used, where the average values of magnetizing currents iM11 and iM12 are controlled to become zero. Fig. 9 shows the timing diagram of the discrete-time implementation of the balancing control. For simplicity, only the coupled inductors between legs “a12” and “a11” are considered. As can be seen in Fig. 9, the magnetizing current iM11 is sampled twice in a switching period Tsw at instants where its value is equal to its average value over a switching period. These instants coincide with instants when the triangular carrier is equal to zero or to its peak value Cpk. Control levels Vctra1, Vctra2 are also updated at the same instants. Consequently, the digital delay TBCDLY, which decreases the phase margin of the balancing control loop, is equal to 3Tsw/4, as shown in Fig. 9. It should be noted that TBCDLY includes two delays: transport delay (from instant magnetizing current is sampled to instant control levels Vctra1 and Vctra2 are updated) TBCDLY_Trans = Tsw/2 and PWM delay TBCDLY_PWM = Tsw/4 for a triangular carrier [12]. Transport delay TBCDLY_Trans mainly consists of the ADC conversion time and the FPGA calculation time.

With digital delay TBCDLY = 3Tsw/4, phase margin PM will be ~ 60o.

The timing diagram of balancing control for the coupled inductors between legs “b12” and “b11” can be obtained

Triangular Carrier

t

t

T sw

V bal1V ctrla1

V ctrla2V bal1

v a12a11 t

t i 12 R p1

2

i 12R p12

-v dc

v dc0

T sw

t

Sampling instants for magnetizing currents

t

Update instants for Vctra1 and Vctra2

T BCDLYT BCDLY_PWM

T BCS

C pk2

pkC +vctr

C pk2

i M11

T BCDLY_Trans

v 11i 12R p1

2 -v a12a11

=

Fig. 9. Timing diagram of discrete-time domain implementation of balancing control.

0200400

-5000

500

-200-100

0

0 0.0005 0.001 0.0015 0.002 0.0025-40-20

0

037.5

75

-200

0

200

-40-20

0

0 0.0005 0.001 0.0015 0.002 0.0025-10

-505

-iM11

iM12

igcigcref

vgc

29A

7A

165A

40A

Fig. 10. Key simulation waveforms of two FB converters, in digital domain, without balancing control at a) Imax= 75 A, Vdc= 150 V and b) Imax= 400 A and Vdc= 400 V.

(a) (b)time [s] time [s]

1227

similarly as in Fig. 9. The sampling instants of magnetizing current iM12 will be exactly the same as those for magnetizing current iM11.

Finally, to obtain the transfer function of the balancing controller in the discrete-time domain, translation from s-domain to z-domain is performed by using bi-linear (Tustin’s) approximation

𝑠 , (15) where balancing-loop sampling period TBCS = Tsw/2 = 12.5 µs. Applying (15) to the s-domain PI current compensator in (12), the PI compensator transfer function in the z-domain is obtained as

𝐺 𝑧 𝐾 𝐾 , (16) where KPZ = KP and KIZ = KITBCS/2.

VI. SIMULATION AND EXPERIMENTAL RESULTS To have a good agreement between simulation and

experimental results, simulations are performed in the discrete-time domain with fixed-point calculations (digital domain) by using Simulink/MATLAB.

Key simulation waveforms of the two paralleled FB converters in digital domain without balancing control at maximum gradient-coil current Imax = 75 A and Vdc = 150 V are shown in Fig. 10(a). The corresponding experimental waveforms are presented in Fig. 11. As shown in Fig. 10(a), during a trapezoidal gradient current pulse, magnetizing current iM11 increases to ~29 A, whereas, magnetizing current iM12 increases to only ~7 A. It should be noted that resistances Rp1 and Rp2 in Fig. 2, which cause unequal current sharing, are selected as Rp1 = 5 m and Rp2= 1 m so that the increase of iM11 and iM12 in the simulation model agrees as close as possible with the experimental results. It should also be noted that in order to show the current waveforms with a better resolution, the sensed and sampled currents in the FPGA are shown by using Digital to Analog Converters (DACs).

Key simulation waveforms of the two paralleled FB converters in digital domain without balancing control at maximum gradient-coil current Imax = 400 A and Vdc = 400 V are shown in Fig. 10(b). As can be seen in Fig. 10(b), during a trapezoidal gradient current pulse, iM11 increases to ~165 A, whereas, iM12 increases to only ~40 A. Since, iM11 increases more than the saturation limit of 110 A, without the balancing control it was not possible to perform corresponding experimental measurements.

Key simulation waveforms of the two paralleled FB converters in digital domain with the proposed balancing control at maximum gradient-coil current Imax = 75 A and Vdc = 150 V are shown in Fig. 12(a) and at Imax = 400 A and Vdc = 400 V are shown in Fig. 12(b). The corresponding experimental waveforms are presented in Figs. 13 and 14, respectively. It can be seen in Figs. 12(a) and 13 that the maximum values of iM11 and iM12 obtained by simulations and experiments are in close agreement and are significantly reduced compared to that without the balancing control in Figs. 10(a) and 11. Similarly, it can be seen in Figs. 12(b) and 14 that the maximum values of iM11 and iM12 obtained by

Fig. 11. Experimental waveforms of two FB converters without balancing control at Imax= 75 A and Vdc= 150 V.

0200400

-500

0

500

-20-10

010

0 0.0005 0.001 0.0015 0.002 0.0025-20-10

010

037.5

75

-200

0

200

-4-202

0 0.0005 0.001 0.0015 0.002 0.0025-4-202

igcigcref

vgc

-iM11

iM12

16A

12A

~4A

~3A

Fig. 12. Key simulation waveforms of two FB converters, in digital domain, with balancing control at a) Imax= 75 A, Vdc= 150 V and b) Imax= 400 A and Vdc= 400 V.

(a) (b)time [s] time [s]

1228

simulations and experiments are in close agreement and are significantly reduced compared to that without the balancing control in Fig. 10(b). As shown in Fig. 14, at Imax = 400 A, Vdc = 400 V, the maximum value of the measured magnetizing current iM11 is approximately 18A, which is the worst case, resulting in a maximum current sharing error of only 4.5%.

VII. CONCLUSION To achieve a high current (>500 A) in gradient-amplifiers,

two FB converters are paralleled such that each FB converter carries equal share of the gradient-coil current. In this paper, to achieve equal current sharing, a combined hardware-software approach is proposed, where, a coupled inductor with a small value of the magnetizing inductance is used along with a balancing control. Simulation and experimental results obtained without and with the proposed balancing control for two-paralleled FB converters with 75-A and 400-A maximum gradient-coil currents are provided. With the proposed balancing control, at Imax = 400 A and Vdc = 400 V, the maximum current sharing error is reduced to only 4.5%, which is considered as a very good current sharing between two paralleled FB converters.

REFERENCES [1] D. W. McRobbie, E. A. Moore, M. J. Graves, and M. R. Prince, MRI From Picture to Proton, 2nd ed., Cambridge University Press, 2006. [2] S. Li, B. Cao, D. Bi, and X. Jiang, “Stacked high/low voltage level h-bridge circuit for gradient amplifier of MRI system,” Int. Conf. on Electrical Mach. and Syst.,” Oct. 2008, pp. 2154-2158. [3] J. Sabate, L. Garces, P. Szczesny, Q. Li, and W. F. Wirth, “High-bandwidth high-power gradient driver for magnetic resonance imaging with digital control,” Proc. IEEE Appl. Power Electron. Conf. (APEC), Mar. 2005, pp. 1087-1091.

[4] R. Lai, J. Sabate, S. Chi, and W. Skeffington, “High performance gradient driver for magnetic resonance imaging system,” Proc. IEEE Energy Convers. Cong. and Expo., Sep. 2011, pp. 3511-3513. [5] J.A. Sabate, R.S. Zhang, L.J. Garces, P.M. Szczesny, Q. Li, and W. F. Wirth, ” High fidelity, high power switched amplifier,” US Patent 7,116,166, Oct. 2006. [6] R. Lai, L.J. Garces, J.A. Sabate, J.M.R. Davila, S. Chi, and W.M. Skeffington, ” Gradient amplifier system,” US Patent 8,502,539, Aug. 2013. [7] J. Sabate, Q. Li, and W.F. Wirth, “Parallel operation of switching amplifiers driving magnetic resonance imaging gradient coils,” Int’l Power Electron. and Motion Control Conf. (IPEMC), Aug. 2004, pp. 1563-1567. [8] S. Watanabe, P. Boyagoda, H. Iwamoto, M. Nakaoka, and H. Takano, “Power conversion PWM amplifier with two paralleled four quadrant chopper for MRI gradient coil magnetic field current tracking implementation,” Rec. IEEE Power Electron. Special. Conf. (PESC), Jul. 1999, pp. 909-913. [9] H. Huang, M. Kumar, L. Huber, J. Xue, and D. Jiao, ”Gradient amplifier driver stage circuit, gradient amplifier system and control method thereof,” US Patent Application Publication US 20190212403, July 2019. [10] M. Kumar, L. Huber, and M.M. Jovanovic, “Verification of control design and implementation for power supplies by FPGA-in-the-loop simulation,” Proc. IEEE Appl. Power Electron. Conf. (APEC), Mar. 2017, pp. 3114-3121. [11] Altera, Cyclone V Device Handbook, Volume 1: Device Interfaces and Integration, 2012. [12] D.M. Van de Sype, K. De Gusseme, A.P.M. Van den Bossche, and J.A. Melkebeek, “Small-signal Laplace-domain analysis of uniformly-sampled pulse-width modulators,” Rec. IEEE Power Electron. Spec. Conf., pp. 4292-4298, Jun. 2004.

Fig. 13. Experimental waveforms of two FB converters with balancing control at Imax= 75 A, Vdc= 150 V : a) gradient-coil current igc; b) magnetizing currents -iM11 and iM12, and voltage across gradient-coil vgc.

(a)

(b)

Fig. 14. Experimental waveforms of two FB converters with balancing control at Imax= 400 A, Vdc= 400 V : a) gradient-coil current igc and gradient-coil reference current igcref; b) voltage at input of LC filter vab, voltage across gradient-coil vgc, and magnetizing currents -iM11 and iM12.

(a)

(b)

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