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Design of an 8 Bit Barrel Shifter

Gene Vea, Perry Hung, Ricardo Rosas, Kevin Yoo

Advisor: D. ParentMay 11, 2005

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Agenda

• Abstract• Introduction

– Why– Simple Theory– Back Ground information (Lit Review)

• Summary of Results• Project (Experimental) Details• Results• Cost Analysis• Conclusions

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Abstract

• Summarize the logic, clock frequency, area, and power specs of your final design

• We designed an 8-bit barrel shifter that operated at 200 MHz

• 20mW of Power

• Area of 370x350 m2

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Introduction

• The barrel shifter is a very important part of a combinational logic block. It was incorporated the 386 processor and is also used in microcontrollers. Intel has since moved on to software implemented barrel shifters in their Pentium 4’s but AMD still uses it to this day.

• The designed circuit should shift a data word by any number of bits in a single operation. An N-bit shifter would require log2N number of levels to implement. For an 8 bit barrel shifter, it would require 3 logic levels.

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Project Summary

• Project was implemented with an array of 24 MUXs and 19 DFF MUXs arranged in three stages.

• Implemented with the new DFF MUXs designed in class

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Project Details

• Explain all the details of your project.– Schematics should be legible, and not too busy.– If you did a set of experiments describe the conditions

you did them under.– show a table with all hand calculations for your longest

path

• Show– Final schematic (not test bench)– Final layout– Final simulation

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Longest Path CalculationsLogic Gate Cg to #N #M #NS

N #NS

PWN WP WN WP WN WP Cg of

gateLevel Drive (H.C) (H.C) (S) (S) (L) (L)

1 Mux-DFF Slave Nand

17.1 1 2 1 2 1.96 1.63 3.9 3.45 1.96 1.63 5.99

1a Mux-DFF Slave Latch

5.99 2 2 2 2 3.96 6.8 3.9 6.85 3.96 6.8 18.3

1b Mux-DFF Master Nand

17.1 1 2 1 2 3 2.55 3.9 3.45 1.96 1.63 5.99

1c Mux-DFF Master Latch

5.99 2 2 2 2 3.96 6.8 3.9 6.85 3.96 6.8 18.3

2 Inveter 20 1 1 1 1 1.5 2.7 1.95 3 1.95 3 8.43

2a Mux (AOI22) 8.43 6 6 2 2 4.31 7.49 2.85 4.65 2.85 4.65 20.1

3 Inveter 40 1 1 1 1 2.86 5.14 3 6 3 6 13.6

3a MUX (AOI22) 13.6 6 6 2 2 3.46 5.99 2.25 3.9 2.25 3.9 16.1

4 Inveter 32 1 1 1 1 2.32 4.17 3 6 3 6 11.1

4a MUX (AOI22) 11.1 6 6 2 2 3.45 6.15 3.45 6.15 3.45 6.15 16.4

 5 Superbuffer 17.8 4 4 2 2 3.7 6.36 3.7 6.36 3.7 6.36 12

6 inverter 1 240 1 1 1 1 26.7 49.2 26.7 49.2 26.7 49.2  

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Schematic

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Layout

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Verification

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Simulations

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Cost Analysis

• Estimate how much time you spent on each phase of the project– verifying logic (40 hours)– verifying timing (10 hours)– Layout (many hours 100+ hours)– Post extracted timing (3 hours)

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Lessons Learned• Start early

• Using the excel sheet to calculate Wn & Wp

• Make sure to use the correct devices for layout if the same type of parts are used more than once.

• Plan device schematic carefully and attack it part by part making sure that it works with the other parts of the circuit

• Problems will always come up during LVS no matter how carefully it was wired together.

• Because a device passes DRC does not mean that it will pass LVS when placed in layout

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Summary

• Barrel shifters have the ability to shift data words in a single operation over standard shift left or shift right registers that utilize more than one clock cycle.

• Barrel shifters will continue to be used in smaller devices because it has a speed advantage over software

implemented ones.

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Acknowledgements

• Cadence Design Systems

• Synopsys

• Prof. Parent

• David Flores

• Junghoon Kang