IEEE/OSAIIAPR International Conference on Informatics, Electronics & Vision

A New Low Voltage Differential Current Conveyor Sanjay K. Kasodniya

ksanjay@sac.isro.gov.in Dipankar N agchoudhuri

dnc@daiict.ac.in Nilesh M. Desai

nmdesai@sac.isro.gov.in

Abstract- Current conveyor (a current mode circuit) is a good

choice for low voltage applications as it provides high gain­

bandwidth product. Current mode design technique offers

voltage independent, high bandwidth in analog circuits with

properties of accuracy and versatility in a wide range of

applications. In this paper we present a rail-to-rail low voltage

(±1.5 V) differential current conveyor (L VDCC) circuit in

standard CMOS technology that is suited for low

voltage operation. The proposed circuit uses a low-voltage­

current-mirror. The output range is -1.3 to +1.4 voltage which

is nearly rail-to-rail.

This proposed differential current conveyor is

suitable for low power CMOS mixed-mode designs.

1. INTRODUCTION

Current-mode circuits have begun to emerge as an important class of circuits, with properties of accuracy, good performance, and versatility in a wide range of applications. Since the second generation current conveyor (CC Il) was introduced in 1970 [1], several applications, such as amplifiers, oscillators, filters and signal-processing circuits using CC I I have been proposed in the literature [2-3]. Current mode circuits are being widely used in high frequency circuit design applications. Current conveyor (CC) has been proved to be an important part of current mode design. Current conveyors are commercially available now (AD844) and can be used in instrumentation amplifier, filters, DC-to-DC converter, RF mixers, high-frequency precision rectifiers and medical applications such as electrical impedance tomography. The conventional operational amplifiers cannot be used in the high-frequency applications due to their limited gain-bandwidth product.

Differential-difference-current-conveyor (DDCC) was introduced by Chiu [2]. Author has combined the advantages of the CC I I (second Generation Current Conveyor) and differential difference amplifier (DDA), and extended to a new building block, called DDCC. It has been shown that DDCC based circuits offer a competitive design choice to CC I I based and DDA based circuits.

A DDCC, whose symbol is in Fig. 1, is a five terminal network with terminal characteristics described by (1)

IyJ = Iy2 = Iy3 = 0 Vx =VYl-VY2 +VY3 (1)

Iz= ± Ix

z

Fig.1. Symbol of DDCC

978-1-4673-1154-0112/$31.00 ©20 12 IEEE

The plus and minus sign indicate whether the conveyor is configured as an inverting or non inverting circuit termed DDCC- or DDCC +. Here Y3 terminal can be used for biased signal processing

The CMOS DDCC circuit is shown in Fig. 2. The input trans conductance elements are realized with two differential stages, MI-M2 and M3-M4. The high gain stage is composed of a current mirror (M5 and M6) which converts the differential current to a single-ended output current (M7).

Fig.2. CMOS non inverting DDCC

I I. Low VOLTAGE CURRENT MIRROR

A current mirror is an integral part of all analog VLS I circuits. So many structures of current mirror are available like simple current mirror, Wilson current mirror, modified Wilson current mirror, Widlar current mirror, casco de

current mirror. These current mirrors have high output voltage swing [4] but input voltage swing is not high enough for low voltage applications. These current mirror uses diode connected configuration of the input transistor. And because of this, they require a minimum input voltage Yin of at least one threshold (V in :::: V th ).

�'d M1 1 1M2

(a)

�'"_'O.

. + Vshifl:

M1 M2

(b) Fig.3. (a) Conventional Current mirror (b) Corresponding Low

voltage current mirror

A conventional current mirror is shown in Fig. 3(a). Ml has been used in diode connected configuration and Yin is required to pump lin into the input port. Here, Yin depends solely on the biasing conditions of Ml, which operates in saturation mode. The transconductance of Ml ( gmJ) decides the input impedance. For this structure Yin is given by (2).

(2)

ICIEV 2012

IEEE/OSAIIAPR International Conference on Informatics, Electronics & Vision

Lower limit of Vin is restricted to V tn threshold voltage of NMOS. Where �I =/-lnCox WI ILl . A few Low Voltage Current Mirror (LVCM) topologies

have been reported in [5] and [6] which used bulk-driven MOS FETs which suffer either from low range of input current (lin <150flA) or low bandwidth ( B W < 100MHz).

L VCM using a voltage shifter [7-8] is shown in Fig. 3(b). The CMOS implementation is shown in Fig. 4.

v"

Fig.4. LVCM Structure

It uses MI and M2 just like conventional current mirror. The level-shifter M4 is operated in sub-threshold region by

selecting low bias current (lbiasl). Second level-shifter M5 provides suitable bias to M3, which is used to enhance the output impedance (Rout). Input current (lin) flowing through MI is transferred to M2.

Where V =17VT +ln

lbi�,L4 gS4 IDo4W4

In sub threshold region the drain-current is given by (5).

Vgs-Vtn

(3)

(4)

I TXT riVT I = DOyye (5)

dn L Input impedance of L VCM is given by Rin ;:::; l Igml and

output impedance Rout;:::; gm4.gm2/&!4.g2d2 . The minimum

output voltage of the LVCM is given by (6).

v =V +V out ds2(sat) ds3(sat)

Current transfer can be given as

(6)

(7)

Offset current Ioffset is the most critical factor in low voltage current mirror and sets the lower limit for lin. When Ioffset = 0, Vdsl must be zero but due to level--shifting action

of the M4, M2 has some voltage at its gate. Hence a sub­threshold current will flow in M2 when lin is zero. This current is known as offset current, and is given by (8). Here Ioffset can be tailored according to the designer's need

838

through the appropriate selection of W and L. Threshold voltage mismatch (�Vt ;:::; Vtn-Vtp) depends on particular CMOS technology. Even if the threshold voltages of PMOS and NMOS are matched Ioffset cannot be reduced to zero. Simplified L VCM structure is shown in Fig.5 for analysis purpose.

W. L I dV, I = I 2 4 DO, e'lVT offset biasj L W. I 2 4 DO,

v 55

Fig.5. Simplified L VCM

(8)

I I I. PROPOSED Low VOLTAGE DIFFERENTIAL

CURRENT CONVEYOR

L VCM needs less voltage across it to operate, one can use it to make other complex circuits work at low voltage. Here DCC is modified to a new Low Voltage Differential Current Conveyor (L VDCC) circuit for the low voltage application.

LVCM

Fig.6. Proposed LVDCC

Proposed L VDCC circuit is shown in Fig.6. Terminal behavior can be given by (9).

(9)

A simplified circuit is shown in Fig.7 using the simplified-L VCM shown in Fig.5. Ibiasl is bias current for the differential amplifier MI-M2 and M3-M4 and it is provided by M9 and MlO. Ibias2 is bias current for the LVCM. M5, M6 and Ml4 forms simplified LVCM. M7, MIl and M8, Ml2 form the class-AB gain stage.

ICIEV 2012

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

Fig.7. Simplified LVDCC

Transistor M14 is biased such that it is in sub-threshold region, around nano-ampere order of current is pushed in to it Ibias2. We have assumed that current mirrors have unity gain, and transistors are perfectly matched. However in practical realizations, several nonidealities must be present. The major factor we will consider here are finite

transconductance gm of the transistors, and transistor mismatch.

The relationship between Vyl , Vy2 , Vy3 and Vx can be obtained using small signal analysis. The transistors are replaced by equivalent circuits. To simplify discussion, the body effect has been neglected and the two differential pairs are assumed to be identical. By solving node equations, we obtain

v = g""g",cq (V -v +v ) . t

gm7gmeq + (gd12 + gd34 + gd6 )(gd7 + gdj) '1 )'2 )'3

With gmeq = 2.gmdlgm2 and gdij = 2.gdillgdj· Where &i and gml denote the drain conductance and transconductance of the transistor Mi, respectively and &1 is drain conductance of the current source. It is clear that voltage at port VI , V2 and V3 will be accurately transferred to port X only if gm7·gmeq» (gdI2+gd34 +gd6)(gd7+gdl).

Similarly terminal impedance looking into X can be derived by setting Vyl , Vy2 and Vy3 to zero, applying a test voltage V x at node X and calculating the current Ix , the result is

R = (gmy + gm4 )(gd12 + gd" + gd6)

x (10)

The terminal impedance at Z can also be derived as Rz ;::: 1/(gd8+&I).

Where

V.d gm7gmeq

VYI - vY2 + VY3 (g"'7 - g""q + gdl)( TIS - 1)

gd12 + gd34 + gd6

(11)

For high frequency operation, the major limitation is due to the stray capacitance at terminal X. The high frequency response can be expressed in terms of Vyl , Vy2 , Vy3 and V x

839

by (11). Where Cgdi and CgSl are the gate-to-drain capacitance and gate-to-source capacitance of device Mi. respectively. The pole frequency is quite low and will be the dominant frequency limiting factor of the circuit.

The input offset voltage Vos is defined as the differential input voltage required to cause the voltage across a resistor between terminal X and ground to be exactly zero. Large signal analysis is performed to solve the node equations. Then the offset voltage can be obtained as

v -(V -v +v -v )_� fd (K2-KI)_� fd (

K3-K4) "' - T2 T1 T3 T4 K K K K K K K K 1+ 2 2+ I 3+ 4 3+ 4

Where VTi and Ki are the threshold voltage and the transconductance parameter of the device Mi, respectively. The first term is due to mismatch among the threshold voltages, which is bias-current independent and is a strong function of process cleanliness and uniformity. The second term is caused by geometrical mismatch and can be reduced by increasing W IL or reducing bias current.

IV. SIMULATION RESULTS

The design of proposed low voltage differential current conveyor is verified using SP ICE simulations using 0.18J..lm technology from TSMC. The circuit has been designed for minimum power dissipation and maximum range of voltage transfer. The supply voltage is ±1.5V and Ibiasl =lOOJ..lA and Ibias2 =2 nA .

Voltage transfer characteristics is shown in Fig.S. It transfers voltage nicely from -1.3 volt to 1.4volts.

Current transfer characteristics is shown in Fig.9, which shows it gives almost unity current transfer ratio ( I/ Ix) and the transfer of current is linear from X to Z node.

1.SV;w.-----------------------------------------------._---.. ------,

_ 0'0'1 i! . > :

-1.5V .. ------------------------------,.----------------------------_ . ... -l$V -1.2SV 0'0' 1.25'11 1.SV

• '1(5) VCS)-Y1N

Fig.S. Voltage transfer curve for LVDCC

Frequency response for the output current is shown in Fig.IO, which gives bandwidth of 15MHZ.

A summary of simulation results comparing DCC ( Fig.2) and LVDCC is given below in Tablel.

The same design was also configured as current amplifier as shown in Fig.ll, with Ry =lOk and Rx = lk and seen the gain (= RylRx) is very near to the calculated one.

ICIEV 2012

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

lOOul

SOu'"

..

01 ---------... -,..-----... --.. --.,- -- --, ..... -.............. - .. .. -r .. .. -... -----.. -� 0" 20,"" .. OuA ,"OuA 'OuA lOOul

o Hhn)

around 12MHz. Which gives output swing from -1.3 to +1.4, which is nearly rail-to-rail. Proposed low voltage

circuit has been used to implement a current amplifier for gain of lO and seen that it gives good results with bandwidth of 1.2MHz.

This idea can be extended to make a fully differential current conveyor (FDCC) also .

REFERENCES

[I] A.S. Sedra and K.C. Smith, "A second generation current conveyor

and its applications," IEEE Trans. on Circuit Theory, Vol. CT-17, pp.

132--134, Feb. 1970.

[2] W. Chiu, S.l. Liu, H.W. Tsao and lJ. Chen, "CMOS differential

difference current conveyors and their applications," lEE Proc.--

Fig.9. Current transfer Curve for LVDCC Circuits Devices Syst., Vol. 143, No. 2, pp. 91--96, April 1996.

lNAi

a.t OIfFroq • IMiz Rx .1()Ok

0IaA+--_ ......... -.. _ .. .,- .... --.... . IOOlh l(I(tb

• reS) .,....-.

Fig.IO. Frequency Response for lout

TABLE I. COMPARISION BETWEEN DCC AND L VDCC

Parameters Dee Proposed L VDee Bias Current 100llA Supply ±3V Voltage Transfer ratio (V,/VY1) 0.95 Output Swing Power Dissipation Linear Range

-2.2 to 2.8V 2.48mW

83%

Fig.ll. LVDCC as current amplifier

V. CONCLUSION

100llA ±1.5V 0.95

-1.3 to 1.4 V 0.75mW

90%

As low power and hence low voltage is main design consideration now a days, a low voltage circuit for

DCC (L VDCC) has been proposed for supply voltage of ±1.5V with a good performance. It gives bandwidth of

840

[3] S.1. Liu, D.S. Wu, H.W. Tsao and J.H. Tsay, "Nonlinear circuit

applications with current conveyors," lEE Proc., Vol. 140, No. I, pp.

1--6, Feb. 1993.

[4] P.R. Gray and R.G. Meyer, Analysis and Design of Analog

Integrated Circuits. Wiley, Singapore, 1997, Ch. 4.

[5]

[6]

V.L Proddanov and M.M. Green, "CMOS current mirrors with

reduced input and output voltage requirements," Electron. Lett., Vol.

32, pp. 104--105,1996.

P. Heim and M.A. Jabri,"MOS cascode current mirror biasing

circuit operating at any current level with minimal output saturation

voltage," Electron. Lett., Vol. 31, pp. 690--691,1995.

[7] S.S. Rajput and S.SJamuar, "A high performance current mirror for

low voltage designs," Proc. APCCAS, Tianjin, China, Dec. 2000

[8] S.S. Rajput and S.S. Jamuar, "Low voltage, low power, high

performance current conveyors " Proc. ISCAS 200 I, Sydney 200 I.

[9] K.C. Smith and A.S. Sedra, "The current conveyor-a new circuit

building block," Proc. IEEE, Vol. 56, pp. 1368--1 369, Aug. 1968.

[10] H.W. Chua and K. Watanabe, "Wideband CMOS current conveyor,"

Electron. Lett., Vol. 32, No. 14, pp. 1245--1246, July 1996.

[11] O. Oliaei and J. Porte, "Compound current conveyor (CCIl+ and

CCIl-)," Electron. Lett., Vol. 33, No. 4, pp. 253--254, Feb. 1997.

[12] Th. Laopoulos, S. Siskos, M. Bafleur and Ph. Givelin, "CMOS

current conveyor," Electron. Lett., Vol. 28, No. 24, pp. 2261--2262,

Nov. 1992.

[13] A.S. Sedra, G.W. Roberts and F.Gohh, "The current conveyor:

history, progress and new results," IEE Proc., Vol. 137, pp. 78--87,

April 1990.

[14] A. Awad and A.M. Soliman, "New CMOS Realization of the CClI­

," IEEE Trans. on Circuits and Systems-H, Vol. 46, No. 4, pp. 460--

463, April 1999.

[15] Hassan O. Elwan and A.M. Soliman, "Low--Voltage Low--Power

CMOS Current Conveyors," IEEE Trans. on Circuits and Systems-I,

Vol. 44, No. 9, pp. 828--835, Sept. 1997.

[16] B. Wilson, "Recent developments in current conveyors and current

mode circuits," lEE Proc., Vol. 137, No. 2, pp. 63--77, April 1990.

Sanjay K. Kasodniya received the B.E. (Bachelor

of Engineering) degree in Electronics & Communications from M.B.M. Engineering College Jodhpur, India in 1998, and M.Tech. from liT (Indian Institute of Technology )Delhi in Integrated

ICIEV 2012

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

Electronics & Circuits in 200 I. He joined ISRO (Indian Space Research

Organisation) in 2002. He is currently working at Space Applications Centre (ISRO) Ahmedabad, in field of design of Mixed signal ASIC & FPGA based

systems for Microwave Payloads of different satellites of [SRO. He in pursuing PhD. from DAIlCT, Gandhinagar, India.

Dr. Dipanlrnr Nagchoudhuri is a Professor at DA­nCT. Previously, he was at llT Delhi for about thirty years, and a Professor there from 1982. During this

period, he held the position of Philips Chair Professor for about two years. He has also been a visiting

faculty to University of Malaya, Kuala Lumpur, a

Visiting Professor at Siemens AG, Munich, and at Instituto Nacional de Astrofisica, Optica y

Electronica, Mexico. He has authored three books: Semiconductor Devices ([989), Microelectronics Technology (1998) and Microelectronic Devices

(2001). He has published numerous papers in National and International

Conferences. He has guided about a dozen PhD theses and taught undergraduate and graduate courses in electronics. He was awarded the best teacher award in

1980-1981 by the EE Students Society. His research interests are in CMOS

technology and circuits.

Nilesh M. Desai received the B.E. (Bachelor of

Engineering) degree in Electronics and Communication Engineering (1986) and is a gold­medallist of 1986 batch from L.D.College of Engineering, Gujarat University,Ahmedabad, India.

He joined Space Applications Centre, ISRO, Ahmedabad, in 1986. He has contributed extensively

towards ISRO's various airborne and spaceborne Radar Projects. Presently, he is Group Director of Microwave Sensors Digital Electronics Group (MSDG) and Microwave Sensors Trans receiver Group

(MSTG) of SAC/ISRO, Ahmedabad.

841 ICIEV 2012