basic electrical & electronics lab department of … · 2013. 10. 6. · q2 2n3904 q1 2n3904 rl...

Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

ELECTRONICS-II 1

THIRD SEMESTER

ELECTRONICS - II

BASIC ELECTRICAL & ELECTRONICS LAB

DEPARTMENT OF ELECTRICAL ENGINEERING

Prepared By: Checked By: Approved By:

Engr. Saqib Riaz Engr. M.Nasim Khan Dr.Noman Jafri

Lecturer (Lab) Senior Lab Engineer Dean Electrical Department


ELECTRONICS-II 2

Name: ____________________________________________

Registration No: ____________________________________

Semester: _________________________________________

Batch: ____________________________________________

FEDERAL URDU UNIVERSITY OF ARTS, SCIENCE & TECHNOLOGY


ELECTRONICS-II 3

PRACTICAL LIST

S.NO. PRACTICAL NAME

01 Verification of the calculated value of a BJT amplifier

02 Implementation of OR gate using BJT’s

03 Determination of Input-offset voltage of LM-741

04 Implementation of the Buffer/Non-Inverting Amplifier using LM-741

05 Implementation of the Inverting Amplifier using LM-741

06 Implementation of the Summing Amplifier using LM-741

07 Frequency Response of Active Low Pass Filter

08 Frequency Response of Active High Pass Filter

09 Plot the Drain Characteristics of a JFET

10 Plot the Transfer Characteristics of a JFET

11 JFET Self Biased Network

12 JFET Voltage Divider Bias Network

13 Implementation of Common Source Amplifier using JFET

14 Implementation of Common Drain Amplifier using JFET

15 A-stable Operation of a 555 Timer

16 Mono-stable Operation of a 555 Timer


ELECTRONICS-II 4

C2

10uF

1kHz

V2-1m/1mV

+

Vcc

12V

C1

10uF

Q1

2N3904RL 1k

RC 3kRB 57k

Experiment # 01

VERIFICATION OF THE CALCULATED VALUES OF A BJT AMPLIFIER

OBJECTIVE:

Understand and analyze the operation of common-emitter amplifiers.

APPARATUS:

• BJT (2N3904) • AC/DC POWER SUPPLY • BREAD BOARD • CAPACITORS 10UF • RESISTORS 57K, 3K • MULTIMETER • CONNECTING WIRES

INITIAL CONDITIONS:

IC = 2mA & VCE= VCC/2

CIRCUIT DIAGRAM:

Common Emitter Amplifier

PROCEDURE:

1. Connect the circuit as shown in circuit diagram 2. Use the multimeter to find out the type of transistor and the value of beta. 3. Set the initial condition for the circuit and calculate the value of Rc and RB.


ELECTRONICS-II 5

4. Use the following relationship RC= (VCC-VCE)/IC

RB= (VCC-VBE)/IB

IC= βIB

5. Measure the Output Voltage Vo (p-p) for different values of input voltage Vin (p-p). 6. All the readings are tabulated and voltage gain in dB is calculated by using the expression

Av=20 log10 (V0/V i)

CALCULATIONS:

Table No. 01:

S. No. Red Wire (+) Black Wire (-) Voltage

1 A B

2 B A

3 A C

4 C A

5 B C

6 C B

From voltage table:

Side A is __________ Side B is _________ Side C is _________

Transistor is __________.

Table No. 02:

Calculated Values Actual Values

RB RC RB RC


ELECTRONICS-II 6

Table No. 03:

Input Signal

Output Signal

Gain

AV=(V0/V i)

Gain in dB

Av=20log10 (V0/V i)

Input Signal 01

Output Signal 01


ELECTRONICS-II 7

Input Signal 02

Output Signal 02

Input Signal 03


ELECTRONICS-II 8

Output Signal 03

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.


ELECTRONICS-II 9

+VBB2 0/5V

+VBB1 0/5V

+VCC 5V

Q22N3904

Q12N3904

RL 10k

RE2 100RE1 100

RC2 1k

RBB2

100k

RC1 1k

RBB1

100k

Experiment # 02

IMPLEMENTATION OF OR GATE USING BJT’S

OBJECTIVE:

Understand the working of digital OR gate. See how the truth table is constructed & also understand the outputs of the OR gate. APPARATUS:

• BJT (2N3904) • DC POWER SUPPLY • BREAD BOARD • LED’s (Red & Green) • RESISTORS 10K, 1K, 10K & 3.3K • MULTIMETER • CONNECTING WIRES

CIRCUIT DIAGRAM:

OR Gate using BJT’s

PROCEDURE:

1. Construct the circuit as shown above. 2. Clearly mark the inputs and outputs of the circuit 3. Apply the different possible combinations of the inputs to the circuit. 4. Construct the truth table for the inputs as well as for the outputs. 5. Verify the operation of the lab circuit.


ELECTRONICS-II 10

Truth Table for an OR gate:

Input A Input B Output Y

Table of results from the circuit:

Vin1 Vin2 Vout

Question: Draw the circuit diagram of AND gate using BJT’s? Also make truth table for it.


ELECTRONICS-II 11

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

_______________________.




ELECTRONICS-II 12

EXPERIMENT # 03

DETERMINATION OF INPUT-OFFSET VOLTAGE OF OPAMP

LM 741

OBJECTIVE:

To sketch and briefly explain an operational amplifier circuit symbol and identify all terminals. To understand the pin configurations, specifications & functioning of LM741 opamp used in the practical applications. To reduce the offset voltage zero at the output.

APPARATUS:

• OPAMP LM741 • RESISTORS 100K • DC POWER SUPPLY (+15,-15) • MULTIMETER • CONNECTING WIRES

PIN CONFIGURATION OF LM741 OPAMP:

SPECIFICATIONS:

1. Supply voltage:

µA 741A, µA 741, µA 741E ---------------- ±22V

µA 741C ---------------- ±18 V

2. Internal power dissipation

DIP package ----------------- 310 mw.

3. Differential input voltage ---------------- ±30 V.


ELECTRONICS-II 13

Vout

+V2 15V

+V1 15V

+U1

UA741

R3

100k

R2100k

R1100k

4. Operating temperature range

Military (µA 741A, µA 741) --------------- -550 to +1250 C.

Commercial (µA 741E, µA 741C) --------- 00 C to +700 C.

5. Input offset voltage ------------ 1.0 mV.

6. Input Bias current ------------ 80 nA.

7. PSSR --------------30µV/V.

8. Input resistance -------------2MΩ.

9. CMMR --------------90dB.

10. Output resistance ---------------75Ω.

11. Bandwidth --------------1.0 MHz.

12. Slew rate ---------------0.5 V/µ sec.

CIRCUIT DIAGRAM 1:

PROCEDURE:

1. Connect the circuit as shown in the figure (1). 2. Make both the inputs inverting as well as non-inverting to ground. 3. Make sure that you have powered the chip with the dual power supply. 4. Measure the DC output voltage at pin 6 using multimeter and record the result in table 1. 5. Calculate the input offset voltage using the formula and record the value in table 1.

Vin = Vout/Av

6. Replace the 100 K resistance with 220 K and repeat the above steps.


ELECTRONICS-II 14

Vout

+V

R4 10k 40%

+U2

UA748

+V2 15V

+V1 15V

R3

100k

R2100k

R1100k

R4 10k 40%

Table 1:

Resistance Vout Vin

100 K

220 K

Elimination of the OFFSET voltage:

1. Connect the circuit as shown in the figure (2). 2. To eliminate this offset voltage connects the stationary ends of 5K potentiometer between pin 1 & 5. 3. Use the pot, to zero the output of the amplifier this is how the offset voltage is eliminated. 4. In your experiment due to pot sensitivity, you may not get a full zero volt output. A 10

mV at the output will be sufficient. 5. Record the reading of voltage drop across the variable resistance that makes output zero

in the following table 2.

CIRCUIT DIAGRAM 2:

Table 2:

Vin Vr Vout


ELECTRONICS-II 15

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

_______________________.




ELECTRONICS-II 16

1kHz

V3-2/2V

+V2 15V

+V1 15V

+U1

UA741

RL 10k

EXPERIMENT # 04

IMPLEMENTATION OF NON-INVERTING/BUFFER AMPLIFIER BY USING LM741

OBJECTIVE:

Understand the op-amp as a voltage follower or buffer. Analyze the non-inverting configuration & understand the closed loop gain.

APPARATUS:

• OP-AMP IC LM741 • RESISTOR 22K & 100K • AC/DC POWER SUPPLIES • OSCILLOSCOPE • CONNECTING WIRES

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the buffer amplifier circuit as shown in the figure. 2. Connect AC input signal at the non-inverting end of the amplifier i.e +ve end. 3. Use the oscilloscope to observe the input as well as the output signal. 4. Compute the voltage gain by the following formula.

AV = VOUT/V IN = 1 + RF/RIN

5. Sketch the observed input & output waveforms.


ELECTRONICS-II 17

Calculations:

Table

Input Signal (VP-P)

Output Signal (VP-P)

Calculated Voltage Gain

AV

Measured Voltage Gain

AV

Difference

Calculation of the waveform:

input Signal

Output Signal


ELECTRONICS-II 18

1kHz

V3-2/2V

+V2 15V

+V1 15V

+U1

UA741

RL 10k

Rf

100kRin 22k

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the non-inverting amplifier circuit as shown in the above figure. 2. Connect AC input signal at the non-inverting end of the amplifier i.e +ve end. 3. Use the oscilloscope to observe the input as well as the output signal. 4. Compute the voltage gain by the following formula.

AV = VOUT/V IN = 1 + RF/RIN

5. Sketch the observed input & output waveforms. Calculations:

Table

Input Signal (VP-P)

Output Signal (VP-P)


AV


AV

Difference


ELECTRONICS-II 19

Input Signal

Output Signal

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 20

1kHz

V3-2/2V

+V2 15V

+V1 15V

+U1

UA741

Rin

22k

RL 10k

Rf

100k

Rin

22k

EXPERIMENT # 05

IMPLEMENTATION OF INVERTING AMPLIFIER BY USING LM741

OBJECTIVE:

Analyze the inverting configuration & understand the voltage gain.

APPARATUS:

• OP-AMP IC LM741 • RESISTOR 22K & 100K • AC/DC POWER SUPPLIES • OSCILLOSCOPE • CONNECTING WIRES

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the inverting amplifier circuit as shown in the figure. 2. Connect AC input signal at the inverting end of the amplifier i.e -ve end. 3. Use the oscilloscope to observe the input as well as the output signal. 4. Compute the voltage gain by the following formula.

AV = VOUT/V IN = - RF/RIN

5. Sketch the observed input & output waveform


ELECTRONICS-II 21

Calculations:

Table:

Input Signal (VP-P)/Freq.

Output Signal (VP-P)/Freq.


AV


AV

Difference

Input Signal

Output Signal


ELECTRONICS-II 22

Input Signal

Output Signal

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 23

1kHz

V4-1/1V

1kHz

V3-1/1V

+V2 15V

+V1 15V

+U1

UA741

RL 10k

Rin1

22k

Rf

50k

Rin

22k

EXPERIMENT # 06

IMPLEMENTATION OF SUMMING INVERTING AMPLIFIER BY USING LM741

OBJECTIVE:

Analyze the operation of summing amplifiers & how to achieve any specified gain

greater than unity

APPARATUS:

• OP-AMP IC LM741 • RESISTOR 10K, 22K & 100K • AC/DC POWER SUPPLIES • OSCILLOSCOPE • CONNECTING WIRES

CIRCUIT DIAGRAM:

Summing Inverting Amplifier

PROCEDURE:

1. Construct the summing inverting amplifier circuit as shown in the figure. 2. Connect at least two AC input signal at the inverting end of the amplifier i.e -ve end. 3. Use the oscilloscope to observe the input as well as the output signal. 4. Compute the voltage gain by the following formula.

AV = VOUT/V IN = - Rf/Rin1+Rf/Rin2

5. Sketch the observed input & output waveforms.


ELECTRONICS-II 24

Calculations:

Table:

Input Signal (VP-P)/Freq.

Output Signal (VP-P)/Freq.


AV


AV

Difference

Vin1

Vin2


Input Signal 1


ELECTRONICS-II 25

Input Signal 2

Output Signal

OBSERVATIONS: ______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 26

C1 .1uF

1kHz

V4-1/1V

+V2 15V

+V1 15V

+U1

UA741

Rin 22k

RL 10k

R1

10k

Rf

100k

1kHz

V4-1/1V

EXPERIMENT # 07

FREQUENCY RESPONSE OF ACTIVE LOW PASS FILTER OBJECTIVE:

Describe the gain-versus-frequency responses of the basic filters & explain the low-pass

response.

APPARATUS:


CIRCUIT DIAGRAM:

Active Low Pass Filter

PROCEDURE:

1. Construct the active low pass filter circuit as shown in the figure. 2. Connect AC input signal at the non-inverting end of the amplifier i.e +ve end. 3. Use the oscilloscope to observe the input as well as the output signal. 4. Increase the input signal frequency in steps from 1KHz to 1MHz & Observe the

corresponding output voltage of the filter and tabulate the results. 5. Compute the voltage gain by the following formula.

AV = VOUT/V IN = (AF)/√1+(f/fc)2


ELECTRONICS-II 27

Where, AF= the pass band gain of the filter (1+Rf/Rin) f = the frequency of the input signal fc = the cut-off frequency (fc=1/2πRC)

6. Plot the frequency response curve of the low pass filter with the experimental results

obtained & compare it with the expected waveform.

Table:

Input Frequency(Fin)

in Hz

V in

Input volatage in volts

Vout

Output Voltage

in volts

GAIN

Vout / Vin 20 Log (Vout / Vin) Magnitude in dB


ELECTRONICS-II 28


Output Signal Frequency vs Gain in dB

OBSERVATIONS: ______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 29

C1.1uF

10 Hz

V4-1/1V

+V2 15V

+V1 15V

+U1

UA741

Rin 22k

RL 10kR1 10k

Rf

100k

EXPERIMENT # 08

FREQUENCY RESPONSE OF ACTIVE HIGH PASS FILTER OBJECTIVE:

Explain the high-pass response & determine the critical frequency of a high-pass filter.

APPARATUS:


CIRCUIT DIAGRAM:

Active High Pass Filter

PROCEDURE:

1. Construct the active high pass filter circuit as shown in the figure. 2. Connect AC input signal at the non-inverting end of the amplifier i.e +ve end. 3. Use the oscilloscope to observe the input as well as the output signal. 4. Increase the input signal frequency in steps from 1KHz to 1MHz & Observe the

corresponding output voltage of the filter and tabulate the results. 5. Compute the voltage gain by the following formula.

AV = VOUT/V IN = AF(f/fc)/√1+(f/fc)2


ELECTRONICS-II 30

Where, AF= the pass band gain of the filter (1+Rf/Rin) f = the frequency of the input signal fc = the cut-off frequency (fc=1/2πRC)

6. Plot the frequency response curve of the low pass filter with the experimental results

obtained & compare it with the expected waveform.

Table:

Input Frequency(Fin)

in Hz

V in

Input volatage in volts

Vout

Output Voltage

in volts

GAIN

Vout / Vin 20 Log (Vout / Vin) Magnitude in dB


ELECTRONICS-II 31


Output Signal Frequency vs Gain in dB

OBSERVATIONS: ______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 32

Rs 470 ohm

+VDD10V

+VGS 0V,-2V

Rd

1k

Rg

1M

Q12N5457

EXPERIMENT # 09

PLOT THE DRAIN CHARACTERISTICS OF JFET OBJECTIVE:

Explain ohmic area, constant current area and breakdown. Also explain pinch-off voltage.

APPARATUS:

• JFET KS-192 • RESISTOR 1K & 1M • DC POWER SUPPLIES • MULTIMETER • CONNECTING WIRES

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the circuit diagram as shown above. 2. Set VGS=0V & measured ID=VRD/RD. 3. As VGS=0V, therefore the resulting drain current is IDSS with VGS=0V. 4. Slowly increase VDD to 3V & measure VDS and ID. 5. Increase VDD to 6V & measure VDS and ID. 6. Take couple of more measurements by increasing the value of VDD. 7. Plot the resulting curve between VDS & ID. 8. Repeat the same procedure with VGS = -2V.


ELECTRONICS-II 33

Table for VGS = 0V:

VDD(V)

Calculated

ID(mA)

Measured

ID(mA)

VDS(V)

03

06

09

12

15

Table for VGS = -2V:

VDD(V)

Calculated

ID(mA)

Measured

ID(mA)

VDS(V)

03

06

09

12

15


ELECTRONICS-II 34

Calculations:

VDS vs ID

OBSERVATIONS: ______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 35

Rs 470 ohm

+VDD10V

+VGS 0V,-2V

Rd

1k

Rg

1M

Q12N5457

EXPERIMENT # 10

PLOT THE TRANSFER CHARACTERISTICS OF JFET OBJECTIVE:

Analyze a JFET transfer characteristic curve & Use the equation for the transfer

characteristic to calculate ID also calculate transconductance.

APPARATUS:

• JFET KS-192 • RESISTOR 1K & 1M • DC POWER SUPPLIES • MULTIMETER • CONNECTING WIRES

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the circuit diagram as shown above. 2. Set VGS=0V & VDD = 10V at this point measure the drain current ID. 3. Slowly increase VGS to -1V & VDD = 10V measure ID. 4. Take couple of more measurements by increasing the value of VGS. 5. Measures drain current & transconductance by using following equation.

ID = IDSS (1 – VGS/VGS (off)) 2……………. (1) gm = ∆ID/∆VGS ……………. (2)


ELECTRONICS-II 36

Table for VDD = 10V:

VGS(V) Measured

ID(mA)

0

-1

-2

-3

-4

-5

Calculations:

VGS vs ID

OBSERVATIONS: ______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 37

+ VDD15VQ1

2N5457

RS220

RD1k

RG 10M

EXPERIMENT # 11

JFET SELF BIASED NETWORK OBJECTIVE:

Analyze JFET bias circuits & self-biased JFET circuit. Set the self-biased Q-point

APPARATUS:

• JFET KS-192 • RESISTOR 1K, 220Ω & 10M • DC POWER SUPPLIES • MULTIMETER • CONNECTING WIRES

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the circuit diagram as shown above. 2. Set VGS=0V & VDD = 15V at this point measure the drain current ID. 3. Slowly decrease the value of VDD = 10V measure ID. 4. Take couple of more measurements by decreasing the value of VDD. 5. Calculate VS by the following formula:

VS = IDRS

6. Calculate drain-source voltage by the following formula. VDS = VDD – ID (RD+RS)


ELECTRONICS-II 38

Table at VGS = 0V:

Drain Voltage

VDD

Drain Current

Measured

ID

Calculated Source Voltage

VS

Calculated Drain-Source

Voltage

VDS

Measured Drain-Source Voltage

VDS

15

10

5

3

Calculations:

VGS vs ID

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 39

+ VDD15VQ1

2N5457

RS2.2k

RD3.3k

R2 1M

R1 6.8M

EXPERIMENT # 12

JFET VOLTAGE DIVIDER BIASED NETWORK OBJECTIVE:

Analyze JFET bias circuits & the effect of parallel resistance on JFET circuit.

APPARATUS:

• JFET KS-192 • RESISTOR 1M, 2.2K, 3.3K & 10M • DC POWER SUPPLIES • MULTIMETER • CONNECTING WIRES

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the circuit diagram as shown above. 2. Set VGS=0V & VDD = 15V at this point measure the drain current ID. 3. Calculate VS by the following formula:

VS = IDRS

4. Calculate gate voltage VG & VGS by the following formula: VG = (R2/ (R1 + R2)) * VDD

VGS = VG - VS


ELECTRONICS-II 40

Table at VGS = 0V:

Gate-Source Voltage

VGS

Drain Voltage

VDD

Drain Current

Measured

ID

Calculated Source Voltage

VS

Calculated Gate Voltage

VDS

Calculated Gate-Source

Voltage

VGS

0 15

OBSERVATIONS: ______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 41

+ V210V

1kHz

V1-1/1V

C3 10uF

C2

1uF

C1

0.01uF

Q12N5457

RL 10k

RS 1k

RD 2.2k

R11k

EXPERIMENT # 13

COMMON SOURCE AMPLIFIER OF JFET OBJECTIVE:

Explain and analyze the operation of common-source FET amplifiers.

APPARATUS:

• JFET KS-192 • RESISTOR 1M, 2.2K, 1K & 10K • CAPACITOR 0.01uF, 1uF & 10uF • AC/DC POWER SUPPLIES • MULTIMETER • CONNECTING WIRES

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the circuit diagram as shown above. 2. Set VIN=1Vp-p & VDD = 12V. 3. Measure the Output Voltage Vo (p-p) for different values of input voltage Vin (p-p). 4. Voltage gain of the common source amplifier is given by:

AV = gm RD 5. The output signal voltage VDS at the drain is:

Vout = VDS = AVVGS


ELECTRONICS-II 42

Table :

Input Signal

Output Signal

Gain

AV=(V0/V i)

Gain in dB

Av=20log10 (V0/V i)


Input Signal 01

Output Signal 01

Output Signal 01


ELECTRONICS-II 43

Input Signal 02

Output Signal 02

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 44

+ V210V

100kHz

V1-1/1V

C3

1uF

C1

0.01uF

Q12N5457

RL 10k

RS 1k

RD 2.2k

R11k

EXPERIMENT # 14

COMMON DRAIN AMPLIFIER OF JFET OBJECTIVE:

Explain and analyze the operation of common-drain FET amplifiers.

APPARATUS:

• JFET KS-192 • RESISTOR 1M, 2.2K, 1K & 10K • CAPACITOR 0.01uF & 10uF • AC/DC POWER SUPPLIES • MULTIMETER • CONNECTING WIRES

CIRCUIT DIAGRAM:

PROCEDURE:

1. Construct the circuit diagram as shown above. 2. Set VIN=1Vp-p & VDD = 12V. 3. Measure the Output Voltage Vo (p-p) for different values of input voltage Vin (p-p). 4. Voltage gain of the common source amplifier is given by:

AV = gm RS / 1 + gm RS


ELECTRONICS-II 45

Table :

Input Signal

Output Signal

Gain

AV=(V0/V i)

Gain in dB

Av=20log10 (V0/V i)


Input Signal 01

Output Signal 01

Input Signal 01


ELECTRONICS-II 46

IntPut Signal 02

Output Signal 02

Output Signal 02

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________




ELECTRONICS-II 47

EXPERIMENT # 15

A-STABLE OPERATION OF 555 TIMER OBJECTIVE:

To investigate the operation of 555 timer in the A-Stable mode

APPARATUS:

• LM 555 • RESISTORS • CAPACITORS • DC POWER SUPLLY • DIGITAL MULTIMETER • OSCILLOSCOPE

OPERATION:

A-stable circuit produces a 'square wave’; this is a digital waveform with sharp transitions between low (0V) and high (+Vs). Note that the durations of the low and high states may be different. The circuit is called an A-stable because it is not stable in any state the output is continually changing between 'low' and 'high'.

The time period (T) of the square wave is the time for one complete cycle, but it is usually better to consider frequency (f) which is the number of cycles per second.


ELECTRONICS-II 48

T = time period in seconds (s) f = frequency in hertz (Hz) R1 = resistance in ohms (Ω)

T = 0.7 × (R1 + 2R2) × C1 and f = 1.4 (R1 + 2R2) × C1 R2 = resistance in ohms ( ) C1 = capacitance in farads (F) The time period can be split into two parts: T = Tm + Ts

Mark time: (output high): Tm = 0.7 × (R1 + R2) × C1 Space time: (output low): Ts = 0.7 × R2 × C1

Many circuits require Tm and Ts to be almost equal; this is achieved if R2 is much larger than R1. For a standard a-stable circuit Tm cannot be less than Ts, but this is not too restricting because the output can both sink and source current. For example an LED can be made to flash briefly with long gaps by connecting it (with its resistor) between +Vs and the output.

This way the LED is on during Ts, so brief flashes are achieved with R1 larger than R2, making Ts short and Tm long. Tm must be less than Ts a diode can be added to the circuit as explained under duty cycle below.

Choosing R1, R2 and C1:

R1 and R2 should be in the range 1k to 1M. It is best to choose C1 first because capacitors are available in just a few values.

Choose C1 to suit the frequency range you require (use the table as a guide). Choose R2 to give the frequency (f) you require. Assume that R1 is much smaller than

R2 (so that Tm and Ts are almost equal), then you can use:


ELECTRONICS-II 49

R2 = 0.7 f × C1

Choose R1 to be about a tenth of R2 (1k min.) unless you want the mark time Tm to be

significantly longer than the space time Ts. If you wish to use a variable resistor it is best to make it R2. If R1 is variable it must have a fixed resistor of at least 1k in series (this is not required for R2 if it is variable). A-stable operation With the output high (+Vs) the capacitor C1 is charged by current flowing through R1 and R2. The threshold and trigger inputs monitor the capacitor voltage and when it reaches 2/3Vs (threshold voltage) the output becomes low and the discharge pin is connected to 0V.

The capacitor now discharges with current flowing through R2 into the discharge pin. When the voltage falls to 1/3Vs (trigger voltage) the output becomes high again and the discharge pin is disconnected, allowing the capacitor to start charging again.

This cycle repeats continuously unless the reset input is connected to 0V which forces the output low while reset is 0V. A-stable can be used to provide the clock signal for circuits such as counters.

A low frequency A-stable (< 10Hz) can be used to flash an LED on and off, higher frequency flashes are too fast to be seen clearly. Driving a loudspeaker or piezo transducer with a low frequency of less than 20Hz will produce a series of 'clicks' (one for each low/high transition) and this can be used to make a simple metronome. An audio frequency A-stable (20Hz to 20 kHz) can be used to produce a sound from a loudspeaker or piezo transducer. The sound is suitable for buzzes and beeps. The natural (resonant) frequency of most piezo transducers is about 3 kHz and this will make them produce a particularly loud sound.

OBSERVATIONS:

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ELECTRONICS-II 50

EXPERIMENT # 16

MONOSTABLE OPERATION OF 555 TIMER OBJECTIVE:

To investigate the operation of 555 timer in the Mono-Stable mode

APPARATUS:

• LM 555 • RESISTORS • CAPACITORS • DC POWER SUPLLY • DIGITAL MULTIMETER • OSCILLOSCOPE

OPERATION:

A Mono-stable circuit produces a single output pulse when triggered. It is called a Mono-stable because it is stable in just one state: 'output low'. The 'output high' state is temporary. The duration of the pulse is called the time period (T) and this is determined by resistor R1 and capacitor C1: time period,

T = 1.1 × R1 × C1 T = time period in seconds (s) R1 = resistance in ohms (Ω) C1 = capacitance in farads (F) The maximum reliable time period is about 10 minutes. Why 1.1? The capacitor charges

to 2/3 = 67% so it is a bit longer than the time constant (R1 × C1) which is the time taken to charge to 63%.

Choose C1 first (there are relatively few values available). Choose R1 to give the time period you need. R1 should be in the range 1k to 1M, so use a

fixed resistor of at least 1k in series if R1 is variable. Beware that electrolytic capacitor values are not accurate; errors of at least 20% are common. Beware that electrolytic capacitors leak charge which substantially increases the time period if you are using a high value resistor - use the formula as only a very rough guide!

For example the Timer Project should have a maximum time period of 266s (about 4½ minutes), but many electrolytic capacitors extend this to about 10 minutes!

The timing period is triggered (started) when the trigger input (555 pin 2) is less than 1/3 Vs, this makes the output high (+Vs) and the capacitor C1 starts to charge through resistor R1. Once the time period has started further trigger pulses are ignored. The threshold input (555 pin 6) monitors the voltage across C1 and when this reaches 2/3 Vs the time period is over and the output becomes low. At the same time discharge (555 pin 7) is connected to 0V, discharging the capacitor ready for the next trigger. The reset input (555 pin 4) overrides all other inputs and the timing may be cancelled at any time by connecting reset to 0V, this instantly makes the output low and discharges the capacitor. If the reset function is not required the reset pin should be connected to +Vs.


ELECTRONICS-II 51


ELECTRONICS-II 52

Power-on reset or trigger: It may be useful to ensure that a mono-stable circuit is reset

or triggered automatically when the power supply is connected or switched on. This is achieved by using a capacitor instead of (or in addition to) a push switch as shown in the diagram. The capacitor takes a short time to charge, briefly holding the input close to 0V when the circuit is switched on. A switch may be connected in parallel with the capacitor if manual operation is also required. This arrangement is used for the trigger in the Timer Project.

Edge-triggering: If the trigger input is still less than 1/3 Vs at the end of the

time period the output will remain high until the trigger is greater than 1/3 Vs. This situation can occur if the input signal is from an on-off switch or sensor. The Mono-stable can be made edge triggered, responding only to changes of an input signal, by connecting the trigger signal through a capacitor to the trigger input. The capacitor passes sudden changes (AC) but blocks a constant (DC) signal. For further information please see the page on capacitance. The circuit is 'negative edge triggered' because it responds to a sudden fall in the input signal. The resistor between the trigger (555 pin 2) and +Vs ensures that the trigger is normally high (+Vs).

OBSERVATIONS:

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basic electrical & electronics lab department of … · 2013. 10. 6. · q2 2n3904 q1 2n3904 rl...

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