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BASICS OF VLSI (VHDL) CODING Presented by: Atchyuth Sonti

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Page 1: Basics of Vhdl

BASICS OFVLSI (VHDL) CODING

Presented by:

Atchyuth Sonti

Page 2: Basics of Vhdl

INTRODUCTION VHDL (Very High Speed IC Hardware description

Language) is one of the standard hardware description language used to design digital systems.

VHDL can be used to design the lowest level (gate level) of a digital system to the highest level (VLSI module).

Other than VHDL there are many hardware

description languages available in the market for the digital designers such as Verilog, ABEL, PALASM, CUPL, and etc but VHDL and Verilog are the most widely used HDLs.

Page 3: Basics of Vhdl

TYPES OF REPRESENTATION

There are two types of representation

1.Behavorial(Dataflow)2.Structural

Page 4: Basics of Vhdl

EXPLANATION OF TYPES

o Behavorial(Dataflow) Warning = Ignition_on AND ( Door_open OR

Seatbelt_off)

o Structural We should have the knowledge of the circuit which

drives the logic.

Page 5: Basics of Vhdl

BASIC STRUCTURE OF A PROGRAM

Page 6: Basics of Vhdl

ENTITY DECLARATION

The entity declaration defines the NAME of the entity and lists the input and output ports.

entity BUZZER is port (DOOR, IGNITION,

SBELT: in std_logic; WARNING: out std_logic); end BUZZER;

Page 7: Basics of Vhdl

ARCHITECTURE BODY The architecture body specifies how the circuit

operates and how it is implemented. As discussed earlier, an entity or circuit can be specified in a variety of ways, such as behavioral, structural (interconnected components), or a combination of the above.

architecture dataflow of BUZZER is

begin

WARNING <= (not DOOR and IGNITION) or (not SBELT and IGNITION);

end behavioral;

Page 8: Basics of Vhdl

STRUCTURAL TYPE…..

architecture structural of BUZZER is component AND2 port (in1, in2: in std_logic; out1: out std_logic); end component; component OR2 port (in1, in2: in std_logic; out1: out std_logic); end component; component NOT1 port (in1: in std_logic; out1: out std_logic); end component;

Page 9: Basics of Vhdl

signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic;

begin U0: NOT1 port map (DOOR, DOOR_NOT);

U1: NOT1 port map (SBELT, SBELT_NOT);

U2: AND2 port map (IGNITION, DOOR_NOT, B1);

U3: AND2 port map (IGNITION, SBELT_NOT, B2);

U4: OR2 port map (B1, B2, WARNING); end structural;

Page 10: Basics of Vhdl

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