bc3601 application note - holtek · 2018. 7. 20. · bc3601 application note an0481e v1.10 1 / 19...

BC3601 Application Note

AN0481E V1.10 1 / 19 July 18, 2018


D/N: AN0481E

Introduction This application note will introduce how to use the bidirectional wireless FSK/GFSK high

performance transceiver IC, the BC3601. The device operates in the sub-1GHz

license-free ISM bands (300MHz~960MHz). The device includes a fully integrated high

power programmable amplifier, a frequency synthesizer and a digital demodulation

function, etc., greatly simplifying the peripheral circuit design. The RF characteristic of the

device is compliant with ETSI/FCC standards.

The operating voltage range is from 2.0V to 3.6V. The device has up to +17dBm of

programmable transmitting power, high RX sensitivity capacity with a maximum 250Kbps

data rate, an Auto-Transmit-Receive (ATR) function, an integrated high precision low

power oscillator for Wake-on-TX (WOT) and Wake-on-RX (WOR) functions. These

features make the device suitable for low-power battery and IoT products, such as Smart

Homes, intelligent security systems, car alarms, industrial/agricultural controllers and

many other bidirectional wireless communication products.

This application note introduces the BC3601 basic functions to help new users quickly

understand the device operating principles and control methodology, allowing users to

quickly design their related application products.

Operational Principle The BC3601 is a wireless transceiver which can operate in various Sub-1GHz license-free

ISM bands. Since data cannot be transmitted or received at the same time, data transfers

are implemented using Time-Division Duplexing (TDD). Signal transmission and reception

operations require an internal high precision local oscillator (LO) which is composed of a

voltage controlled oscillator (VCO) and a fractional-N PLL.

During the data transmission period, the device modulates data using its internal digital

packet modulator after which the data is synthesized via a Gaussian Filter and an

Integral-Differential Modulator (Σ-Δ Modulator). Finally, the data is transmitted once the

internal high power amplifier (PA) activates the external antenna.


AN0481E V1.10 2 / 19 July 18, 2018

During the data reception period, the signal from the external antenna is amplified using

the internal Low-Noise Amplifier (LNA). After passing through the RX mixer, the data is

modulated to the lower intermediate frequency (IF) band. The intermediate frequency

complex band pass filter and the Received Signal Strength Indicator (RSSI) are used to

generate the data which is demodulated and output using a digital packet demodulator.

The structure details are shown in the following block diagram.

CRC FEC

Whitening/Manchester

Radio Controller

ATR LIRC

WOT/WOR

LNA ADC

AGC

AFCM

OD

EM

Packet H

andler

64-byte FIFO× 2

SP

I

PA VCO Fractional-N PLL

Sigma Delta Modulator

Gaussian Filter XOSC

XI XO

RFIN

RFOUT

SDIOSCKCSN

GIO1~GIO4

Function Structure

Enabling the BC3601 to implement the RF signal transmission and reception functions is

setup using internal control registers. Users need to setup the operating mode, the

operating frequency and the modulator/demodulator signal format and so on. The device

will setup the internal control registers using its SPI interface. Refer to the datasheet for

more details on the control methods. The diagram below shows the general design

architecture which should include an antenna, an RF matching circuit, a BC3601 and an

MCU.

GND_PAGND

BC3601

XOXI

RFIN

RFOUT

GIOn

SPI

RF Matching

V_IF/LNAV_SX

V_VCOV_DIGV_XO

V_RTC/IOV_ADC

3.3V

3.3V

MCU

BC3601 System Structure Diagram


AN0481E V1.10 3 / 19 July 18, 2018

Features Main Features:

Supports FSK/GFSK modulation/demodulation functions Operating voltage range: 2.0V~3.6V Operating frequency bands: 315/433/470/868/915MHz Programmable data rate: 2Kbps~250Kbps High RX sensitivity - 433.92MHz -121dBm at 2Kbps -114dBm at 10Kbps -112dBm at 50Kbps -108dBm at 125Kbps -105dBm at 250Kbps

High output power: 0dBm~17dBm Low current consumption TX mode at 433MHz: 31mA @ 10dBm, 54mA @ 17dBm TX mode at 868MHz: 34.5mA @ 10dBm, 45mA @ 13dBm RX mode at 433MHz: 13.5mA RX mode at 868MHz: 14mA

Integrates 64-byte TX/RX FIFO buffers - supports 4 kinds of FIFO Modes Simple FIFO Mode Block FIFO Mode Extend FIFO Mode Infinite FIFO Mode

Integrates Voltage Controlled Oscillator (VCO) and Fractional-N synthesizer with internal loop filter

Auto Frequency Compensation Supports low cost crystal: 16 or 19.2MHz Integrates 8-bit Received Signal Strength Indicator - RSSI Programmable complex band pass filter bandwidth: 125/200kHz Digital channel filter for optimum performance Programmable threshold for carrier detection Frame synchronisation recognition: FIFO mode/Direct mode Data packet handling Forward Error Correction - FEC Data Whitening Manchester Encoding CRC-16 checking

Auto-Transmit-Receive - ATR Auto-Resend Auto-Acknowledgment WOT + Auto-Resend WOR + Auto-Acknowledgment

Data packet filtering CRC filtering Address filtering

Small package type: 24-pin QFN


AN0481E V1.10 4 / 19 July 18, 2018

Functional Description Users need to setup the application required operating mode, operating frequency and

modulator/demodulator signal format before generating any wireless data transmissions.

The following description includes two parts to help users quickly understand operations

of the frequency synthesizer and the modulation mode. The BC3601 supports two major

wireless transmission modes. One is the Direct mode, here the transmitted or received

data is set directly via BC3601’s GIO1/GIO2 pin. The other is the FIFO mode where the

data is accessed through the internal FIFO registers.

Transceiver Frequency

The RF transceiver frequency is generated by the fractional-N delta-sigma frequency

synthesizer. By setting the configuration parameters D_N[6:0] and D_K[19:0], a frequency

under 1GHz is produced. The structure is shown in the following figure.

PFD Loop Filter

ODDIV(1, 2, 4)

fXTAL

DSM

fRFVCO

DIVBAND_SEL[1:0]

D_N[6:0]

D_K[19:0]

IF Offset

From modulator

Frequency Synthesizer Structure

The settings for D_N and the D_K are determined by the following formulas.

For 315MHz band, ODDIV=4 (BAND_SEL[1:0]=00b)

For 433MHz band, ODDIV=2 (BAND_SEL[1:0]=01b)

For 470~510MHz band, ODDIV=2 (BAND_SEL[1:0]=10b)

For 869/915MHz band, ODDIV=1 (BAND_SEL[1:0]=11b)

𝐷𝐷_𝑁𝑁[6: 0] = 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹(𝑓𝑓𝑅𝑅𝑅𝑅 ∗ 𝑂𝑂𝐷𝐷𝐷𝐷𝑂𝑂𝑂𝑂

𝑓𝑓𝑋𝑋𝑋𝑋𝑋𝑋𝑋𝑋)

𝐷𝐷_𝐾𝐾[19: 0] = 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹(�𝑓𝑓𝑅𝑅𝑅𝑅 ∗ 𝑂𝑂𝐷𝐷𝐷𝐷𝑂𝑂𝑂𝑂

𝑓𝑓𝑋𝑋𝑋𝑋𝑋𝑋𝑋𝑋− 𝐷𝐷_𝑁𝑁[6: 0]� ∗ 220)

In the reception mode, the frequency synthesizer generates a local intermediate

frequency (LO-IF) for the RX mixer. The RXIFDOS[11:0] bits are used to generate the

required intermediate frequency offset. If the data rate is equal to or larger than 200Kbps,

the IF should be set to 300kHz, otherwise it should be set to 200Kbps. The RXIFDOS

setting value is calculated using the following formula.

𝑅𝑅𝑅𝑅𝑂𝑂𝐹𝐹𝐷𝐷𝑂𝑂𝐹𝐹[11: 0] = 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹(�𝑓𝑓𝐼𝐼𝑅𝑅𝑓𝑓𝑋𝑋𝑋𝑋𝑋𝑋𝑋𝑋

� ∗ 217)

In the transmission mode, the modulator uses the input data to generate a frequency

offset. The modulator operating mode is shown in the following description.


AN0481E V1.10 5 / 19 July 18, 2018

Modulator

The device supports GFSK modulation. Firstly, the data is filtered by an internal BT=0.5

Gaussian filter after which it is modulated according to the required frequency deviation,

fDEV. The frequency deviation is programmed using the FSCALE[11:0] bits. The modulation

index (h) should be considered when determining the frequency offset. For low data rate

applications (fS ≤ 10Kbps), a modulation index of 8 is recommended. For high data rate

applications (fS ≥ 50Kbps), a modulation index of 0.75 is recommended. For applications

where data rate is between the aforementioned boundaries (10Kbps<fS<50Kbps), keeping

the frequency deviation above 20K is recommended. The FSCALE bit field needs to be

multipled by a scaling factor for data rates equal to or larger than 100Kbps. Since the

FSACLE configuration is more complex for data rates equal to or larger than 100K, the

required values are provided in the following tables. Users can refer to the following tables

and configure the corresponding registers according to the application.

fXTAL = 16MHz Data Rate: fS(BPS) 250K 125K 50K 25K 10K 5K 2K Frequency Deviation: fDEV(Hz) 93.75K 46.875K 18.75K 50K 40K 20K 8K DTR[8:0] 001h 003h 009h 013h 031h 063h 0F9h RXIFOS[11:0] 99Ah 99Ah 666h 666h 666h 666h 666h MDIV5[5:0] 03h 07h 13h 07h 09h 13h 31h SDR[5:0] 00h 00h 00h 04h 09h 09h 09h FD_MOD[6:0] E0h E0h E0h E6h E6h E6h E6h THOLD[3:0] 4h 4h 4h 4h 4h 4h 4h CFO_DSEL[0:0] 1h 1h 1h 1h 1h 1h 1h CFO_OFFSET_EN[2:0] 0h 0h 0h 0h 0h 0h 0h FD_HOLD[7:0] 30h 30h 18h 33h 33h 1Ah 1Ah PH_DIFF_MOD[0:0] 0h 0h 1h 0h 0h 1h 1h PH_DIFF_STEP[7:0] 9Ah 9Ah 66h 66h 66h 66h 66h M_RATIO[7:0] 40h 20h 0Dh 20h 1Ah 0Dh 05h SFRATIO[1:0]=2'b 0h 0h 0h 1h 1h 3h 3h FSCALE[11:0]=12'h 444h 119h 4Ch 0CDh A4h 052h 021h CF_B12[9:0]=10'h 444h 119h 4Ch 000h 000h 000h 000h CF_B13[9:0]=10'h 285h 01Dh 000h 000h 000h 000h 000h CF_A12[9:0]=10'h 08Ah 346h 000h 000h 000h 000h 000h CF_A13[9:0]=10'h 012h 022h 000h 310h 310h 302h 302h CF_B22[9:0]=10'h 32Bh 331h 000h 000h 000h 000h 000h CF_B23[9:0]=10'h 114h 386h 000h 000h 000h 000h 000h CF_A22[9:0]=10'h 021h 012h 000h 000h 000h 000h 000h CF_A23[9:0]=10'h 078h 008h 000h 000h 000h 000h 000h

fXTAL = 19.2MHz

Data Rate: fS(BPS) 150K 100K 50K 25K 10K 5K 2K Frequency Deviation: fDEV(Hz) 56.25K 37.5K 18.75K 50K 40K 20K 8K DTR[8:0] 003h 005h 00Bh 017h 03Bh 077h 12Bh RXIFOS[11:0] 800h 800h 555h 555h 555h 555h 555h MDIV5[5:0] 07h 0Bh 17h 05h 0Bh 17h 3Bh SDR[5:0] 00h 00h 00h 07h 09h 09h 09h FD_MOD[6:0] E0h E0h E0h D5h E6h E6h E6h THOLD[3:0] 4h 4h 4h 4h 4h 4h 4h CFO_DSEL[0:0] 1h 1h 1h 1h 1h 1h 1h CFO_OFFSET_EN[2:0] 0h 0h 0h 0h 0h 0h 0h


AN0481E V1.10 6 / 19 July 18, 2018

fXTAL = 19.2MHz FD_HOLD[7:0] 30h 18h 18h 2Bh 33h 1A 1A PH_DIFF_MOD[0:0] 0h 1h 1h 0h 0h 1h 1h PH_DIFF_STEP[7:0] 80h 55h 55h 55h 55h 55h 55h M_RATIO[7:0] 20h 15h 0Bh 20h 15h 0Bh 04h SFRATIO[1:0]=2'b 0h 0h 0h 1h 1h 3h 3h FSCALE[11:0]=12'h 133h 096h 040h 0ABh 89h 044h 01Ch CF_B12[9:0]=10'h 013h 014h 000h 000h 000h 000h 000h CF_B13[9:0]=10'h 33Eh 356h 000h 000h 000h 000h 000h CF_A12[9:0]=10'h 01Ch 016h 000h 310h 310h 302h 302h CF_A13[9:0]=10'h 329h 346h 000h 000h 000h 000h 000h CF_B22[9:0]=10'h 365h 360h 000h 000h 000h 000h 000h CF_B23[9:0]=10'h 01Fh 032h 000h 000h 000h 000h 000h CF_A22[9:0]=10'h 3E7h 3A6h 000h 000h 000h 000h 000h CF_A23[9:0]=10'h 015h 024h 000h 000h 000h 000h 000h

Transmission Data Packet Format

In wireless transmission, the transmitted data will be packaged with some specific data

packet formats, thus reducing the error signal transmission. Different encoding methods

can be used to increase successful data transmission. The BC3601 device supports a

general packet format as shown in the following description. The transmitted data is

composed of the Preamble, the SYNCWORD, the Trailer and the DATA. The DATA field is

composed of different data fields (Field) and various optional encoding formats. In

addition, all the DATA functions can only be activated in the FIFO mode. All the

transmission data fields and the encoding format descriptions are shown as follows:

TX: 1~256 bytesRX: 1/2/4 bytes

Preamble SYNCWORD

TX: 4/6/8 bytesRX: 4/6/8 bytes

Trailer

4 bits

Header

1~2 bytes

PLEN

1 byte(optional)

DATA CRC

2 bytes

CRC calculation (optional)

FEC encode/decode (optional)

Whitening (optional)

Manchester encode/decode (optional)

Max. 255 bytes

PID Address 0 Address 1

2 bits 6 bits 8 bits (optional)

Data Packet Format

Preamble

The packet starts with a repeat signal of 1010 or 0101, which is called the preamble. The

data rate can be obtained from the preamble which can be used as a correction for the

receiver. The packet starts a preamble of 1~256 bytes set by TXPMLEN[7:0] in the

transmission mode. In the reception mode, the preamble detection length is limited to 1, 2

or 4 bytes selected by RXPMLEN[1:0]. The preamble format is 1010… or 0101…

depending upon the SYNCWORD MSB bit. If MSB=1, the preamble format=0101…, if

MSB=0, the preamble format=1010….


AN0481E V1.10 7 / 19 July 18, 2018

SYNCWORD

The SYNCWORD length is 4~8 bytes set by SYNCLEN bit field. The receiver and transmitter

SYNCWORD should be configured the same to ensure correct communication. Set the

SYNCWORD using the SPI interface keyboard command (Write SYNCWORD command,

0x10). In addition, the data should be BCH code.

Trailer

The trailer field is fixed at 4 bits which is a concatenating field between SYNCWORD and

the latter payload. The trailer format will follow SYNCWORD LSB to inverse. If LSB=1, the

trailer format=0101, if LSB=0, the trailer format=1010.

The preamble and trailer field changes are affected by SYNCWORD as the following

figure shows.

Preamble MSB LSBSYNCWORD Trailer

10100101···01 0 ... 01 ... 1 01011010···10 Preamble and Trailer Change

Header

The header (Payload Header) contains the packet identification (PID) and packet address

(Address) data fields. The PID is used to identify the packet when using the

Auto-Transmit-Receive (ATR) function. The packet address is the function that defines the

home address. If not matched, the BC3601 will not move the following incoming data into

the FIFO. The header is enabled by PLH_EN and the packet address is optional using the

PLHA and PLHEA fields. The address field length can be 6 or 14 bits set by PLHLEN.


AN0481E V1.10 8 / 19 July 18, 2018

PLEN - Payload Length

The PLEN field is used to decide the payload length which indicates how many bytes in

the packet will be shifted into the FIFO. The PLEN field is enabled by PLLEN_EN. If

PLLEN_EN=1, the TXDLEN will be added to the PLEN field automatically in data

transmission periods. In data reception periods, the RX data length is determined by the

PLEN field. If PLLEN_EN=0, the TX/RX data length is set by TXDLEN/RXDLEN.

DATA

The DATA is that which the users write to the FIFO or read from the FIFO. A data write to

the FIFO or read from the FIFO is implemented using the SPI interface keyboard

command (FIFO Write/Read command, 0x11/0x91).

CRC - Cyclic Redundancy Check

The transmitted data will be operated on using the Cyclic Redundancy Check (CRC), which

calculates and stores in the CRC field, after which the CRC field will be transmitted. In the

receive mode, the received data will be operated on using the Cyclic Redundancy Check

(CRC) which calculates and compares it with the transmitted CRC. The RXCRCF flag will

be set high automatically when a RX CRC failure condition occurs. The CRC field is

enabled by CRC_EN. There are two CRC formulas selected by setting the CRCFMT bit.

CRCFMT=0: CCITT-16-CRC G(X)=X16 + X12 + X5 + 1 CRCFMT=1: IBC-16_CRC G(X)=X16 + X15 + X2 + 1

FEC - Forward Error Correction

The FEC function is that which encodes the transmitted data by (7, 4) Hamming code and

transmits the data. Hamming (7, 4) encodes four bits of data into seven bits by adding

three parity bits. The encoded data is 7/4 times long. The receiver may correct errors if

the received data is encoded by FEC. The FEC function can be enabled by FEC_EN.


AN0481E V1.10 9 / 19 July 18, 2018

Whitening

The whitening function is that which adds the whitening code to the transmitted data and

transmits the data. The transmitted data anti-disturbance ability can be enhanced after it

is encoded by whitening. The BC3601 uses the PN7 code to encode the transmitted data.

It requires a whitening seed to be used as the noise source to enable this function. The

whitening seed is set by the WHTSD bit field. Note that the whitening seed cannot be set

to zero, otherwise the whitening function will be invalid. The whitening function can be

enabled by WHT_EN.

Manchester

This function is that which encodes the transmitted data using the Manchester code and

transmits the data. It makes the transmitter and receiver data easy to synchronize. Each

bit after Manchester encoding will be extended into two bits. Refer to the following figure

for an example. The Manchester function can be enabled by MCH_EN.

Clock

1 0 1 0 0 1 1 1 0 0 1

Data

Manchester(IEEE 802.3)

Manchester Code Example

Direct Mode

After power on, the BC3601 default values will be loaded automatically after which the

device will enter the deep sleep mode. The following steps show the data transmitting and

receiving procedures in the Direct Mode:

Step1. Set parameters: write the relevant values to the internal control bit fields such as

D_N, D_K, FSCALE and DTR, etc. using the SPI interface.

Step2. Set SYNCWORD: the SYNCWORD which determines the TX/RX preamble length

which is set by TXPMLEN/RXPMLEN. Set the SYNCWORD using the SPI

interface keyboard command (write SYNCWORD command, 0x10).

Step3. Set the GIO pins: set the internal GIOxS bit fields using the SPI interface, refer to

the BC3601 datasheet for setting values details. In general, users can set the GIO

pins as follows: GIO1 is used as the data output/input, GIO2 is used as the

interrupt request output, GIO3 is used as the TRBCLK in data transmission period

and GIO4 is used as the TRBCLK in data reception period, (GIO1S=0b010,

GIO2S=0b101, GIO3S=0b1000, GIO4S=0b1001).


AN0481E V1.10 10 / 19 July 18, 2018

Step4. Wake up the BC3601: the BC3601 will enter the light sleep mode using the SPI

interface keyboard command (Light Sleep Command, 0x0C).

Step5. Wait for the crystal oscillator to stabilise: determine whether the XCLK_RDY bit

has been set high or not.

Step6. Set to the Direct mode: set DIR_EN to 1.

Step7. Enable the TX/RX mode: The RX or TX mode should first be selected by the

RTX_SEL bit (0: RX, 1: TX), then set the SX_EN and ACAL_EN to 11 to enable

the frequency synthesizer and the auto calibration functions. Set RTX_EN high to

enable the BC3601 to start transmitting/receiving the data after the automatic

correction function is completed. The automatic correction process should take

about 300μs.

Step8. Output/read data: The GIOx pin will shift out or shift in the transmission data, the

GIOx pin configuration depends on the set value. Note that the device will first

transmit/receive the preamble, SYNCWORD and the trailer when

transmitting/receiving data, and then correctly transfer/receive data according to

TBCLK/RBCLK.

The accompanying flowchart shows the device state switching in the Direct mode. There

is an internal low frequency RC oscillator in the BC3601 to effectively reduce the wake-up

time in the Idle mode.

Power Down

Power On

Deep Sleep

Light Sleep

Standby

TX RX

Idle CalibrationsLight Sleep

Deep Sleep

Idle

Deep Sleep

Idle

OM[2:0]=000b OM[2:0]=000b

OM[2]=1

OM[1:0]=00bOM[1:0]=01b (RX)OM[1:0]=11b (TX)(wait~35μs)

Light Sleep(~1ms)

Auto (calibration completed)

Calibration enabled

OM[2]=1

Direct Mode State Diagram


AN0481E V1.10 11 / 19 July 18, 2018

Use the Direct mode correctly as shown in the following diagram.

RF Pin

SPI Interface

Operating Mode Light Sleep Standby TX Mode Light Sleep

Next Command

Preamble+SYNC+1010b+Payload

Transmitting TimeRF Setting Time

OM[1:0]=11b

OM[2]=1b

OM[2:0]=000b

…

…

TXD

TBCLK

TX Timing in Direct Mode

RF Pin

SPI Interface

Operating Mode Light Sleep Standby RX Mode Light Sleep

Preamble+SYNC+1010b+Payload

Receiving TimeRF Setting Time

SYNC matched

Payload

…

RXD

RBCLK

Next CommandOM[1:0]=01b

OM[2]=1b

OM[2:0]=000b

Waiting Time

RX Timing in Direct Mode

FIFO Mode

After power on, the default value of the BC3601 will be set automatically, and then the

device will enter the deep sleep mode. The following steps show the data transmit and

receive procedures in the FIFO mode:

Step1. Set parameters: write the relevant values to the internal control bit fields such as

D_N, D_K, FSCALE and DTR, etc. using the SPI interface.

Step2. Set SYNCWORD: The SYNCWORD determines the TX/RX preamble length

which is set by TXPMLEN/RXPMLEN. Set the SYNCWORD using the SPI

interface keyboard command (write SYNCWORD command, 0x10).

Step3. Set the format of the transmission data: set the PKT1~PKT9 registers.

Step4. Set to the FIFO Mode: clear DIR_EN to 0.

Step5. Reset the FIFO pointer: Reset the FIFO pointer using the SPI interface keyboard

command (TX/RX FIFO Address Pointer Reset Command, 0x09/0x89), then

TXFFSA[5:0] is cleared to 0.

Step6. Write data to the FIFO: fill out the FIFO using the SPI command (TX FIFO Write

Command, 0x11). Skip this step for the receive procedure.

Step7. Enable the TX/RX mode: enable the TX/RX mode using the SPI keyboard

command (TX/RX mode command, 0x0E/0x8E).


AN0481E V1.10 12 / 19 July 18, 2018

Step8. Wait for the data transfer to finish. Determine whether the TXCMPIF/RXCMPIF bit

has been set high or not.

Step9. Read data from the FIFO: read data from the FIFO using the SPI command (RX

FIFO read command, 0x91). Skip this step in the transmit procedure.

After step 7, the device state switching is shown in the following flowchart. There is an

internal low frequency RC oscillator in the BC3601 to effectively reduce the wake-up time

in the Idle mode.

Power Down

Power On

Deep Sleep(<1μA)

Light Sleep(0.65mA)

Standby(5.5mA)

TX RX(13.5~14.5mA)

Idle(<2μA)

CalibrationsLight Sleep

Deep Sleep

Idle

Deep Sleep

Idle

Auto (TX completed)/Light Sleep

Auto (RX completed)/Light Sleep

TX/(Auto) RX/(Auto)

Light Sleep Standby/RX/TX(~35μs)

Light Sleep(~1ms)

Auto (calibration completed)

Calibration enabled

FIFO Mode State Diagram

Use the FIFO mode correctly, as shown in the following diagram.

RF Pin

SPI Interface

Operating Mode Light Sleep Standby TX Mode Light Sleep

TX Next CommandStrobe Command

Preamble+ID+Payload

Transmitting TimeRF Setting Time TX Timing in FIFO Mode

RF Pin

SPI Interface

Operating Mode Light Sleep Standby RX Mode Light Sleep

RX Next CommandStrobe Command

Preamble+ID+Payload

Receiving TimeRF Setting TimeWaiting Time

RX Timing in FIFO Mode


AN0481E V1.10 13 / 19 July 18, 2018

RF Pin

SPI Interface

Operating Mode Standby→TX/RX IDLE

TX/RX

Preamble+ID+Payload

Timer Expire

LightSleep

IDLE

IDLE

LightSleep

TX/RXLightSleep

LightSleep

LightSleep Standby→TX/RX

Preamble+ID+Payload

IDLELightSleep

IDLE LightSleep

Timer Expire Timer Expire

1ms 1ms

Periodical TX/RX Timing in FIFO Mode

There are four FIFO modes which are Simple FIFO mode, Block FIFO mode, Extend

FIFO mode and Infinite FIFO mode. Refer to the BC3601 development board application

example for other mode operations.

Application Circuits

Application Circuit

Descriptions: There are three areas where special attention is required in the application

circuit. The first of these is the antenna with the label ANT1, the second is the high

frequency output/input matching circuit which includes L1~L5 and C4~C10, and the third

is the external connector with the label J1. These application circuit note details will be

described in the following sections.

BOM:

Designator Descriptions Value

Unit Manufacturer Part Number 315MHz 433MHz 470MHz 868MHz

U1 RF Transceiver — Pcs Holtek BC3601 R1~R4 Resistor 0 Ω Walsin WR04X0R0JFR C1~C3 Capacitor 1u F muRata GRM1555R61A105KE15

C4 Capacitor 1.5p 1p 1p N.C. F muRata GRM1555C1H1R5CA01 GRM1555C1H1R0CA01

C5 Capacitor 100p F muRata GRM1555C1H101JA01

C6 Capacitor 12p 10p 8p N.C. F muRata GRM1555C1H120JA01 GRM1555C1H100JA01 GRM1555C1H8R0DA01

C7 Capacitor 24p 22p 15p 3.3p F muRata

GRM1555C1H240JA01 GRM1555C1H220JA01 GRM1555C1H150JA01 GRM1555C1H3R3CA01


AN0481E V1.10 14 / 19 July 18, 2018

Designator Descriptions Value

Unit Manufacturer Part Number 315MHz 433MHz 470MHz 868MHz

C8 Capacitor 15p 12p 8p 5.6p F muRata

GRM1555C1H150JA01 GRM1555C1H120JA01 GRM1555C1H8R0DA01 GRM1555C1H5R6DA01

C9 Capacitor 100p 68p 68p 68p F muRata GRM1555C1H100JA01 GRM1555C1H680JA01

C10 Capacitor N.C. — — C11 Capacitor 1μ F muRata GRM155R61A105KE15 C12 Capacitor 10n F muRata GRM155R71H103KA88

C14~C15 Capacitor 1μ F muRata GRM155R61A105KE15 C16~C17 Capacitor 22p F muRata GRM1555C1H220JA01

L1 Inductor 18n 15n 15n 0R H muRata LQG15HS18NJ02 LQG15HS15NJ02 WR04X0R0JFR

L2 Inductor 18n 15n 15n 8.2n H muRata LQG15HS18NJ02 LQG15HS15NJ02 LQG15HS8N2J02

L3 Inductor 18n 8.2n 5.6n 3.3n H muRata

LQG15HS18NJ02 LQG15HS8N2J02 LQG15HS5N6S02 LQG15HS3N3S02

L4 Inductor 82n 68n 47n 18n H muRata

LQG15HS82NJ02 LQG15HS68NJ02 LQG15HS47NJ02 LQG15HS18NJ02

L5 Inductor 100n 82n 82n 82n H muRata LQG15HSR10J02 LQG15HS82NJ02

J1 Connector 9 pin — —

External Connector Description When the RF Transceiver IC is used, the external MCU may use the following external

connectors, the related descriptions are shown in the following table.

Pin No Symbol Description 1 AGND System GND 2 VDD System Power, Supply voltage 2.0V~3.6V 3 CSN SPI chip select input, low active 4 GPIO1 Multi-function I/O 1 5 GPIO2 Multi-function I/O 2 6 SDIO SPI data input/output 7 SCK SPI clock input 8 GPIO3 Multi-function I/O 3 9 GPIO4 Multi-function I/O 4

RF Output/Input Matching Circuit To receive high frequency signals, in addition to require an antenna, an impedance

matching circuit is also required before the device receives the RF signals from the

antenna. As shown in following figure, good impedance matching will reduce the noise to

increase the reception sensitivity. A network analyser will normally be required to adjust

the impedance matching. The selected capacitors and inductors should have high Q

values for improved signal reception efficiency.


AN0481E V1.10 15 / 19 July 18, 2018

Output/Input Matching Circuit

The recommended values for different frequency bands PCB layout are listed in the

following table.

Designator 315MHz 433MHz 470MHz 868MHz Unit C4 1.5 1 1 N.C pF C5 100 100 100 100 pF C6 12 10 8 N.C. pF C7 24 22 15 3.3 pF C8 15 12 8 5.6 pF C9 100 68 68 68 pF C10 N.C. N.C. N.C. N.C. — L1 18 15 15 0R nH L2 18 15 15 8.2 nH L3 18 8.2 5.6 3.3 nH L4 82 68 47 18 nH L5 100 82 82 82 nH

Note: If the PCB layout is changed, the impedance matching circuit should be adjusted

accordingly.

Antenna Selection Guides Users can select a dipole or patch antennas with a 50Ω SMA interface as shown in

following figure.

Or use a λ/4-long copper wire, single conductor or stranded wire as shown in following

figure.

Attention should be paid to the considerations in the next section for laying out an

antenna directly on the circuit board.

A n te n n a

R F O U T

V D D

L 5

C 5

L 2L 1

C 8C 6 C 7

L 3 R F IN

C 9

C 1 0

C 4

L 4


AN0481E V1.10 16 / 19 July 18, 2018

PCB Layout Note

Component Placement Rules

The first consideration should be the RF signal path. The related component placement

and the PADs between these components should be placed as close as possible to the

device to shorten the wire length. Refer to the following figure.

Enough space must be reserved for the extra width of the VCC and GND traces.

Routing

As right angles more easily accumulate charge, they will cause point discharges which

will influence PCB stability. It is recommended to conduct all routing using 45 degree

bevels or arc angles.

The distance between two traces should not be less than 6 mils.

The distance between a trace and through holes should not be less than 6 mils.

The distance between two adjacent through holes should not be less than 6 mils.

The width of the VCC and GND main traces should not be less than 12mils.

Power lines should be connected to a bypass capacitor.

The Exposed Pad under the device should have poured copper traces as complete as

possible without other routings, especially in the IC and RF matching circuit. Otherwise it

will affect the RF signal performance. Refer to the following figure.


AN0481E V1.10 17 / 19 July 18, 2018

The IC Pin 4, pin 9 and pin 21 can be directly connected to the external GND which is

under the device for PCB layout. It is recommended that these pins are connected to the

external GND together if there is enough space.

The wire length between the crystal oscillator and the IC should be designed as short as

possible to avoid adversely affecting the power. The bottom layer beneath the crystal

oscillator should have poured copper traces as complete as possible without other

power path or signal routings. Enough distance must be reserved between the crystal

oscillator and the power supply or poured copper traces to separate them. Refer to the

following figure.

Antenna

The bottom layer beneath the antenna components should not have poured copper

traces to avoid adversely affecting the RF signal performance.

The matching circuit for the antenna should have poured copper traces otherwise it will

experience interference during RF signal operation.

With the exception of RF signal matched components, other components should not be

located near the antenna to reduce interference on the RF signals


AN0481E V1.10 18 / 19 July 18, 2018

Module PCB Layout Example

Top View

Bottom View

Conclusion This application note has introduced the Holtek BC3601 wireless transceiver IC operation

principles and control methodology. Using the SPI interface, users can control the device

to operate at the required frequency and in different modes. The device will enter the RF

signal output/input mode using different commands. A matching circuit is required to be

connected to the RF output/input pin, RFOUT/RFIN. This note will help users to use the

device more easily.


AN0481E V1.10 19 / 19 July 18, 2018

Versions and Modify Information

Date Author Issue

2018.07.16 何信智(Ho,Walers)

V1.10. 1. Update tables in the Modulator section. 2. Add register diagrams in Preamble, SYNCWORD,

Header, PLEN, Whitening sections.

2018.01.03 何信智(Ho,Walers) First Version

Reference Files

Reference file: BC3601 DataSheet.

For more information, refer to the Holtek official website http://www.holtek.com.

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