Beam Secondary Shower Acquisition System: Igloo2 GBT Implementation Upgrade

Student MeetingJose Luis Sirvent

PhD. Student07/04/2014

GBT-FPGA Overview in Igloo2(Clock Management)

Tx_CLK (240MHz)

Rx_CLK (240MHz)

TX_Data_P (4.8Gbps)TX_Data_N (4.8Gbps)

Rx_Word (19 bits)@ 240 MHz

TX_Frame_CLK (40MHz)

Data_In (83 bits)@40Mhz

TX_Word_CLK (240MHz)

RefCLK1_P (120MHz)RefCLK1_N (120MHz)

RX_Data_P (4.8Gbps)RX_Data_N (4.8Gbps)

GBT_TXScramblerEncoderGearbox

Tx_Word (19 bits)@ 240MHz

GBT_MGTSERDES_0

Vendor Specific IP

TX_PLL

GBT_RXGearboxDecoder

Descrambler

Data_Out (83 bits)@ 40Mhz

GBT_BANK (Very simplified view)

RX_Frame_CLK (40MHz)

RX_Word_CLK (240MHz)

RX_PLL

SERDES_INIT_MASTERAPB_BUS (PLL)

GBT-FPGA on Igloo2:The MGT block

GBT-FPGA on Igloo2: Testing GBT_TX & GBT_RX modified modules

• It was needed to verify that the TX & RX modules work well with the modifications done.• Dual Port Rams Xilinx IPs substituted by Microsemi Ips (GBT-FPGA STD Version)• Design unconstrained up to now. (Improvements are spected)

84 Bits @ 40MHz 20 Bits @ 240MHz 84 Bits @ 40MHz

GBT Frame:

Data visible to GBT-TX and from GBT-RX84 bits @ 40MHz

GBT-FPGA on Igloo2 : Testing GBT_TX & GBT_RX modified modules

• It was needed to verify that the TX & RX modules work well with the modifications done.• Dual Port Rams Xilinx IPs substituted by Microsemi Ips (GBT-FPGA STD Version)• Design unconstrained up to now. (Improvements are spected)

84 Bits @ 40MHz 20 Bits @ 240MHz 84 Bits @ 40MHz

• TX & RX Frame CLK: Comes from the same FRAME_CLK (40MHz)• TX & RX Word CLK: Comes from the same WORD_CLK (240 MHz)• Both clocks are artificially injected in the TestBench.• The TX & RX frames are well recovered with a delay ~ 320ns.

GBT-FPGA on Igloo2 : Testing GBT_TX & GBT_RX modified modules

Static frame well recovered!!

GBT-FPGA on Igloo2 : Let’s connect all together GBT_TX, GBT_MGT & GBT_RX

Simulation with static Frame: 0x0000BABEAC1DADCDCFFFF

84 Bits @ 40MHz 20 Bits @ 240MHz 84 Bits @ 40MHz20 Bits @ 240MHz1 Bit @ 4.8GHz

Dynamic frame well detected!!We see the TX & RX Flags for delay determination

Delay ~ 314 ns(Non deterministic, STD Version)

Simulation with dynamic Frame: Segmented counter

GBT-FPGA on Igloo2 : Let’s connect all together GBT_TX, GBT_MGT & GBT_RX

84 Bits @ 40MHz 20 Bits @ 240MHz 84 Bits @ 40MHz20 Bits @ 240MHz1 Bit @ 4.8GHz

Slide from Manoel Barros Marin

130.3 ns

GBT-FPGA on Igloo2 : Comparing data with specked results from LATOP version

GBT-FPGA on Igloo2 : Next Steps…. we are almost done with this1. Verify practically the simulation results Program the FPGA and see

2. Start applying optimizations in the code Solve some warnings and apply constrains

3. Study possible synchronization issues Check that these results are not a mirage

4. Check initialization sequence It’s very important for the correct operation

5. Check the repetitively of the link latency maybe there are very few changes…

6. Include UART modules for USB Communication Better resources for debugging

7. Start with TWEPP’14 Abstract:Deadline 30/04/2014 and need approval from Bernd & Rhori Jones