bel 14 sequential logic

8/3/2019 Bel 14 Sequential Logic

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Flip-Flops

A f lip-f lop is basically a sequential circuit with a memory where

the output is f unction not only of the present inputs but also of

the past circuit states.

The f undamental, most important characteristic of a f lip-f lop is

that it has a ³memory´

Sequential Logic Circuits

The timing or sequencing history of the input signals plays a role

in determining in the output f or sequential logic devices

Sequential logic system must have some f orm of memory

The outputs of a sequential logic system must have some f orm of

memory

Examples of sequential logic devices include f lip-f lops,registers, counters and latches.

S. Kal, IIT-Kharagpur



33

It has two stable states which are called 1 (High) or 0 (Low). It has

two complementary level outputs called Q and Q. When Q is atstate 1, Q is at state 0 and vice versa.

Enabled / Disabled inputs :

For an AND or NAND gate, if one input is ³0´, the output will be³0´ or ³1´ independent on other inputs, since

F = A.B.C f or AND

F = A.B.C f or NAND

One selected input takes control of the gate and the gate is³disabled´ ( ³inhibit´) with respect to any other input.

Alternatively, if the selected input is at logic ³1´, it does not takecontrol, and the gate is enabled to respond to other inputs.

Similarly in OR or NOR gate, a selected input takes control anddisabled f or other inputs, when selected input goes to logic ³1´.

FLIP-FLOPS

Q




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SRSR FlipFlip--FlopFlop

1. As long as the inputs S and R are both 0, the outputs of the flip-flop remain

unchanged

2. When S = 1 and R = 0, the flip-flop is set to Q = 1 and Q = 0.

3. When S = 0 and R = 1, the flip is reset to Q = 0 and Q = 1.

4. It is not used to place S = 1 and R = 1 simultaneously since the output will

be unpredictable.S. Kal, IIT-Kharagpur



55

SRSR FlipFlip--FlopFlop usingusing NORNOR andand NANDNAND gategate

1. For the input condition, S = 0, R = 0, theoutput of NOR gates A and B depends on the

other inputs. If we assume that initially Q = 0

and Q = 1, then, NOR A will be disabled and

its output, Q = 0. Since the output Q is f eed to

input of NOR B, the output of NOR B(Q) will

be 1. Thus, this input condition does not

change the state of

thef lip-

f lops and theoutput will remain the same as earlier.

2. When S = 1, R = 0, the output of NOR B is

disabled and its output is always 0, i.e. Q = 0

and thus Q = 1 as the inputs of NOR A are

both 0

3. When S = 0, R = 1, the output of NOR A willbe disabled and its output is always 0, i.e. Q

= 0 and thus Q = 1 since the inputs of NOR B

are both 0

4. The last input condition in, S = 1 and R = 1, is not used as it f orces the output of the

NOR gates to the low state, I.e. both Q = Q = 0S. Kal, IIT-Kharagpur



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The exact times at which any output can change state is determined

by a signal termed clock signal. The clock signal can be periodicsquare wave or an aperiodic collection of pulses.

Flip Flops can be level triggered ( latch) or edge triggered (positive or

negative)

Clocked SR Flip-Flop

Edges of positive

and negative pulse

Symbol of a SR Flip-

f lop, (b)positive

edge-triggered

and (c) negative

edge-triggered




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Achange be

f ore B change

No problem

B change bef ore A change, f or a moment, A = 1, B = 1, S = 1, @unintentional change of the output

If B changes at a time (t bef ore A changes, S will be in error f or onlythis time (t

Solution:

S and R inputs determine the eventual state of the FF but theexact moment of the response of the FF to these inputs isdetermined by an auxiliary signal

State transitions can be def erred until all input logic levelsestablished

Need f or clocked FF

Assume R = 0, S = 0 f or

A = 1, B = 0

Simultaneous change of

A, B should not change

Q, DQ




88

A Clocked SR Flip-Flop using NAND gates

1. If S = 0 and R = 0, the output

state remains unchanged

2. If S = 1 and R = 0, the f lip-f lop

output is set to 1

3. If S = 0 and R = 1, the f lip-f lop

output is reset to 0

4. S and R should never be 1. The words µnot allowed¶ in the last row indicate

that the input condition f or that row is not allowed.S. Kal, IIT-Kharagpur



99

When Pr = Cr = 1, the output gates are enabled, i.e. neither of these inputsaffects the operation of the flip-flop. In case power is switched on initially S =R = 0, the output states may be decided by the preset and clear inputs. If Pr = 0, Cr = 1, then Q = 1. Since the output of N 1 connects as input of N2, all theinputs of N2 are 1(R = 0) and the output Q = 0. The flip-flop is in set state.Similarly, Pr = 1, Cr = 0 gives Q = 0, Q = 1, and the flip-flop is in reset state.The flip-flop will be disabled when both Pr and Cr inputs are 0,

RC Clock Edge-triggered Flip-Flop usingPreset and Clear Inputs




1010

Diff iculties of positive Edge-Triggering Digital system generally uses common clock wave f rom f or all

the f lip-f lops in the system. The data inputs of f lip-f lops may be

derived entirely or in part f rom the outputs of other f lip-f lops.

Because of the f inite time clock stay at the enabling level

(Ck=1), the f lip-f lops connected in cascade would response af ter each successive f lip-f lop propagation delay so long as Ck

remained at Ck=1

Solution:

Use of narrow train of positive pulses; (i) The pulse duration will

be very short in comparison with the interval between pulsespgenerating and handling appropriately narrow pulses might well

represent the state of the art circuitry. p (ii) Use of too narrow

pulses to avoid the timing diff iculty described above, cause the

problem of triggering the f lip-f lop reliably

Master-Slave SR Flip-Flop




1111

A better solution would be to use of f lip-f lops designed so that thetriggering transition is f rom the enabling to the disabling level of

the clock, I.e., negative edge-triggered transition





1212

Master-slave f lip-f lop is a kind of f lip-f lop, which respondswhen the clock makes a transition to the disable level. Ituses two individual clocked SR f lip-f lop ± one f lip-f lop iscalled the master and the other the slave. The Ck is

applied to the input gates of

the master, but the clockcomplement DC is applied to the input gates of the slave

When Ck goes high, the data at S and R are registered inthe master but restrained f rom passing on to the slave.When the Ck goes low, at which time the input gates (N1,N

2) are disabled, the data in the master (QM) aretransf erred to the slave f lip-f lop and appear at the outputQS and D QS





1313

JK FlipJK Flip--FlopFlop




1414

J ± K Flip ± Flop

Let J=K=0, both the input gates are disabled and the clock willnot change the FF state. Hence Qn+1 = Qn.

J=0, K=1, (i) initially FF reset state ie Q = 0, then gate A disabledbecause J=0, gate B disabled as Q=0. Hence Ck will not movethe FF out of the reset state. (ii) J=0, K=1, initially FF in set

state, ie Q=1. Then gateA

disabled asJ

=0, but B enabled asQ=1, Ck will cause a transf er of FF to the reset state with Q=0.Thus, J=0, K=1, the Ck will set the FF in the reset state if it isnot already in the reset state.

Similarly, J=1, K=0, the Ck will set the FF in set state if it is notalready in the set state.

J=1, K=1, which of the gates A or B is enabled depends entirelyon Qn and Qn ie on the state of the FF. If Qn=0, the Ck will setthe FF to Qn+1=1. If Qn=1. The Ck will set the FF to Qn+1=0. Thuseach cycle of the Ck will change the state of the FF. This isknown as toggle mode operation of the FF.




1515

³R ace Around´ Problem of J-K Flip-Flop

In a J-K f lip f lop, when clock = 0, both the input gates are

disabled, so the f lip-f lop does not respond to the J-K inputs and

remains in the earlier state.

Let, when J = 1, K = 1, Ck = 0, then Q = 0, Q = 1.

Now if Ck changes 0 p 1, the gate A is enabled which results in

Q = 0p 1 and hence Q = 1p 0

Thereaf ter the gate B is enabled and hence Q = 0p1 and Q =

1p

0. Thus the output toggles between the two statescontinuously so long as Ck =1.

This is called race around phenomena

J ± K Flip ± Flop




1616

If the

f eedback lines

A, B are disconnected, it becomes amaster-slave S- R with J = S, K = R.

When Ck goes 0p1, master is enabled and slave is disabled.

Thus the input at J, K is transf erred to the output of master, QM

and QM, but it cannot be f urther transmitted, since slave is

disabled.

When Ck goes back 1p0, master is disabled and the slave is

enabled. Slave transf ers data f rom QM, QM to Q, Q.

In this case, ³race around´ problem is avoided, since as Ck

goes 0 p1 with J = K = 1, master ³toggles´, but slave remainsinoperative.

Master ± Slave JK f lip-f lop




1717

Master Master--Slave JK FlipSlave JK Flip--FlopFlop




1818

D Flip ± Flop

The D f lip-f lop, also called a data f lip-f lop, uses a SR f lip-f lop

The logical signal, i.e., the data, is applied to S terminal of an SR

f lip-f lop or J terminal of a JK f lip-f lop. The complement of the data

is then applied to the R or K terminal

In this type of f lip-f lop, there is no possibilities of ambiguous

stateS. Kal, IIT-Kharagpur



1919

D Flip ± Flop

If D=

J

=0, thenK

=DD = 1 and the output Q = 0, so the

f lip-f lop goes to the reset state.

If D=J=1, then K =DD = 0 and the output Q = 1, so the f lip-f lop goes to the set state.

The truth table of this f lip-f lop indicates that the input is

transf erred to the output at the end of the clock pulse.Thus the output af ter clock pulse equals the input at Dbef ore clock pulse

The transf er of data f rom input to output is delayed andthis f lip-f lop is also called delayed f lip-f lop

As the bit on D input is transf erred to the output at thenext clock pulse, these unit f unction as a 1-bit delaydevice and is used as a temporary storage latch




2020

A f lip-f lop can store or remember or register a single bit and is

theref ore ref erred to as a one bit register . If we require that N

bits be remembered or registered, N f lip-f lops are required.

When an array of f lip-f lops has a number of bits in storage, it

becomes necessary on occasion to shif t bits f rom one f lip-f lop to another. An array of f lip-f lops which permits this

shif ting is called a shift register .

There are two methods f or shif ting binary inf ormation into a

register. The f irst involves shif ting the inf ormation into the

register one bit at a time in series f ashion and leads to the

development of a serial shift register .

Shif t Registers




2121

The second method involves shif ting all the bits into theregister at the same time and leads to the development of a

parallel shift register .

The size of a register is determined by the size of the number to be stored. In a serial shif t register it requires n clock pulses

to shif t an n-bit number into the register.

Two other usef ul operations which can be per f ormed with thebasic shif t register are shift right and shift left .

A bit shif ted out of the last f lip-f lop is lost. When it isnecessary to preserve the bits stored in the register, this can

be achieved by coupling the output of the last f lip-f lop back tothe data input of the f irst f lip-f lop. In such a register, the bitswill circulate around the register, shif ting one f lip-f lop at eachclocking. A register so connected is called an end-around- carry shift register or ring counter.

Shif t Registers




2222

(a) 4-bit serial shift register; (b) D flip-flop from JK flip-flop

Shif t Registers




2323

Timing Diagram of a 4-bit Shif t Registers




2424

Acounter is probably one o

f the most use

f ul and versatilesubsystem in a digital system. It can be used as an instrument

f or measuring time (and theref ore period of f requency)

A f lip-f lop has two states. So an array of N f lip-f lops has 2N

possible states. If the array is interconnected in such a waythat the state of the array advances af ter each cycle of the

input wavef orm (clock), then if af ter ³k´ cycles, the arrayreturns to its initial state, the array is called a counter of

modulo ³k´ or mod-k counter.

Let the states of 3 f lip-f lops change in the f ollowing manner with input clock cycles:

Counters

It is a mod - 5 counter.S. Kal, IIT-Kharagpur



2525

If the counter counts all possible states of the array of N f lip-

f lops, it is a mod-2N counter.

Counters

When the output of one f lip-f lop drives another, we call thecounter a ripple counter: A f lip-f lop has to change statesbef ore it can trigger the B f lip-f lop; B has to change bef ore it

can trigger C; and sof orth. The triggers move through the

f lip-f lops like a ripple in water. Because of this, the overall

propagation delay time is sum of the individual delays and Ithas a speed limitation. Such type of counters are called serialor asynchronous counter(ripple).




2626

The ripple counter is simple and straightf orward in operation

and construction and usually requires a minimum hardware.

Counters

Four-bit ( mod-16 ) Ripple Counter




2727

The speed limitation of ripple counter can be overcome by theuse of a synchronous or parallel counter . The diff erence here

is that every f lip-f lop is triggered by the common clock. Thus,

they all make their transitions simultaneously.

Counters

A mode ± 16 Synchronous Counter S. Kal, IIT-Kharagpur



2828

Active-high decoder circuit for mod-8 counter. All flip-flops are clearedinitially, so that Q0 = Q1 = Q2 = 0

Ripple Counter (Mod ± 8)




2929

Decoder Truth Table




3030

Propagation Delay of a Logic Gate


bel 14 sequential logic

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