benq-ldp6100

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DLP PROJECTOR SERVICE MANUAL MODEL：PB6100 / PB6200

CAUTION

BEFORE SERVICING THE PROJECTOR,

READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

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Index

1. Safety Precautions -------------------------------- 3

2. Engineering Specification---------------------- 4

3. Spare Parts List ---------------------------------- 32

4. Block Diagram ------------------------------------ 36

5. Packing Description ---------------------------- 44

6. Factory OSD Operation ------------------------ 50

7. Firmware upgrade procedure --------------- 57

8. RS232 Communication Protocol ----------- 61

9. Trouble Shooting Guide ----------------------- 73

10. CUSTOMER ACCEPTANCE CRITERIA ---- 78

11. Schematics ---------------------------------------- 96

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1. Safety Precautions

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2. Engineering Specification

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3. Spare Parts List Model : PB6100 Item Component Description Type

1 42.J8618.001 U/C PC+ABS PB6100 R

2 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2

3 54.J8612.001 BALLAST PHG201G16 PB6100 R

4 60.J8605.001 ASSY Lower Case PB6100 R

5 23.10102.001 BLOWER 12V 50*50*20MM ADDA R

6 60.J8617.001 ASSY LAMPBOX PB6100 R

7 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R

8 60.J8604.001 ASSY R/C PB6100 R

9 55.J8608.001 PCBA REAR IR BD PB6100 2

10 65.J8602.001 ASSY AC INLET+THERM SW PB6100 R

11 55.J5019.001 PCBA THERMAL BD DX850 2

12 55.J5020.001 PCBA EMI BD DX850 2

13 55.J8601.001 PCBA MAIN BD PB6100 2

14 60.J8607.001 ASSY DOOR PB6100 R

15 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI 2

16 65.J8603.001 CW DIA44DEG110 PB6100 PRODISC R


18 55.J8623.001 PCBA CHIP BD PB6100 2

19 65.J7602.001 PL ZOOM PB7200 ASIA R

20 71.08060.000 IC DMD 0.6SVGA 8060-624C 12DDR R

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Model : PB6100 Item Component Description Type

21 31.J8601.001 BADGE AL PLATE PB6100 R

22 60.J1334.001 ASSY CAP LENS SL700X R

23 60.J8603.001 ASSY F/C PB6100 R

24 55.J8611.001 PCBA PFC BD PB6100 2

25 55.J8613.001 PCBA FAN BD PB6100 2

26 65.J5003.001 FOOT ADJ DX850 R

27 44.J0502.005 CTN 415*325*255 PB6100/BENQ VI R

28 47.J8605.001 CUSHION FRONT EPE PB6100 R

29 47.J8606.001 CUSHION REAR EPE PB6100 PB6100 R

30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R

31 50.J0508.503 SIGNAL/C 15/15P 20276 1800MM R

32 50.J1303.501 CABLE RCA Y/Y 1600MM BLK R

33 56.26J86.001 REMOTE CR14AI PB6100 R

34 42.20019.002 BAG PE 250*350 LD FP741/NEC R

35 46.00003.012 CARD WARRANTY 7254E R

36 49.J8601.001 MANUAL USER PB6100/ PB6200 R

37 53.J8601.001 CD MANUAL USER PB6100/ PB6200 R

38 60.J8618.CG1 ASSY Service LAMP 200W/U PB6100 0

39 60.J8621.001 ASSY S2+ EGN 12D PB6100 0

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1 55.J8501.001 PCBA MAIN BD PB6200 2

2 42.J8618.001 U/C PC+ABS PB6100 R

3 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2

4 54.J8612.001 BALLAST PHG201G16 PB6100 R

5 55.J5020.001 PCBA EMI BD DX850 2

6 60.J8605.001 ASSY L/C PB6100 R

7 55.J8608.001 PCBA REAR IR BD PB6100 2

8 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R

9 60.J8607.001 ASSY DOOR PB6100 R

10 23.10102.001 BLOWER 12V 50*50*20MM ADDA R

11 60.J8617.001 ASSY LAMPBOX PB6100 R

12 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI 2

13 65.J8603.001 CW DIA44DEG110 PB6100 PRODISC R

14 60.J8621.001 ASSY S2+ EGN 12D PB6100 0

15 55.J8623.001 PCBA CHIP BD PB6100 2

16 71.08060.000 IC DMD 0.6SVGA 8060-624C 12DDR R

17 31.J7601.061 NAME PLATE AL PB6200 R


19 60.J1334.001 ASSY CAP LENS SL700X R

20 60.J8603.001 ASSY F/C PB6100 R

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21 55.J8611.001 PCBA PFC BD PB6100 2

22 55.J8613.001 PCBA FAN BD PB6100 2

23 65.J5003.001 FOOT ADJ DX850 R

24 44.J7601.051 CTN AB PB6100/BENQ(VI) R

25 45.L2701.011 LBL CTN 120*100 BLUE FP559 R

26 47.J8605.001 CUSHION FRONT EPE PB6100 R

27 22.91007.001 SKT PLUG 2/3P W/G R

28 27.01818.000 CORD SVT#18*3C 10A125V 1830US R

29 44.J0501.011 CTN ASSY 350*240*48 7765P R

30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R

31 50.J0508.503 SIGNAL/C 15/15P 20276 1800MM R

32 50.J1303.501 CABLE RCA Y/Y 1600MM BLK R

33 56.26J86.001 REMOTE CR14AI PB6100 R

34 46.00003.012 CARD WARRANTY 7254E R

35 49.J8601.001 MANUAL USER PB6100/ PB6200 R

36 53.J8601.001 CD MANUAL USER PB6100/ PB6200 R

37 60.J8618.CG1 ASSY Service LAMP 200W/U PB6200 0

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4. Block Diagram PB6100 DMD projector being using the SGA DMD Engine made by BENQ, it included front end circuitry that digitizes and scaling processes for the input analog VGA and TV signals. As shown, in figure below the front end circuitry consists of : 1. Frond end Circuitry 1.1 Power supply module include PFC and DC/DC portion. DC/DC portion provide 12V, 5V and

3,3V for whole system.

1.2 Pixelworks scaler(PW166) with x86 CPU, OSD and SDRAM is used for system control. It control whole system operation and with crucial role of this system.(Include fan speed, inter-lock SW,….)

1.3 A/D-decoder(AD9883) is used for decoding VGA analog signal to digital signal(RGB 888) which

provide 24 bit true color resolution. It can accept SOG(sync on green) and composite signal for PC input. It also support YPbPr signal.

1.4 The video decoder that process TV video signal input. The TV video signal support both of

composite and S-video input and output YUV format to scaler processor. The basic block as following.

Lamp Fan1

POWER SUPPLY Module

Lamp Power

12V,5V,2.5V

AC IN

12V

Lamp Fan Power Fan

EMI Filter

PFC

IGNITOR

DC to DC

For System

2. DMD driver board that transfer PW166 scaler output RGB888 signal to DMD chip acceptable

signal for driving DMD mirror operation. The relate diagram as below:

DDP 1000

DMD Chip(0.6 SVGADDR)

Front End Circuit

RAMBUS CLOCKGEN

RAMBUS RDRAM

MOTOR DRIVER

SR16CDMD

RESET DRIVER

100MHz

60MHz

VoltageGEN

CLK

VBIASVRSTVCC2

MBRST(15:0)

VCC2

Control SignalCWY(1:CWCTR

m

DATA , CONTROL,60MHz

SENSOR BOARD

DATA-GY(7:0),RV(7:0),BU(7:0)

VSync,HSync,ACTDATA

PIXEL CLOCK(CLKIN)

Resetz,Poweron

LampLitz

Data &

Address400mHz

CWindex

Control Signal

RGB888 Signal

ThERMAL IC SENSOR

Power(12V,5V,2.5V)

12V,5V,2.5V

AD Converter

Scaler (memory +cpu+osd)

Regulator(3.3v)

EEPROM(16K bit)

From Power Supply

To DMD Driver

To DMD Driver

To DMD Driver

Video DecoderS-Video& RCA input

D-Sub Input

3)COLOR DruColor Wheel

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3. Whole system block diagram is show as below:

Power Board and BallastOptical Engine

DMD CHIP Board

Lamp On

Control Signal

RGB 888

2.5V, 5V, 12V

IR Rear Board

Keypad

Color Wheel Sensor Board

Sensor Signal

Data &

Control Signal

Color Wheel Sensor

Power & Control Data

PFC

PW166 Scaler

Color WheelDMD

Optical DeviceLamp Module

EMI Filter

BallastDC/DC

A/D ConverterVideo Decoder

Video InputS-video Input

D-Sub Input

Main Board

Fan

Fan/BD

DMD Driver

Overview The Main Board of PB6100 is mainly composed of an ADC converter(AD9883) , a ImageProcessor(PW166) , a EEPROM(24C16) and a flash memory (MBM29LV800B) .

The input signal is analog RGB format , which comes from the standard VGA D_SUB connector , the analog signal input to ADC converter , which output RGB digital data stream to Image Processor .

The Image Processor also known as “Scaler” , which indicate its main function , expand or downsize the digital picture from ADC to a fixed size digital image output .

The CPU which control the whole system is embedded inside the Image Processor , there is also a Real Time Operating System which incorporates with the CPU as hardware layer interface .

The EEPROM stores the system information such as brightness , contrast …which ensure the system operates under the most user friendly circumstance .

The Flash memory stored the Software Program which control the system , the CPU will read the Flash as its execution command .

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Block Diagram Below is the simple block diagram of PB6100 Main Board .

As the diagram shown above , here is the function of every discrete blocks . - D_SUB input

Analog RGB data input , the standard maximum analog input resolution is SXGA .There also some interface signals from the VGA cable , they are ADHSYNC – Providing the Horizontal Synchronization signal to AD9883. ADVSYNC - Providing the Vertical Synchronization signal AD9883.

DDC interface – Providing Digital Display Channel , which include VCC(Pin9) , SCL(Pin15) , SDA(Pin12) .

- Analog Flat Panel Interface (ADC Converter) , AD9883

The ADC converter digitizes the input analog RGB data signal from D_SUB and output the digital data streams to Image Processor .

The normal voltage level of analog RGB input signals is about 0.7V , while the ADC digital signal output to Image Processor is LVTTL level , about 3.3V.

The ADC , AD9883 could supports up to pixel rate at about 140MHZ , which is about SXGA 75HZ analog input signal .

D_SU

BS-V

ideoR

CA Video Decoder

SAA7118

Analg Flat PanelInterfaceAD9883

Image ProcessorPW166

Flash

EEPROM

RG

B 888

Signals

RGB888 signals

Address

Data

I2CI2C

Control Signals

I2C

Control Signals

DMD Driver

Clock GEN

Clocksignal

YUV 422

I2C

Control Signals

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There are some other interface signals related to AD9883 SOGIN – Sync On Green input from Image Processor , the signal enable the PB6100 support the very special VGA input signal . GCOAST – Input signal from Image Processor , the signal enable the PB6100 support the Machintosh analog input format . GCLK – Output to Image Processor as Pixel Clock , providing the reference clock for Image Processor . GHS – Providing the Horizontal Synchronization signal to Image Processor . GVS - Providing the Vertical Synchronization signal to Image Processor . GRE,GGE,GBE – Digital data stream to Image Processor which is higher than SXGA 75HZ .

. Image Processor (PW166) The most important IC is the image Processor , here below list its main function - Supporting input digital data stream up to UVGA and output digital data up to SXGA - Two input port , which are Graphic port ( VGA format ) and Video port ( video decoder format ) .

- Frame rate conversion , the output frame rate is independent from the input frame rate and the most important feature of the Image Processor is memory inside , there is no need of external memory for frame rate convertion . - Up and Down scaling of different input resolution , ensure the same output image size .

- Providing Bitmap OSD picture , which if more fancy than normal OSD chip . - On chip Microprocessor

The Image Processor is a highly integrated circuit , it include MCU , Scaler , Memory , OSD . This will increase the stability of the system . There is some control signals list below DCLK – pixel clock output to DMD driver BD , provided as a reference clock for DMD driver

DVS – Vertical synchronization signal output to DMD BD , provided as Vertical reference signal for DMD driver . DHS – Horizontal synchronization signal output to DMD BD , provided as Horizontal reference signal for DMD driver . DEN – Data enable signal output to DMD BD , provided as a valid data indicator signal for DMD driver . VCLK – V-port pixel clock . VPEN – V-port data enable . VVS – V-port Vertical Synchronization . VHS – V-port Horizontal Synchronization . VFILED – V-port Even/Odd frame indicator . RESETZ – Output to DMD driver BD as RESETZ signal for DMD normal operation . ABNORMAL – Input to CPU for indicating abnormal condition , if the CPU detects an

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abnormal status , it will disable lamp ignition . POWERON – Output to power to enable the other power source into normal working situation . LAMPLIT – Input signal as an indicator that the Lamp is ON or OFF LED1, LED2 – Output to enable the LED ON or OFF . IRRCVR0 – System IR input to CPU as remote control signals . MCKEXT – Memory clock to CPU . DCKEXT – Data clock to for Scaling . I2C_SDA , I2C_SCL – I2C format data transfer line .

. EEPROM Store the system information for user friendly . . Flash Memory System software was stored in this chip , the memory size is 8M bits

. DDP1000

The DDP1000 transfer signal from PW166 to DMD for driving DMD mirror operation. . Direct Rambus Memory

The DDP1000 utilizes a high speed Direct Rambus Memory. To support the RDRAM a Direct Rambus clock generator CDCR83 is utilized. It can transfer input clock from 50MHz to 400MHz.

IR Receiver schematic: The IS1U621 is miniaturized receivers for infrared remote control systems. PIN diode and pre-amplifier are assembled on lead frame, the epoxy package is designed as IR filter. The demodulated output signal can directly be decoded by a microprocessor. The main benefit is the reliable function even in disturbed ambient and the protection against uncontrolled output pulses. Electronic System Protection for abnormal state: The circuit of electronic system protection for abnormal state is used for the hardware light off and power off in abnormal state of thermal and safety issues. If the protection function is active then the software system will detect the abnormal signal.

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Sensor BD: The Sensor BD provides the color wheel index signal to DMD BD. The CWINDEX shall indicate the beginning of the red light on the DMD device. The phase of the display data on the DMD based on the CWINDEX signal. It can be configured to delay the CWINDEX for electronic alignment of the color wheel. The timing of CWINDEX and the delayed CWINDEX is shown in Figure 1. CWINDEX DELAYED CWINDEX DMD COLOR Red FIGURE 1

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PB6100 Lamp on Sequence

Signal Voltage Change Description POWERON Low High 1. This signal should go from low to high after all

the DC supplies are within spec. Then RESETZ can go high.

2. After the power key pressed 3 second continuously, the POWERON signal will activate.

RESETZ Low High DMD is working, when the DMD reset.

LAMPEN Low High Lamp lights up. LAMPLIT Low High Indicate ”Lamp on”.

PB6100 Normal Lamp off Sequence

Signal Voltage Change Description RESETZ High Low DMD is off. LAMPEN High Low Lamp is off. LAMPLIT High Low Indicate “lamp off“.

POWERON High Low Power down the system, but the peripherals of the CPU still power on.

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5. Packing Description

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6. Factory Menu 1. How to enter factory menu:

I. Hold press "UP" button until the "Lamp hours info." OSD display on

bottom-right of screen (Fig-1)

(Fig-1) Lamp Hours Info

II. Press keypad <Power> and <Blank> key simultaneously again, then enter

Factory menu.

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2. Factory layer:

I. DMD layer (Fig-3):

(Fig-3) DMD layer

1. CW delay: Adjust color wheel delay.(Note this value before upgrade software)

2. White peak: Adjust DMD white peak. In PC mode default value set 10, in Video mode is 0. Software auto set this value as source find.

3. DLP Brightness: Adjust DLP Brightness. Default setting is 36.Do not change this value.

4. DLP Contrast: Adjust DLP Contrast. Default setting is 30.Do not change this value.

5. Burn-In Hour: set how many hours to burn-in. Projector will enter burn-in mode on next selection.

6. Burn-In: After you set burn-in hours, set this selection to “On” and system will enter going to burn-in immediately. Projector will run color change (Red, Green, Blue, Black, White) on screen. System will auto turn off after burn-in hour count down to 0 and burn-in complete. (You can also cancel burn-in sequence by set this selection to “Off”).

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II. ADC layer (Fig-4): (only available when input source is analog RGB)

(Fig-4) ADC layer

1. ADC Brightness: ADC brightness auto calibration black. 2. ADC Contrast: ADC contrast auto calibration white. 3. ADC Offset RGB: value to tell you calibrate result. 4. ADC Gain RGB: value to tell you calibrate result. 5. Fac Brightness: adjust default brightness value in source PC. 6. Fac Contrast: adjust default contrast value in source PC.

III. Color layer (Fig-5):

(Fig-5) Color layer

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1. PbPr: enter PbPr color control Layer.

When Source is YPbPr (Never Change these setting) (Note these values Before Upgrade Software) PbPr G Offset : combine with user OSD brightness in YPbPr PbPr G Gain: combine with user OSD contrast in YPbPr PbPr R Offset: offset of color red PbPr G Offset: offset of color green PbPr R Gain: saturation R PbPr B Gain: saturation B 2. 6500,11500 R,G,B: 6500K/11500k submenu

(Never Change these setting) 6500 R :gain of color red while color temp is 6500 6500 G :gain of color green while color temp is 6500 6500 B :gain of color blue while color temp is 6500 6500 R :gain of color red while color temp is 11500 11500 G :gain of color green while color temp is 11500

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11500 B :gain of color blue while color temp is 11500

3. PC 9300 and Video 9300: 9300K submenu.

(Never Change these setting)

PC 9300 R :gain of color red while PC color temp is 9300 PC 9300 G :gain of color green while PC color temp is 9300 PC9300 B :gain of color blue while PC color temp is 9300 Video 9300 R :gain of color red while Video color temp is 9300 Video 9300 G :gain of color green while Video color temp is 9300 Video 9300 B :gain of color blue while Video color temp is 9300

IV. Optic layer (Fig-5):

(Fig-5) Optic layer

1. Test Pattern: system auto produce pattern for engineer test. 2. Spoke light: unit display full white. 3. Curtain Red: unit display full color red. 4. Curtain Green: unit display full color green.

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5. Curtain Blue: unit display full color blue.

V. Lamp layer (Fig-6):

(Fig-6) Lamp layer

1. Interpolation: De-interlace Mode 2. Filter: system auto select Filter. 3. Lamp Hour: value to tell you lamp usage hours. 4. Usage Hour: value to tell you unit usage hours. 5. Fac Lamp Hours: Record all of the amp usage hours 6. Data Reset: Reset all data to default include factory assign value. Never try to reset all data.

VI. Others layer (Fig-7):

(Fig-7) YPbPr layer

1. Gamma index: system auto select DLP gamma index 2. Gray value: adjust here to check DMD fail pixel.

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3. Blue value: adjust here to check DMD fail pixel. 4. Scaling: tell you what scaling mode is using now. 5. Pc/PbPr Mode: index of input timing 6. RS232: Enable / Disable RS232 control

VII. FAN Layer.

T1-DMD: DMD sensor temperature T2-Lamp: Lamp sensor temperature T3-Blwr: Blower sensor temperature F1-Lamp:Lamp fan speed in RPM F2-Blst: Blaster fan speed in RPM F3-Blwr : Blower fan speed in RPM Manual Fan Speed: Change fan speed by manual. SOG Threshold : Change SOG threshold level of AD More Options: Change to Fac7 submenu

(Fac7 Submenu)

( This menu only for control testing)

7. Firmware upgrade procedure PB6100/PB6100 Download Procedure

Hardware required 1. D-sub download cable (full ping D-SUB P/N : 50.J2402.201) 2. Download board ( P/N : 55.J1316.001 ) 3. PS2 Download cable from download BD to PC ( P/N : 50.J0510.5D1 ) 4. (Cable/RS232D MD8PM/DS9PF 1800MM) 5. Adaptor for Download BD ( DC12 V) 6. DVD player with YPbPr (Progressive) output 7. PC timing/pattern generator 8. Personal computer or laptop computer

Software required 1. FlashUpgrader.exe (or FlashUpgraderNT.exe if you’re using Windows NT®) 2. pwSDK.inf 3. romcode.hex 4. configdata.hex 5. gui.hex 6. flasher.hex

Download procedure 1. Record CW delay value in factory page 1 on the unit to be upgraded.

Fig. 1

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2. Record all Color Temperature values in factory page 3.

3. Power down the projector and turn the power switch off after cooling. 4. Setup the download board as Fig. 3

5. Connect the D-Sub to PC input of Projector.

PS2 Download cable to PC P/N : 50.J0510.5D1

Fig. 2

D-Sub connector to Projector P/N : 50.J2402.201

Power supply DC 12 V

Fig. 3

Download BD P/N : 55.J1316.001

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6. Run FlashUpgrader.exe and open the file pwSDK.inf. You can browse to locate it. Select the

correct COM port and use 115200 as the BAUD rate.(as Fig. 4)

7. Press the “Flash” button , and then turn on the power switch. (as Fig. 5)

8. Now the progress bar in the FlashUpgrader should be running. 9. Download is complete ,Pls turn off power switch , and turn ON power swit

10. Power on projector and the factory settings should be restored.

Fig. 4

Fig. 5

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ch.

60

Calibration procedure 1. Use any video pattern generator to output XGA 60Hz PC timing with 32 grayscale pattern.

Enter the factory OSD page 2 and execute ADC Brightness and ADC Contrast.(as Fig. 6)

2. Restore CW delay value and color temperature values.

Verification

Check the version number in the factory OSD page 1.(as Fig. 1)

Fig. 6

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8. RS232 Communication Protocol / Codes External Communication Protocol

External communication protocol include two parts：A. setup connecting, B. send command.

BenQ default Serial Port : Baud Rate: 19200 Parity: none Data bits: 8 Stop bits: 1 Flow Control: none

A. Setup Connecting

A typical Packet transaction session is shown in Figure 1

PC BenQ Projector

Figure 1

Host System Target

System

Packet to Target =>

<= ACK

<= Packet to Host

Packet to Target =>

<= ACK

<= Packet to Host

Packet to Target =>

a

c

e

d

b

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a. 1st Packet to Target (BenQ PB6XXX) structure like as below (Table 1)

Byte0 0xBE Byte1 0xEF

Magic Number

Byte2 0x01 Packet Type Byte3 0x05 Packet size (Low) Byte4 0x00 Packet size (High) Byte5 0xD1 CRC (Low)

Packet Header

Byte6 0xFA CRC (High) Byte7 0x01 System Info Type Byte8 0x02 Byte9 0x00

Version Number

Byte10 0x00 Object ID

Packet Payload

Byte11 0x00 Level Table 1

b. The Ack of Packet to Host (PC) (Table 2)

Ack Byte0 0x1E PAK Byte1 0xBE Byte2 0xEF

Magic Number

Byte3 0x01 Packet Type Byte4 0x05 Packet size (Low) Byte5 0x00 Packet size (High) Byte6 0xD1 CRC (Low)

Packet Header

Byte7 0xFA CRC (High) Byte8 0x01 System Info Type Byte9 0x02 Byte10 0x00

Version Number


Packet Payload

Byte12 0x00 Level Table 2 PAK means that PC will follow the received Packet data c. Packet same as 1st Packet (Table 1) d. Same as Ack (Table 2)

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e. Packet to Target (BenQ PB6XXX) structure (Table 3)


Magic Number

Byte2 0x01 Packet Type Byte3 0x05 Packet size (Low) Byte4 0x00 Packet size (High) Byte5 0xA9 CRC (Low)

Packet Header

Byte6 0xC6 CRC (High) Byte7 0x00 System Info Type Byte8 0x00 Byte9 0x00

Version Number


Packet Payload

Byte11 0x00 Level Table 3

B. Send Command 1. Introduction

Command packets consist of “Header” and “Payload”. The Packet Header is consistent for all packets. The Packet

Payload type and content varies based on the type of packet sent. The entire packet size is variable, being the sum of the

fixed-size Packet Header and variable-sized Packet Payload.

Packet Header (fixed size) Packet Payload (variable size)

Figure 2 Packet Format

Packet Header Format All Packets use the same Packet Header format illustrated Figure 3.

Byte 0 1 2 3 4 5 6

Magic Number Type Packet Payload Size CRC

0xBE 0xEF type size_lo size_hi crc_lo crc_hi

Figure 3 Packet Format

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The Packet Header size is fixed at seven bytes (Intel byte ordering is used). The following code fragments are taken

from these source files

The Packet Header definition is shown below:

typedef struct

{

BYTE ePacketType; // type of the payload

WORD nPacketSize; // size of the payload

WORD nCRCPacket; // CRC for the entire packet

} PACKET_HEADER;

Magic Number

The Magic Number is a fixed value that is used to insure packet alignment if there are partial packets received or

bytes lost. The Magic Number is a WORD in length (2 bytes). The Magic Number value is 0xEFBE. Because Intel

byte ordering is used, the ls-byte of the word is sent first (byte0 = 0xBE), then the ms-byte (byte1 = 0xEF).

Packet Type The Packet Type (ePacketType) is a BYTE in length number that defines the type of data in the packet. The following

entries are valid packet typess:

Table 4 Packet Types

Packet Payload Size The Packet Payload Size (nPacketSize) is a BYTE that defines the size of the Payload portion of the packet. If the

packet contains only header information, this is zero. Therefore, the total byte count of any packet = nPacketSize plus

7 (since the Packet Header is seven bytes long).

Packet Checksum (CRC) Each packet is CRC’ed using the tables later in this document. This number is the CRC value for the complete packet

including the Packet Header and Packet Payload. The CRC is calculated with the nCRCPacket value initialized to

zero.

Packet Type Name Packet Type Number

Description

pt_INVALID 0 Invalid Packet Type

RESERVED 1 RESERVED

pt_EVENT 2 Host can send any event defined in BenQ PB6XXX

software.

pt_OPERATION 3 Host can send any operation defined in BenQ PB6XXX

software.

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2. Packet Payload Definition

Event Packet Type The Event packet is used by the host system to send virtual events (such as Zoom, Source, Auto Adjust, etc.) to the

target system. Packet payload size is 6 bytes.

Byte Field Name Field Value Description

0-1 Virtual Event Virtual Event ID as defined through

Configurator 2-5 Parameter Parameter that can be associated with the

event. . Table 5 Event Packet Type Format

The source code definition of the Message packet data structure is:

typedef struct

{

WORD eEvent;

DWORD dwParam;

} EVENT_MESSAGE;

This lets you send any event defined in Configurator to the system including all remote, IR, or special events

Operation Packet Type

The Operation packet is used by the host system to execute operations (such as Brightness, Contrast, Image

Position, etc) in the target system. The Operation packet payload size is 25 bytes.

Byte Field Name Field

Value

Description

1 OPERATION_SET

2 OPERATION_GET

3 OPERATION_INCREMENT

4 OPERATION_DECREMENT

0 Operation Type

5 OPERATION_EXECUTE

1-2 Operation Operation ID as defined in Configurator

3-4 Is Avail Operation is available

5-8 Operation Target Used for Operation with Targets. These Targets are

defined in configurator. For instance,

op_BRIGHTNESS has a Target of either MAIN or

PIP window..

9-12 Operation Value Value of the Set on a set or the Value of the

Get on a Return.

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13-16 Operation Value of

minimum.

The Minimum Value of the set for operation

command.


maximum

The Maximum Value of the set for operation

command.


Increment

The Increment Value of the set for operation

command.

Table 6 Operation Packet Payload Format

The source code definition of the Operation packet data structure is:

typedef struct

{

eOPERATION_TYPE eOpType;

WORD eOperation;

WORD bisAvail;

DWORD dwTarget;

DWORD dwValue;

DWORD lmMin;

DWORD lmMax;

DWORD lmInc;

} OPERATION_MESSAGE;

This lets the user directly perform logical operations such as “Set Contrast = 80”.

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3. Send Command PC BenQ PB6XXX

Figure 4

a. The structure of Command (EX. input select) send to Target (BenQ PB6XXX) like as below (Table 7)


Magic Number

Byte2 0x02 Packet Type Byte3 0x06 Packet size (Low) Byte4 0x00 Packet size (High) Byte5 0x80 CRC (Low)

Packet Header

Byte6 0xC7 CRC (High) Byte7 0xC9 Byte8 0x00

Virtual Event ID

Byte9 0x00 Byte10 0x00 Byte11 0x00

Packet Payload

Byte12 0x00

Parameter

Table 7

b. Target return to Host (PC) Ack like as below Table 8 Ack Byte0 0x06 ACK

Table 8

Host System Target System

Packet to Target =>

<= ACK

a

b

68

C. Serial Communication Cable and Parameters

For external serial communication from a computer to BenQ projector, BenQ recommends manfactures use RS-232 communations over a straight through serial cable a 9 pin female D-sub9 connector. The standard D-sub9 connector on the computer is a male connector, and BenQ projector, too. The wiring between the computer and BenQ projector is a straight through cable. A 9 pin female to 9 pin female stright through cable is a very standard part and readily available in many lengths. Female D-sub9 pinout numbering and definitions on both terminal :

PW Serial uses the following default serial port settings: . Baud Rate: 19200 . Parity: none . Data bits: 8 . Stop bits: 1 . Flow Control: none

Pin number Name

2 Transmit

3 Receive

5 Ground

D. Software Flow Chart

Build serial communication port Baud rate: 19200

Parity: none Data bits: 8 Stop bits: 1

69

Transmit 1st Packet (see Table 1)

Delay 100ms

Transmit 2nd Packet (see Table1)

Delay 100ms

Transmit 3rd Packet (see Table3)

Transmit Command (see Table7)

70

Command List

Event Packet Type command: Command Packet Header (7 bytes) Packet Payload (6 bytes)

Power BE EF 02 06 00 13 CE AA 00 00 00 00 00

Auto BE EF 02 06 00 F7 C8 8E 00 00 00 00 00

Input select BE EF 02 06 00 C4 C8 8D 00 00 00 00 00

Menu BE EF 02 06 00 26 C9 8F 00 00 00 00 00

Exit BE EF 02 06 00 FE CA 97 00 00 00 00 00

Zoom + BE EF 02 06 00 AD CD B4 00 00 00 00 00

Zoom - BE EF 02 06 00 7C CC B5 00 00 00 00 00

PIP Source BE EF 02 06 00 37 C6 CE 00 00 00 00 00

Freeze BE EF 02 06 00 46 CE AF 00 00 00 00 00

Ratio BE EF 02 06 00 04 C6 CD 00 00 00 00 00

Force PC BE EF 02 06 00 AE C6 C7 00 00 00 00 00

Force Video BE EF 02 06 00 51 C6 C8 00 00 00 00 00

Force S-Video BE EF 02 06 00 80 C7 C9 00 00 00 00 00

Force YPbPr BE EF 02 06 00 B3 C7 CA 00 00 00 00 00

RS232 Power ON BE EF 02 06 00 3E C4 D7 00 00 00 00 00

RS232 Power OFF BE EF 02 06 00 C1 C4 D8 00 00 00 00 00

Blank BE EF 02 06 00 1A CC B3 00 00 00 00 00

Operation Packet Type command

PC Picture Controls Command Packet Header (7 bytes) Packet Payload (25 bytes)

Brightness + BE EF 03 19 00 44 A0 03 C7 02 CC CC 00 00 00 00 CC×16

Brightness - BE EF 03 19 00 2A 0A 04 C7 02 CC CC 00 00 00 00 CC×16

Contrast + BE EF 03 19 00 2E 19 03 C5 02 CC CC 00 00 00 00 CC×16

Contrast -

BE EF 03 19 00 40 B3 04 C5 02 CC CC 00 00 00 00 CC×16

YPbPr Picture Controls

Command Packet Header (7 bytes) Packet Payload (25 bytes)

Brightness + BE EF 03 19 00 7B 14 03 D9 02 CC CC FF FF FF FF CC×16

Brightness - BE EF 03 19 00 15 BE 04 D9 02 CC CC FF FF FF FF CC×16

Contrast + BE EF 03 19 00 FA 6A 03 F1 02 CC CC FF FF FF FF CC×16

Contrast - BE EF 03 19 00 94 C0 04 F1 02 CC CC FF FF FF FF CC×16

71

S-Video / Composite Video Picture Controls


Brightness + BE EF 03 19 00 E9 18 03 35 02 CC CC 00 00 00 00 CC x16

Brightness - BE EF 03 19 00 87 B2 04 35 02 CC CC 00 00 00 00 CC x16

Contrast + BE EF 03 19 00 16 FC 03 36 02 CC CC 00 00 00 00 CC x16

Contrast - BE EF 03 19 00 78 56 04 36 02 CC CC 00 00 00 00 CC x16

Color + BE EF 03 19 00 83 A1 03 37 02 CC CC 00 00 00 00 CC X16

Color - BE EF 03 19 00 ED 0B 04 37 02 CC CC 00 00 00 00 CC x16

Tint + BE EF 03 19 00 00 0F 03 4A 02 CC CC 00 00 00 00 CC x16

Tint - BE EF 03 19 00 6E A5 04 4A 02 CC CC 00 00 00 00 CC x16

Sharpness + BE EF 03 19 00 43 D0 03 38 02 CC CC 00 00 00 00 CC x16

Sharpness - BE EF 03 19 00 2D 74 04 38 02 CC CC 00 00 00 00 CC x16

Misc Controls


Color Temp –50 (0) BE EF 03 19 00 69 49 01 ED 02 CC CC 00 00 00 00 CE FF FF FF

CC CC CC CC CC CC CC CC CC CC CC CC

0 (10) BE EF 03 19 00 1C 89 01 ED 02 CC CC 00 00 00 00 00 00 00 00


50 (20) BE EF 03 19 00 69 1C 01 ED 02 CC CC 00 00 00 00 32 00 00 00


PIP Controls PIP Size

Off BE EF 03 19 00 15 02 01 8C 02 CC CC 01 00 00 00 03 00 00 00


Small BE EF 03 19 00 E4 42 01 8C 02 CC CC 01 00 00 00 00 00 00 00


Medium BE EF 03 19 00 74 83 01 8C 02 CC CC 01 00 00 00 01 00 00 00


Large BE EF 03 19 00 85 C3 01 8C 02 CC CC 01 00 00 00 02 00 00 00


PIP Position

Upper-Left BE EF 03 19 00 1D 66 01 43 02 CC CC 01 00 00 00 00 00 00 00


Upper-Center BE EF 03 19 00 8D A7 01 43 02 CC CC 01 00 00 00 01 00 00 00


Upper-right BE EF 03 19 00 7C E7 01 43 02 CC CC 01 00 00 00 02 00 00 00

72


Mid-Left BE EF 03 19 00 EC 26 01 43 02 CC CC 01 00 00 00 03 00 00 00


Mid-Center BE EF 03 19 00 DE 64 01 43 02 CC CC 01 00 00 00 04 00 00 00


Mid-Right BE EF 03 19 00 4E A5 01 43 02 CC CC 01 00 00 00 05 00 00 00


Lower-Left BE EF 03 19 00 BF E5 01 43 02 CC CC 01 00 00 00 06 00 00 00


Lower-Center BE EF 03 19 00 2F 24 01 43 02 CC CC 01 00 00 00 07 00 00 00


Lower-Right BE EF 03 19 00 DB 61 01 43 02 CC CC 01 00 00 00 08 00 00 00


PIP Source

S-Video BE EF 03 19 00 E8 36 01 DA 02 CC CC 01 00 00 00 03 00 00 00


Video BE EF 03 19 00 DA 74 01 DA 02 CC CC 01 00 00 00 04 00 00 00


PIP Brightness

-50 (48)

BE EF 03 19 00 FE 0B 01 35 02 CC CC 01 00 00 00 CE FF FF FF


0 (126) BE EF 03 19 00 8B CB 01 35 02 CC CC 01 00 00 00 00 00 00 00


50 (204) BE EF 03 19 00 FE 5E 01 35 02 CC CC 01 00 00 00 32 00 00 00


PIP Contrast

-50 (58)

BE EF 03 19 00 01 EF 01 36 02 CC CC 01 00 00 00 CE FF FF FF


0 (131) BE EF 03 19 00 74 2F 01 36 02 CC CC 01 00 00 00 00 00 00 00


50 (204) BE EF 03 19 00 01 BA 01 36 02 CC CC 01 00 00 00 32 00 00 00


PIP Color

–50 (129)

BE EF 03 19 00 94 B2 01 37 02 CC CC 01 00 00 00 CE FF FF FF


0 (157) BE EF 03 19 00 E1 72 01 37 02 CC CC 01 00 00 00 00 00 00 00


-50 (185) BE EF 03 19 00 94 E7 01 37 02 CC CC 01 00 00 00 32 00 00 00


PIP Tint -50 (0) BE EF 03 19 00 17 1C 01 4A 02 CC CC 01 00 00 00 CE FF FF FF


0 (128) BE EF 03 19 00 62 DC 01 4A 02 CC CC 01 00 00 00 00 00 00 00


50 (255) BE EF 03 19 00 17 49 01 4A 02 CC CC 01 00 00 00 32 00 00 00


73

9. Trouble Shooting Guide Optical Engine

No. Item Trouble Shooting Guide

1 Brightness 1. Change lamp 2. Check overfill size: If overfill too large, re-install SL and AL to

ensure correct position

2 Uniformity

1. If Uniformity is within 3% of spec: Change lamp 2. Check FM installation 3. Check overfill size: If overfill too small, re-install SL and AL

to ensure correct position

3 FOFO Contrast 1. Clean DMD 2. Clean PL

4 ANSI Contrast 1. Clean PL 2. Clean DMD 3. Change PL

5 Color Check CW 50% point. Replace CW if necessary 6 Color Uniformity Change CM

7 Blue Edge 1. Readjust LP: Make sure the LP end is touching with

DMD_HSG Datum 2. Check LP: If LP is crushed, replace with new LP

8 Blue/Purple Border 1. re-install SL and AL to ensure correct position 2. Check FM installation

9 Focus 1. Change Projection Lens 2. Put shim metal between upper side of DMD and DMD datum

10 Dust Clean DMD

11 Horizontal/Vertical Strips

1. Check connector between FPC and M/B 2. Re-install DMD with FPC 3. Check if any pin of C-Spring is missing or damaged 4. Change new FPC/C-Spring 5. Change new DMD

12 Pixel Fail Change new DMD

74

Main board

System no work

No image when graphicsis the current input

No image when videois the current input

Unable to download

Unable to saveOSD setting

Keypadmalfunction

Yes

Yes

Yes

Yes

Yes

Yes

Yes

No

No

No

No

No

No

No

No data

1.chk RN725-RN728 soldering2.chk U27,U28

1.change U21

1.change U172.chk U711 enable pins(1,4)

1.chk D_SUB cable and L92.chk GHS(UH2-4),GVS(UH702-4)3.chk U15 voltage source U12(3.3V),UB16(3.3V)4.chk U15 GHS(64),GVS(63),GFBK(65),GCLK(66)5.chk U15 soldering6.change U15

1.chk voltage input from F/B : 2.5V,5V,12V2.chk oscillator Y2,Y3 output frequency (16.257MHz,10MHz)3.chk MCLK(U24-5,130MHz) and DCLK(U25-5,40MHz)4.chk U17 whether S/W inside or bad soldering5.change U22(bad soldering)6.chk Reset IC (U14)7.chk Abnormal signal8.chk Resetz(RN25-5),Poweron(RN25-6) ,DVS(RN18-3),DEN(RN18-1),DHS(RN18-2),DCLK(RN18-4)

1.chk output from U15(RN6,RN7,RN8,RN9,RN10,RN11) [graphics input]2.chk output from U13 (Via VUV[0:7}&VY{0:7]) [video input]3.chk U22 and its peripherals (as above block)

1.chk U13 voltage source U12,UA64.chk Y1 output frequency(24.576MHz)5.chk U13 output signals to U226.chk U13 soldering7.chagne U13

75

DMD Driver Start

Power Voltage

Yes

No

Yes

DDP 1000function

No

Yes

.

PeripheralHardware

Yes

No

Image ColorNo

Yes

Image Quality

1.chk CW spinning in cloclwise2.chk CW tape position and width3.chk cutrain displayed 220us after CW index4.sequence color transition during CW spoke interval

No

Lamp On

Yes

No

1.chk J702,2.5V(4,,5,6),5V(3),12V(1)2.chk bead L710-L714,L44

1.chk clock frequency (unit:MHz) a.Y901(30)b.Y5(20) C.UY1(100) C.Motor Controller(8.33)2.chk ACTDATA,POWERON,RESETZ,CLKIN,HSYNC, VSYNC,SYNCVALID from Front End3.chk CW spinning frequency 120Hz , if wrong, chk MTRDATA , MTRCLK , MTRSELZ1.LAMPEN Signal to Ballast.

2. 3.5s after LAMPLIT,DMD Become Active and Display an Image .

1.Output from DAD1000 : VBIAS(22-25V),VRST(-26V), VCC2(7.5V)2.chk control signal of DMD chip from U29(RN40,RN45)3.chk data sequence from U29 to FPC(RN37~RN44)4.chk JP2,JP3 soldering

1.chk CWINDEX2.chk LAMPEN3.chk LAMPLIT

76

Smaller boards

Keypadfunction

1.chk U1 voltage source(5V)2.chk U1 output signal (always 5Vdc in regular time,no pulse voltage)

Yes

Yes

No

No

NoRear Front IRfunction

FAN/BD

Fan control: 1.chk the voltage of QF1 (5,6,7,8) 2.chk the fan voltage U502(2,15),U503(8) 3.check Y501(32.768kHz)No 5V 1.Check Q701 & thermal Breaker

LED dark 1.chk LED voltage from J1 2.chk the mounting direction of LEDsNo work 1.chk buttons contact to PCB

PFC BOARD

77

DC-DC BOARD

Appendix: Abbreviations PWR Power supply module M/B Main board F/C Front End Circuit D/B DMD Driver Circuit FPC FPC transmission board K/B Keypad board R/B Rear IR board CW Color wheel S/W Software S/B Sensor board F/B Fan board AL Aspherical Lens SL Spherical Lens FG Front Glass LP Light Pipe FM Fold Mirror CM Concave Mirror PL Projection Lens

78

10. CUSTOMER ACCEPTANCE CRITERIA CONTENT

1.0 SCOPE 2.0 PURPOSE 3.0 APPLICATION 4.0 DEFINITION 5.0 CLASSIFICATION OF DEFECTS 6.0 CLASSIFICATION OF DEFECTIVES 7.0 INSPECTION STANDARD 8.0 GENERAL RULES 9.0 TEST CONDITIONS

10.0 TEST EQUIPMENTS

PART Ⅰ INSPECTION CRITERIA

1. PACKING, MARKING AND ACCESSORY 2. APPEARANCE ON VISIBLE PARTS 3. INSTALLATION 4. FUNCTION 5. SAFETY DEFECT CLASSES

79

1.0 SCOPE This document establishes the general workmanship standards and functional acceptance criteria for PROJECTOR produced by BENQ.

2.0 PURPOSE The purpose of this publication is to define a procedure for inspection of the PROJECTOR by means of a customer acceptance test, the method of evaluation of defects and rules for specifying acceptance levels.

3.0 APPLICATION

The "Customer Acceptance Criteria" is applicable to the inspection of the PROJECTOR, completely packed and ready for dispatch to customers. Unless otherwise specified, the customer acceptance inspection should be conducted at manufacturer's site.

4.0 DEFINITION

The "Customer Acceptance Criteria" is the document defining the process of examining, testing or otherwise comparing the product with a given set of specified technical, esthetic and workmanship requirements leading to an evaluation of the "degree of fitness for use", including possible personal injury or property damage for the use of the product.

5.0 CLASSIFICATION OF DEFECTS

The defects are grouped into the following classes: 5.1 Critical defect

A critical defect is a defect which judgment and experience indicate that there is likely to result in hazardous or unsafe conditions for individuals using product.

5.2 Major defect

A major defect is a defect, other than critical one, is likely to result in failure, or to reduce materially the usability of the product for its intended purpose.

5.3 Minor defect

A minor defect is a defect that is not likely to reduce materially the usability of its intended purpose, or is a departure from established standards having little bearing on the effective use of operation of the product.

80

6.0 CLASSIFICATION OF DEFECTIVES

A defective is a product which contains one or more defects. The defective will be classified into following classes: 6.1 Critical defective

A critical defective contains one or more critical defects and may also contain major and/or minor defects.

6.2 Major defective

A major defective contains one or more major defects and may also contain minor defects but contains no critical defect.

6.3 Minor defective

A minor defective contains one or more minor defects but contains no critical and major defects.

7.0 INSPECTION STANDARD

Unless otherwise specified, the inspection standard will be defined by MIL-STD-105E, NORMAL INSPECTION LEVEL Ⅱ, SINGLE SAMPLING PLAN.

7.1 Acceptance Quality Level

7.1.1 Critical Defect:

When a critical defect is found, this must be reported immediately upon detection, the lot or batch shall be rejected and further shipments shall be held up pending instructions from the responsible person in relevant department.

7.1.2 Under normal sampling Critical Defective : 0% AQL

Major Defective : 0.65% AQL

Minor Defective : 2.5% AQL

7.1.3 Under special sampling Critical Defective : 0% AQL

Major Defective : 1.0% AQL

Minor Defective : 4.0% AQL

81

8.0 GENERAL RULES

8.1 The inspection must be carried out by trained inspectors who have good knowledge about the product.

8.2 The inspection must be based upon the documents concerning the completely

assembled and packed product. 8.3 When more defects appear with the same unit only the most serious defect

have to be taken into account. 8.4 Defects found in accessory packed with the product such as Cable,

Connector, Manual, CD and the like, and being inspected as a part of the complete product, must be included in the evaluation.

8.5 The evaluation must be within the limits of the product specification and, for not specified characteristics, refer to the sample machine or the judgment of BENQ QA Engineer. But any kind of proposals or judgments must be reasonable and acceptable by both sides.

8.6 Faults must be able to be repeatedly demonstrated.

9.0 TEST CONDITIONS

Unless other prescription, the test conditions are as followings:

Nominal voltage : refer to operation manual Environmental illumination variable from 400 to 700 lux Temperature : Operating : 0~ 35 ℃ Storage : -10~ 60 ℃ Humidity: Operating : 10 ~ 90 % RH Storage : 10 ~ 90 % RH Altitude:

Operating : 0 ~ 6000 ft above sea level,

82

10.0 TEST EQUIPMENTS

10.1 Pentium with 32MB of system memory , 64M RAM and above are recommended.

10.2 Win98 or later Operation Environment 10.3 VGA or any Windows compatible display with a resolution of at

least 640x480 pixels, and set to high color or true color mode.

10.4 Quantum card/Chroma & Test pattern files 10.5 Dark room 10.6 29 points optical measure equipment 10.7 Pattern generators 10.8 DVD player 10.9 Mouse

83

PART Ⅰ INSPECTION CRITERIA

■ Packing, marking and accessory

△ Inner packing material broken. minor

△ Carton damaged with hole over 1.5 cm in diameter. minor

△ Carton crashed with dent over 5 cm in diameter. minor

△ Printing of carton is illegible. minor

△ Broken packing bag minor

☆ Spec. label's serial number not the same as carton label's. Major

☆ Packing model not the same as carton. Major

☆ Marking missing/wrong. Major

☆ Accessory shortage/wrong. Major

☆ Projector missing(found none in carton). Major

☆ Label on box missing or damaged Major

☆ Strange objects in the box Major

■ Appearance on visible parts

△ Poor printing on panel sticker(segment broken, illegible). minor

△ Damage or deviation when viewed at a distance of 50 cm. minor

△ Cover/case is dirty(removable). minor

△ Cover/case exists black spot(irremovable). minor

△ Cover/case is scratched. (Note 1) minor

△ Spec Label reverse, rugged, illegible printing. minor

△ LED sink over 1 mm. minor

☆ Label/screws shortage or missing. Major

☆ Wrong logo of panel sticker. Major

☆ Wrong spec. label printing. Major

☆ Label on product wrong or missing Major

■ Installation

☆ Any accessory which are failed Major

to meet the installation purpose

84

■ Function

△ Abnormal sound during projection(from 50 cm). minor

☆ LED won’t light / No power / can't work. Major

☆ Other function test please refer to Note 2.

■ Safety defect class

☆ Any item which violates the approved safety standard. major

★ Electrical shock or smoke. Critical

Note 1 : Please refer to attachment 1. Note 2 : Please refer to attachment 2.

Attachment 1 Scratch Acceptance Any scratch which exceeds the maximum allowance is treated as a minor defect.

Black spot, Soil, Bubble inspective standard Spec. (mm2) A side B side C side 備註

0.05 mm2以下 between 2 cm

Accept Accept Accept

0.05 ~0.1mm2 between 5 cm

4 5 6

Black Soil Bubble

0.1~0 5m㎡ between 5cm

3 4 5

1. A、B、C side defineted as Diagram - A1

2.. LOGO 周邊 2 cm 內不可有 0.05m㎡以上之斑點 (0.05m㎡以內斑點不計)

0.2~0.3mm2 between 10cm

2

3

4

PS : Any kind of defect not seen from 45 cm(18 inches)(It’s about an arm’s length) with 15 seconds should not be a reject. Any scratch which exceeds the maximum allowance is treated as a minor defect. Spec. (mm) A side B side C side Remake

W<0.1 L<1 1 2 3

W<0.1 L<2 0 1 2

Scratch Dent

W<0.1 L<3 0 0 1

1. The separation distance between defects must great than 10mm.

85

Diagram - A1 Definition of Projector's sides

86

Attachment 2 Quality Specification of PB6100 Following item’s spec. will base on Engineering spec. Item Spec Remarks 1. Brightness Minimum 1120 lumens major 2. Uniformity Minimum 50 % major

3. ANSI Contrast Ratio 150:1 major 4. FOFO contrast Ratio 700:1 major 5. Screen Size For Testing 60” at 2m major 6 .Focus Range 1.5~6m major 7. Keystone Distortion <1.0% major 8. Audible Noise Level Typical 34dBA at 25°C major Maximum 35dBA at 25°C 9. Power Connector IEC - 06 major

10. Throw Ratio 47” ±5% Diagonal at 2m major

12. Power consumption Typical 285W / Standby <15W 13. Blue Border <2 lux with 40” (diagonal) image size Purple Border <4 lux with 40” (diagonal) image size 14. Light Leakage In Active Area <1.5 lux within 47” (diagonal) image size Light Leakage out of Active Area <5 lux between of 47” (diagonal) image size and 60”

(diagonal) area 15. IR Receiver , IR Receiver X 2 (Front, Rear)

16. Check the remote control function whether it is correct

17. Check the DVD image whether it is correct

87

18.Color Temprature 1.8.1 White .298±.040 .318±.040 1.8.2 Red .627±.040 .369±.040 1.8.3 Green .333±.040 .559±.040 1.8.4 Blue .137±.040 .061±.040

19. Focus 1.9.1 for PROT lens 1.Pattern:区 pattern

2.Observation:2m to screen(wide only) 3.Criteria: 1.pattern uniform and clear-------->OK 2.If can’t focus uniform and clear，switch to 区 pattern and focus uniform clear all over screen (central must clear than corner) Measure flare and defocus a.flare:R,G≦2.5 B≦3.5

b.defocus:≦2.5

(区 pattern: Chroma 84,flare and defocus pattern: chroma 34)

1.9.2 for AOCI lens(A.17) (A.19) Flare : Defocus

R <=4.5 R < = 2.0

G<=4.5 G < = 2.0

B<=4.5 B < = 2.0 Pattern(A.19) Center of screen All other area

R-G <1/2 <1 G-B <1/2 <1

20.Lateral Color

R-B <2/3 <1 21. Compatibility

PC Compatible 640X400 1024X768, compressed 1280X1024; Composite-Sync; Sync-on-Green; Interlace Mode (8514A); Detailed Support Timing Specification refer to Appendix E.1

H-Sync 24 ~ 88 KHz V-Sync 48 ~ 100 Hz

21.1 PC

PC Frequency Limitation

Pixel Clock 140 MHz 21.2 Video NTSC/ NTSC4.43/ PAL (Including PAL-M, PAL-N)/

SECAM/ PAL60/ 21.3 YPbPr NTSC 480i/ 480p, PAL 576i/ 720p, HDTV 720p/1080i

88

DMD Image Specification

1. SCOPE This document specifies the image quality requirements applicable to the XGA RGBW Palmtop Configuration F Component Kit. The Component Kit provides the XGA RGBW Palmtop Projector with Digital Imaging functionality based on Digital Micromirror Device (DMD) technology.

2. Definitions 2.1 Blemish

A blemish is an obstruction, reflection, or refraction of light that is visible, but out of focus in the projected image under specified conditions of inspection (see Table 1). It is caused by a particle, scratch, or other artifact located in the image illumination path.

2.2 Dark pixel A dark pixel is a single pixel or mirror that is stuck in the OFF position and is visibly

darker than the surrounding mirrors. 2.3 Bright pixel A single pixel or mirror that is stuck in the ON position and is visibly brighter than

the surrounding mirrors. 2.4 Unstable pixel A single pixel or mirror that does not operate in sequence with parameters loaded

into memory. The unstable pixel appears to be flickering asynchronously with the image.

2.5 Adjacent Two or more stuck pixels sharing a common border or common point , also referred

to as a cluster . 2.6 Streaks Artifact resulting from localized variation in mirror tilt angle relative to surrounding

mirrors . They are similar in appearance to window scratches but appear at the mirror

Level . Streaks appear as faint diagonal or arcing patterns in the image. 2.7 Sea of Mirrors ( SOM ) SOM is a rectangular array of off-state mirrors surrounding the active area. 2.8 Eyecatcher A small localized light “spot” which haas high spatial frequency and high

differential Brightness. These are due to various DMD window or window aperture “defects” Including : digs , voids , particles and scratches.

89

2.9 Border Artifacts All variations of these artifacts are acceptable under this image quality

specification. Border artifacts are a general category of image artifacts that may show up on screen in the area outside of the active array. Border artifacts include: Exposed Bond Wires , Exposed Metal 2 , and Reflective Edge.

2.9.1 Bond Wires

Bond Wires attach the die to the superstructure. If visible, they will appear as short light parallel lines outside of the Sea of Mirrors ( SOM ).

2.9.2 Exposed Metal 2 is due to a shift in positioning of either the die or the

window aperture which may allow light to be reflected off of the layer of metal 2 that is below the super structure ( mirrors ). This defect is located at the outer edge of the SOM.

2.9.3 Reflective Edge

Reflective Edge is light that may reflect from the edge of the DMD”s window aperture onto the projection screen. It will appear as a thin diffuse line outside of the SOM.

2.10 Two Zone Blue 60 Screen The Two Zone Blue 60 screen is used to test for major dark blemishes. Refer to Figure

1 for configuration. All areas of the screen are colored a Microsoft Paintbrush blue 60 ( green and red set at 0 , blue set at 60 ).

NOTE : If linear degamma table being used in order to generate an equivalent blue level on the test screen image.

2.11 Two Zone Gray 10 Screen The Two Zone Gray 10 screen is used to test for major light blemishes. Refer to Figure

1 for configuration. All areas of the screen are colored a Microsoft Paintbrush gray 10 ( green , red , and blue set at 10 ).

NOTE : If linear degamma is not used then the Microsoft Paintbrush values must be adjusted to match the degamma table being used in order to generate an equivalent gray level on the test screen image.

90

3. ACCEPTANCE REQUIREMENTS 3.1 Conditions of Acceptance All DMD image quality defects must be determined under the folloeing projected

image test conditions : a. Projector degamma shall be linear. b. Projector error diffusion shall be “off “. c. Projector brightness and contrast settings shall be set to nominal. d. The diagonal size of the projected image shall be a minimum of 60 inches. e. The projection screen shall be 1X gain. f. The image shall be in focus during all Table 1 tests. g. The projected image shall be inspected from an 8 feet minimum viewing distance.

3.2 Test Sequence Tests shall be run in the sequence listed in Table 1

TABLE 1. Image Quality Specification

SEQ #

TEST SCREEN ACCEPTANCE CRITERIA

1 Major Dark Blemish

Two Zone Blue 60

1. No blemish will be darker than Microsoft Blue 60 in the Critical Zone

2. <=2 blemishes in the Non-Critical Zone 3. No blemish will be >1/2” long / diameter

2 Major Light Blemish

Two Zone Gray 10

1. No blemish will be lighter than Microsoft Gray 10 in the Critical Zone

2. <=2 blemishes in the Non Critical Zone 3. No blemish will be > 1/2” long / diameter

3 Eyecatcher Gray 10 1. No eyecatcher will be lighter than Microsoft Gray 10

Streaks Blue 60 Gray 10 White

1. No streaks

91

Projected Image

Any screen 1. No adjacent pixels. 2. No bright pixels ( Active Area ) 3. <= 1 bright pixel ( SOM ) 4. ≤ 4 dark pixels 5. ≤ 6 minor blemishes. 6. No DMD window aperture shadowing on the

Active Area 7. No unstable pixels in Active Area

Notes : 1. Projected blemish numbers include the count for the shadow of the artifact in addition to

the artifact itself, so that the count usually represents a single artifact on the window. 2. No blemish shall be more than 5 inches long or have a total area of more than 5 square

inches on a 60 inch diagonal projected image. ( <= 1/2 inch for Major Blemish tests ) 3. During all Table 1 tests , projected images shall be inspected in accordance with the

conditions of inspection specified in Section 3. 4. The rejection basis for all cosmetic DMD defects ( scratches , nicks , particles ) will be

the projected image tests referenced in Table 1. 5. Any other image quality issue not specifically defined in this document shall be

acceptable. 6. Black screens shall not be used as a basis for rejecting DMDs for image quality.

Figure 1. Major Blemish Two Zone Screen

Non Critical Zone

Critical Zone

center 25%

92

Optical Measurement 1.Scope: This document describes critical optical related test definitions and Instructions for data or video projectors. The other general terminologies are specified in ANSI IT7.228-1997. 2.General Requirements

1. The unit under test should be allowed to stabilize without further adjustment for a minimum of 5 minutes, at nominal ambient room temperature of 25°C, before making measurements.

2. Measurements shall take place in a light proof room, where the only source of illumination is the projector. Less than 1 lux of the light on the screen shall be from any source other than the projector.

3. All measurements shall be made on flat screens that do not provide any advantage to the performance of the unit

4. All measurements shall be made at standard color temperature setting, 100% white image (per ANSI IT7.228-1997), except where noted

3.Practical Requirements

1. When measuring contrast manually, operators should not wear white clothing since light reflected from white clothing can influence the measurement.

2. Unless otherwise specified, the projection lens is set in the widest zoom position since zoom function can influence the measurement.

3. Measurement should be performed with Minolta Chromameter, Model CL-100, or equivalent.

A1. ANSI BRIGHTNESS ANSI Lumens = (L1+L2+L3+L4+L5+L6+L7+L8+L9)/9 (lux) x A(m^2) A (Area) = W * H (m^2) W: width of projected image (m) H: height of projected image (m)

93

L11

L13 L12

L10

L1 L2

L4

L7

L5

L8 L9

L3

L6

Note: L10, L11, L12, L13 are located at 10% of the distance from corner itself to L5 A2. BRIGHTNESS UNIFORMITY Brightness Uniformity = Minimum (L10,L11,L12,L13)/ Average (L1,L2,L3,L4,L5,L6,L7,L8,L9) A3. JBMA UNIFORMITY JBMA Uniformity = Average (L1,L3,L7,L9)/ L5 A4. ANSI CONTRAST ANSI Contrast = Average lux value of the white rectangles/Average lux value of the black rectangles Contrast Ratio shall be determined from illuminance values obtained from a black-and-white ”chessboard” pattern consisting of 16 equal rectangles. The white rectangles shall be at 100% gray and the black rectangles at 0% gray. Illuminance measurements shall be made at the center of each of the rectangles. A5. FOFO CONTRAST FOFO Contrast = Lux value at the center of a solid white screen/the lux value at the center of a solid black screen A6. JBMA CONTRAST JBMA Contrast = Average (L1,L2,L3,L4,L5,L6,L7,L8,L9) under solid white / Average (L1,L2,L3,L4,L5,L6,L7,L8,L9) under solid black A7. LIGHT LEAKAGE Leakage = The maximum light leakage under a solid black pattern in or outside of the projected image

94

A8. IMAGE DISTORTION Keystone = (W2-W1)/ (W1+W2) x 100% Vertical TV dist = (H1+H2-2xH3)/2H2 x100%

Horizontal TV dist = (W1+W2-2xW3)/2W1 x100% W1: image width at image bottom W2: image width at image top W3: image width at the half image height. H1: image height at image left H2: image height at image right H3: image height at half image Note: 1. Keystone and Vertical TV Distortion are recommended for Front Projection Display 2. Vertical and Horizontal TV Distortion are recommended for Rear Projection Display A9. THROW RATIO Throw ratio = projection distance / the width of the projected image A10. ZOOM RATIO Zoom ratio = maximum / minimum image diagonal size at a fixed projection distance A11. FOCUS RANGE The minimum/maximum focus distance is the minimum/maximum projection distance (The distance between the outermost element of projection lens and screen), expressed in meter, at which the image is still at its acceptable focus level.(acceptable focus level is specified by FOCUS LIMIT SAMPLE approved by customer) A12. COLOR Color is expressed as (x, y) in 1931CIE chromaticity values Note: Color is measured at the center of the screen that is entirely the measured color under default brightness and contrast settings. A13. ANSI COLOR ANSI Color is expressed as (u, v) in 1976 CIE chromaticity values Note: Color is measured at the center of the screen that is entirely the measured color under default brightness and contrast settings. A14. COLOR UNIFORMITY Color Uniformity is the maximum color difference (△x, △y) between any two points out of L1~L13

95

A15. ANSI COLOR UNIFORMITY ANSI Color Uniformity: △u’v’= [(u’1-u’0)^2+(v’1-v’0)^2]^1/2 (u’0,v’0): the average color of L1~L13 (u’1,v’1): the spot with maximum deviation from (u’0,v’0) A16. PROJECTION OFFSET Projection Offset= Image height above projection lens optical axis / Total image height x 100% Note: Optical engine should be kept horizontal attitude A17. Customer Defined Focus

i. Focus test procedure (Wide only) a. Pattern: Cross Hatch (Refer to A27 for all related test patterns) b. Steps:

Step 1: Get best focus at Screen Center with “Phon Pattern” Step 2: Check “Cross Hatch” at 60”, Wide position. Step 3: Observe R, G, B color separately and check “Center and 4 corners of

screen” for “Defocus” and “Flare” (Check line only, no check point) Step 4: Good (“Defocus” << A, “Flare” << B) No more check needed Step 5: Limit Check “Defocus” (60” <A pixels)

Check “Flare” (60” <B pixels) Step 6: Worst unit of the day Check “Letter pattern” (Screen to Observer 6m,

Wide and Tele same spec) with: “Defocus” < C pixels “Flare“ < D pixels

ii. Criteria: Measure the flare size with agreed “Grid” paper and as follows:

1.5 pixels

Grid of 1.5 pixels

Flare

Defocus

1 Pixel

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GND

FAN1_E FAN1_EFAN2_B FAN2_B

V12 V12

VDD_F VDD_F

SDA SDASCL SCL

GND

GND

Title

Size Document Number Rev.

Date: Sheet o f

Project Code

Reviewed By Approved ByPrepared By

Model Name

PCB P/N PCB Rev.

Benq CorporationOEM/ODM Model Name

99.J8677.B12-C3-304-002

FAN BOARD

1 3

ANGEL HU JACK CHEN

48.J8613.S02 S02

KEN JA CHEN

<Size>

PB610099.J8677.001

0

Wednesday, August 06, 2003

ODM

Screw Holes

Optical Points

OPOP11

OPOP2

OPOP4

H1

HOLE-V8

1

2

3

4

5

6

7

8

9

H4

HOLE-V8

1

2

3

4

5

6

7

8

9

POWER

01_POWER

GND

FAN1_EFAN2_B

V12

VDD_F

SDASCL

OPOP13

OPOP6

OPOP3

OPOP7

FAN

02_FAN

GND

SDASCL

V12

FAN1_EFAN2_B

VDD_F

OPOP12

OPOP9

OPOP10

H2

HOLE-V8

1

2

3

4

5

6

7

8

9

OPOP5

H3

HOLE-V8

1

2

3

4

5

6

7

8

9

OPOP1

OPOP8

OPOP14

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FAN2_B

FAN1_E

W18Vcc

IN

therm

FAN1_E

FAN2_B

VDD_F

GND

SCLSDA

V12

VDD

VDD

VDD

V12

2V5

380Vdc

380Vdc

V12

VDD

VDD

V12

2V5

5V

5VVDD

LAMP-SYNCLAMP-RXD

LAMPLIT

FAN_P

FAN_P

LAMPLITLAMP-SYNC

LAMP-RXD

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


99.J8677.B12-C3-304-002

FAN BOARD

2 3

ANGEL HU JACK CHEN

48.J8613.S02 S02

KEN JA CHEN

<Size>

PB610099.J8677.001

0


ODM

Note:Bllast control PinFOR DC601FOR U6301

CS702

1000P K

RF1 47

+C731010U16V

12

R73102.4K

R73131K

C63041U Z

R630430K

RF51K

CY6301

3300P Y1

W2IN

1

R70147K

R7305

330

+C6303

47U 50V

12

RF2 2K

U6301

TOP247YC 1

F5

X3

S4

D7

L2

R731230K F

U6305

PQ1CY1032ZGN

D3

VOUT 2VIN1

ON

5

FB4

G6

D730110CTQ150S3

2

1

R73112.32KF

QF1SI4431DY-T1

2

4

73

1 65

8

R73141K

TP1

1

C73070.1U K

J6302

2060089102

12

C63060.1U M

CS703

2200P J

R402100

R6308

47

+ C630247U 50V

12

R702

47

R6302

6.8

R7306

15K

D6302

ES1D

12

+ C7308220U25V

12

J730220L2021005 1

2345

G1

G2

+ CC602100U450V

12

+ C7303470U 25V

12

+ C7301470U 25V

12

CS704

2200P J

TP2

1

+ CF222U16V

12

L1 500 OHM

D6303

US1J

12

CA10.01U M

TP4

1

+ C7305220U25V

12

J7301

20D0038108

11

22

33

44

55

66

77

88

G1

G1

G2

G2

R7307

470

CC6010.47U K

C73091000P M

D7303SS24

12

RS702

47

CA20.01U M

R404100

D6301 US1M

12

PC123FY1

U630212

43

TP5

1

t TR602

NTC 5 OHM

2 1

3

W

T6301

600UH

1

2

4

5

8

9

10

RA603680K

RS701

47

R630147K

L7302

180U K

RF447K

DRILL-22

1

R6307 47L7301

10UH

CF1

0.1U M

H6

hsink2

1 2

U7302LM431

31

2

L2 500 OHM

J6301

2062010103

123

J730320L2021005

12345

G1

G2

RA602680K

TP3

1

RS704

47

J7304

20D0049108

12345678

G1

G2

+ C7302470U 25V

12

C73060.1U K

C63010.01U M

CS701

1000P K

R73045.1K

RA601680K

RS703

47

R73092.32KF

t TR601

NTC 5 OHM

2 1

Q701SI4431DY-T1

2

4

73

1 65

8

QF2MMST3904

1

32

D7302

SS3H10

1 2

R630910KF

R73083.32KF

RF3

10K

DC601

SF10L60U

31

R4014.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SCL

SDA

FAN1_E

FAN2_B

V12

GND

SCL

SDA

VDD_F

VDD_F

V12

VDD_F

VDD_F

V12

VDD_F

VDD_F

V12VDD_F

VDD_F

FAN1_B

FANSPIN4

32.768KHZ

FAN1_P

FANSPIN1

SCLSDA32.768KHZ

FANSPIN2

FAN1_EFAN1_B

FANSPIN1

FAN1_P

FAN4_PFANSPIN4

FAN4_P

FAN2_P

FANSPIN2

32.768KHZ

FAN2_P

SDA

SCL

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


99.J8677.B12-C3-304-002

FAN BOARD

3 3

ANGEL HU JACK CHEN

48.J8613.S02 S02

KEN JA CHEN

<Size>

PB610099.J8677.001

0


ODM

Crystal generate the clock for fan control IC.

2 fan speed control and 2 thermal sensor detect IC

Thermal sensor

Fan control IC

C519 220P J

C502

10P J

Q5042N3904

1

32

C5060.1U M

CA5080.1U M

+ C50522U16V

12

R502 10M

R50347K

CA5070.47U K

R5152.2K

R505

2.2K

Q5032SB772S

3

12

U505 G751-2

A25

A16

A07

VCC 8

SDA 1

SCL 2

O.S. 3

GN

D4

C518 220P J

R510

10K

C501

10P J

RA502

5.6K

R512 2.4K

R501 2M

J502

20L2021010

123456789

10

G1

G2

Q501SI4431DY-T1

2

4

73 1

6 58

R509

2.2K

R51410K

C5040.1U M

RB5012.2K

RA5034.7K

Q5052N3904

1

32

U501

CD4049UBCM

VDD1AR2A3BR4B5CR6C7VSS8

NC 16FR 15

F 14NC 13ER 12

E 11DR 10

D 9

Q5062SB772S

3

12

J501

20L2021004

1234

G1

G2

U503

G760A

OUT1

F.G.2

ON/OFF3

GND4

VCC 8

SDA 7

SCLK 6

CLK 5

R511

2.4K

Q5022N3904

1

32

Y501

25.6KHZ

C5100.1U M

C5072200P K

RA5014.7K

R518 OPEN

R5082.2K

R517

4.7KU502

G768B

OUT11

VCC 2

DXP1 3

DXN 4

DXP2 5RESET6

GND 7GND 8

OUT2 16

VCC 15SMBCLK14

FG2 13

SMBDATA12

ALERT11

FG110

CLK9

R5200

+ C50922U16V

12

CA5060.47U K

RB5022.2K

RA504

680

RA5052.2K

+ C50347U16V

12

R507

4.7K

R50410K

R519 OPEN

R513

10K

R5162.2K

R506820

C5082200P K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

G ND

DD[63:0]

MBRST[15:0]

P3P3V

VCC2

DMDSER

DCLK_L

LOADB_LZ

SACCLKSACBUS

SCTRL_L

TRC_L

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


99.J8677.B12-C3-304-003

CHIP BOARD

1 3

ANGEL HU KELVIN LIAO

48.J8623.S01 S01

DAVID HN LIN

<Size>

PB610099.J8677.001

0


ODM

80*2_CONN

80*2_CONN

DD[63:0]

SACCLKSACBUS

SCTRL_L

TRC_LLOADB_LZ

DCLK_L

MBRST[15:0]

DMDSER

GND

VCC2

P3P3V

DMD_CHIP

DMD_CHIP

GND

DD[63:0]

MBRST[15:0]

P3P3V

VCC2

DMDSER

DCLK_L

LOADB_LZ

SACCLKSACBUS

SCTRL_L

TRC_L

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MBRST[15:0]

DCLK_L

BINSEL0

SACCLK

MBRST11MBRST9

MBRST1MBRST3

MBRST13

MBRST7MBRST5

MBRST15MBRST14MBRST12MBRST10MBRST8

MBRST6MBRST4MBRST2MBRST0

DD48

DD24

DD28

DD26

DD40

DD32

DD62

DD36DD38

DD42

DD46DD44

DD30

TRC_L

DD50

DD34

DD52

LOADB_LZ

DD58DD56

DD60

BINSEL0BINSEL1

BINSEL1

DMDSERSACBUSSCTRL_L

DD[63:0]

DD54

DD[63:0]

DD21

DD2

DD49

DD8

DD51

DD63

DD39

DD5

DD19

DD55

DD45

DD16

DD7

DD9

DD23

DD57

DD61

DD41

DD29

DD59

DD20

DD14

DD37

DD15DD13

DD1

DD27

DD17

DD33

DD3

DD35

DD6DD4

DD12

DD31

DD47

DD53

DD22

DD25

DD11

DD43

DD18

DD10

DD0

DD[63:0]

MBRST[15:0]

DMDSER

GND

VCC2P3P3V

SACCLKSACBUSSCTRL_L

TRC_L

LOADB_LZ

DCLK_L

P3P3V VCC2

P3P3V

BINSEL0BINSEL1

BINSEL0BINSEL1

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


99.J8677.B12-C3-304-003

CHIP BOARD

2 3


48.J8623.S01 S01

DAVID HN LIN

<Size>

PB610099.J8677.001

0


ODM

BINSEL1 BINSEL0 DMD Bin0 0 B0 1 C

1 1 E1 0 D

TP116

TP42

TP29

TP56

TP60

TP127

TP31

TP65

TP57

TP132

TP28

TP130

J2

20L1065080

2468

101214161820222426283032343638404244464850525456586062646668707274767880

135791113151719212325272931333537394143454749515355575961636567697173757779

TP111

TP49

TP87

TP63

TP139

TP136

TP115

TP46

TP17

TP128

TP73

TP106

TP47TP48

TP27

TP36

TP64

TP114

TP58

TP25

R21K

TP68

TP79

TP125

J1

20L1065080

2468

101214161820222426283032343638404244464850525456586062646668707274767880

135791113151719212325272931333537394143454749515355575961636567697173757779

TP38

TP117

TP37

TP108

TP30

TP24

TP124

TP50

TP134

TP121

TP34

TP137 TP138

TP41

TP101

TP59

TP43

TP123

TP33

TP120

TP40

TP51

TP44

TP62

TP112

TP92

TP35

TP39

TP88

R11K

TP78

TP129

TP82

TP69

TP45

TP72

TP110

TP107

H1

6240019001

12

43

TP113

TP97

TP54

TP96

TP91

TP140

TP26

TP83

TP100

TP23

TP126

TP133

TP61

TP109

TP21

TP52

TP131

TP32

TP55

TP135

TP53

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SACCLK

LOADB_LZ

DCLK_L

TRC_LSCTRL_L

SACBUS

READ_OUT2

DMDSERREAD_OUT

MBRST[15:0]

MBRST14

MBRST0

MBRST9

MBRST12

MBRST3

MBRST15

MBRST6

MBRST2MBRST1

MBRST11MBRST10

MBRST13

MBRST8

MBRST5MBRST4

MBRST7

DD

60

DD

4

DD

7

DD

18

DD

15

DD

34D

D33

DD

55

DD

63

DD

23

DD

19

DD

21

DD

39

DD

58

DD

32

DD

38

DD

56

DD

62

DD

20

DD

1

DD

57

DD

17

DD

36

DD

54

DD

51

DD

28

DD

30

DD

46

DD

59

DD

35

DD

44

DD

25

VCC2

DD

52

DD

47

DD

45

DD

31

DD

41

DD

43

DD

2

DD

42

DD

5D

D37

DD

6

DD

61

DD

48

DD

24

DD

16

DD

40D

D8

DD

13

DD

3

DD

49

DD

27

DD

0

DD

53

DD

14

DD

26

DD

9D

D10

DD

12D

D11

DD

50

DD

29

DD

22DD[63:0]

DD[63:0]DD[63:0]

MBRST[15:0]

P3P3V

VCC2

DMDSER

DCLK_L

LOADB_LZ

SACCLKSACBUS

SCTRL_LTRC_L

GND

P3P3V

VCC2

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


99.J8677.B12-C3-304-003

CHIP BOARD

3 3


48.J8623.S01 S01

DAVID HN LIN

<Size>

PB610099.J8677.001

0


ODM

Optical Points

Screw Holes

U1B

DMD 0.7XGA DDR

P3P3VA05

P3P3VA17P3P3VA23P3P3VA29P3P3VD02P3P3VH30P3P3VJ01P3P3VM30P3P3VN01P3P3VV30P3P3VW01P3P3VAC05P3P3VAC09P3P3VAC15P3P3VAC21P3P3VAC27

P3P3VA11 GND U03GND T28GND R03GND P28GND P04GND N27GND M04GND M02GND L29GND L27GND L25GND J05GND J03GND H28GND H26GND F04

GN

DB

02G

ND

B08

GN

DB

14G

ND

B20

GN

DB

26G

ND

C05

GN

DC

11G

ND

C17

GN

DC

23G

ND

C29

GN

DD

08G

ND

D14

GN

DD

20G

ND

E27

GN

DA

C07

GN

DA

B26

GN

DA

B24

GN

DA

B18

GN

DA

B12

GN

DA

B06

GN

DA

A21

GN

DA

A15

GN

DA

A09

GN

DA

A07

GN

DY2

4G

ND

Y18

GN

DY1

2G

ND

V02

GN

DU

29

GND F02GND E29

C30.1U M

16V

OPOP8

H6

HOLE-V8

1

2

3

4

5

6

7

8

9

C50.1U M

16V

OPOP11

U1A

DMD 0.7XGA DDR

D0

E01

D1

E03

D2

E05

D3

G01

D4

C01

D5

G03

D6

D04

D7

G05

D8

C03

D9

H02

D10

A01

D11

H04

D12

D06

D13

H06

D14

D10

D15

K06

D16

B06

D17

K04

D18

B04

D19

L05

D20

C09

D21

L03

D22

C07

D23

A03

D24

A07

D25

D12

D26

B10

D27

A09

D28

B12

D29

C13

D30

A13

D31

A15

D32

D16

D33

B18

D34

A19

D35

A21

D36

C19

D37

D18

D38

B22

D39

B24

D40

A25

D41

C21

D42

C25

D43

M26

D44

A27

D45

K28

D46

D22

D47

K26

D48

B30

D49

K30

D50

B28

D51

J25

D52

C27

D53

J27

D54

D26

D55

J29

D56

D24

D57

G27

D58

D28

D59

G29

D60

D30

D61

F30

D62

F28

D63

F26

MBRST_0Y10 MBRST_1AB10 MBRST_2AA11 MBRST_3AC11 MBRST_4AA13 MBRST_5AC13 MBRST_6Y14 MBRST_7AB14 MBRST_8AB16 MBRST_9Y16 MBRST_10AC17 MBRST_11AA17 MBRST_12AC19 MBRST_13AA19 MBRST_14AB20 MBRST_15Y20

DCLKC15

LOADBB16

SAC_CLKAC25SAC_BUSAA25

SCTRLN03TRCL01

PRG_FUS_ENAC23BI_MODEY08BI_TOFK02

READ_OUT2 AB22READ_OUT AA23

SCAN_TEST M28

VCC2A N29VCC2B P02VCC2C P30VCC2D R01VCC2E R29VCC2F T02VCC2G T30VCC2H U01

EVCC0 Y22EVCC1 AB08

OPOP4

C70.1U M

16V

C100.1U M

16V

H3

HOLE-V8

1

2

3

4

5

6

7

8

9

H5

HOLE-V8

1

2

3

4

5

6

7

8

9

C12

0.1U M16V

OPOP6

OPOP10

C14

0.1U M16V

H4

HOLE-V8

1

2

3

4

5

6

7

8

9

OPOP2

TP2T POINT A

1

OPOP13

OPOP14

C90.1U M

16V

C13

0.1U M16V

OPOP7

OPOP12

OPOP5

OPOP1

C20.1U M

16V

TP1T POINT A

1

C11

0.1U M16V

OPOP9

C40.1U M

16V

+

C810U

10V

12

C60.1U M

16V

+C11U16V20%

12

OPOP3

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

LAM

PE

N

VD

D_D

3.3V

_D

V12_D

LAMPEN

2V5_DDCLKDCLK

DGE[7:0]DGE[7:0]

RESETZ

DBE[7:0]DBE[7:0]

DVSDVS

LAMPLITZ

DHSDHS

VD

D

DEN DEN

LAMPLITZ

POWERON POWERON

3.3V

3.3V

SCL

2V5_

D

SD

A

DRE[7:0]DRE[7:0]

SC

L0

3.3V_D

RESETZ

SC

L

3.3V

_D

VDD_D

SDA

SD

A0

FA

N_P

ECO-MODE

EC

O-M

OD

E

V12

_D

VD

D VD

D

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

1 20

DAVID HN LIN KELVIN LIAO

99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1

Tuesday, October 07, 2003

<OEM/ODM>

PAGE_3002_DMD

DRE[7:0]

DGE[7:0]

DBE[7:0]

SC

L0

RESETZPOWERON

DEN

DHSDVS

DCLK

LAMPLITZ

V12_D

2V5_D

VDD_D

3.3V_D

SD

A0

GN

D

LAMPEN

ECO-MODE

VD

D

PAGE_5004_DISPLAY

3.3V

_D

SD

A0

SC

L0

SD

AS

CL

GN

D

PAGE_4003_POWER&LAMP&DETECT

GN

D

RE

SE

TZ

SD

AS

CL

LAM

PLI

TZ

LAM

PE

N

VD

D_D

V12

_D

2V5_

D

3.3V

_D

3.3V

VD

D

ECO

-MO

DE

FAN

_P

PAGE_2001_MAIN

3.3V

VD

D

POWERONRESETZ

DRE[7:0]

DGE[7:0]

DBE[7:0]

DHSDVS

DENDCLK

SCLSDA

LAMPLITZ

GND

ECO

-MO

DE

FAN

_P

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SCL

PO

WE

RO

N

GGE[7:0]GGE[7:0]

CS0n CS0n

A0

RO

MW

En

DVS

ECO-MODE

BH

EN

n

RE

SE

T

A[1

9:1]

DEN

GVSGVS

DC

KEX

T

GRE[7:0]GRE[7:0]

SDA

DGE[7:0]

DBE[7:0]

RESETZ

DCLK

GCOASTGCOAST

GFBKGFBK

LAMPLITZ

FAN_P

GBE[7:0]GBE[7:0]

GCLKGCLK

GBLKSPLGBLKSPL

CS1nCS1n

RO

MO

En

D[0

:15]

GHSGHS

VP

PE

N

DHS

POWERON

KE

YS

TON

E

DRE[7:0]

MCK

EXT

SDA

IRR

CV

R

IRRCVR

GAIN_C GAIN_CBAIN_C BAIN_C

CONTROL

HSYNC HSYNC

RAIN_C RAIN_C

TXDTXD

VSYNC_C VSYNC_C

RXD RXD

VHSVHSCVBSCVBSG

AIN

_V

VVSVVS

VY[7:0]VY[7:0]

BA

IN_V

CHROMACHROMA

SDA

LUMALUMA

VUV[7:0]VUV[7:0]

VCLKVCLK

VFIELDVFIELDVPENVPEN

RA

IN_V

AV

DD

SCL

RESETn

SCL

SDA

SCL

D[0:7]D

[0:7

]

3.3V

VDD

SCLSDA

GND

POWERON

DEN

RESETZ

LAMPLITZ

DGE[7:0]

DHS

DRE[7:0]

DCLK

DVS

DBE[7:0]

ECO-MODE

FAN_P

VDD

3.3VVDD

VDD

3.3V

VDD

3.3V 3.3V

VDD

3.3V

VDD

V33

VDD

V33

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

2 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

Note: To DDP1000 input port

Note: Lamp on/off detect signal.

Note: PW164B RS232 I/O port connect with PC ( for control ) and Ballast ( for lamp stasus )

Regect RC1 and RC2 before connect DX660 main board with INTERFACE board.

PAGE_10015_PW166

VCLK

VFIELDVVS

VHSVPEN

VY[7:0]

GGE[7:0]

GRE[7:0]

GVS

GBLKSPL

GHS

GFBKGCLK

GBE[7:0]

GCOAST

TDO

TXD

RO

MW

En

TCK

RXD

MC

KEXT

RO

MO

En

IRR

CV

R

TMS

A[1

9:1]

DC

KE

XT

RE

SE

T

D[0

:15]

SDA

DVSDHS

DRE[7:0]

DCLK

DGE[7:0]

DBE[7:0]

A0

BH

EN

n

DEN

VUV[7:0] POWERONRESETZ

DRO[7:0]

DGO[7:0]

DBO[7:0]SCL

VP

PE

N

AU

DIO

_MU

T

3.3V

CS0n

LAMPLITZ

GND

ECO-MODE

KE

YS

TON

E

AU

DIO

_VO

L

CS1n

FAN_P

VDD

D[0

:7]

CO

NTR

OL

key8

DECODE

012_DECODE

VDD

VUV[7:0]SCLSDA

V33

VY[7:0]

VHS

VVS

VPENCVBS

VCLK

VFILD

LLC1LLC2

LUMA

CHROMA

GA

IN_V

RA

IN_V

BA

IN_V

AV

DD

GND

PAGE_12017_KEY

D[0:7]

CS0nVDD

3.3VGND

CS1n

RESETn

IRR

CV

R key8

PAGE_11016_MISC

PO

WE

RO

N

DC

KE

XT

MC

KEXT

VDD

3.3V

GND KE

YS

TON

ESD

AS

CL

PAGE_8013_AFE

SCLSDA

GBLKSPL

GCOAST

HSYNC

GBE[7:0]

GGE[7:0]

GRE[7:0]

GFBK

GHSGVS

GCLK

VDD

GND

RAIN_CGAIN_CBAIN_CVSYNC_C

RA

IN_V

GA

IN_V

BA

IN_V

AV

DD V33

INPUT

011_INPUT

RXDTXD

HSYNC

BAIN_C

RAIN_CGAIN_C

VSYNC_C

CONTROL

VDD

3.3V

GN

D

CVBS

LUMA

CHROMA

PAGE_9014_MEMORY&KEYSTONE

VP

PE

N

A[1

9:1]

D[0

:15]

3.3V

GNDRO

MW

En

RO

MO

En

SCLSDA

A0

BH

EN

n

RE

SE

T

RESETn

VDD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RQ[0:7]

DQB[0:8]

DQA[0:8]

PCLKM

SCLKNSCK

SIOCMD

CFMCFMN

VREF-RDRAM

CTM

REFCLKCTMN

POWERON POWERON

DVS DVS

3.3V_D

LAMPLITZLAMPLITZ

V12_D

VDD_D

RESETZRESETZ

DHS DHS

DEN DEN

DCLK DCLK

2V5_D

LAMPEN LAMPEN

DRCGPDZ

FLA

SH

-BU

SY

Z

BINSEL1 BINSEL1

MOSCMOSCCOSC COSC

SR16ADDR2

MTRSELZ MTRSELZ

SDA0

PU

M-A

RS

TZ

SR16ADDR1SR16ADDR1

CWTACH CWATCH

SCL0

MTRDATA MTRDATAMTRCLK MTRCLK

CWINDEXCWINDEX

FSD

16

BINSEL0 BINSEL0

SR16ADDR0

SR16ADDR3

SR16MODE1

CKMTR1 CKMTR1

SR16MODE0

SR16STROBESR16SEL1SR16SEL1

SR16OEZ

SR16SEL0

DBE[7:0]DBE[7:0]

DGE[7:0]

DRE[7:0]

MBRST[0:15]

SCPDISCPDOSCPCKSCPENZ

EXT-ARSTZ

IRQZ

ECO-MODE

TRC-LDCLK-L

VCC2

VCC2

DMDSER

LOADB-LZ

SACCLK

DD[0:63]

SACBUS

SCTRL-L

EXT-ARSTZEXT-ARSTZ

VDD

DBE[7:0]

SCL0

RESETZPOWERONDEN

DHSDVS

DCLK

V12_D

2V5_D

VDD_D

3.3V_D

SDA0

GND

LAMPLITZLAMPEN

DGE[7:0]

DRE[7:0]

ECO-MODE

VDD

3.3V_D

V12_DVDD_D

2V5_D

3.3V_D

V12_D

VDD_D

2V5_D

3.3V_D

VDD_D

2V5_D

3.3V_D VDD

3.3V_D

3.3V_D2V5_D

3.3V_D

V12_D

VDD

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

3 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

From Pixelworks output

PAGE_20028_DMD_MOTOR

V12_D

CKMTR1EXT-ARSTZ

MTRSELZMTRCLKMTRDATA VDD_DCWTACH

GN

DPAGE_15023_DMD_OSC&FAN

MOSC

GND

VDD_D

CWINDEX

3.3V_D

COSC

PAGR_21029_DMD_CHIP

DD[0:63]

MBRST[0:15]

BINSEL0BINSEL1

DMDSER

LOADB-LZ

DCLK-L

VCC2

SACCLKSACBUS

SCTRL-L

TRC-L

3.3V_D

VDD

GND

PAGE_14022_DMD_MEMORY

RQ[0:7]

DQB[0:8]

DQA[0:8]

FLA

SH

-BU

SY

Z

PUM

-AR

STZ

LAMPLITZ

RESETZPOWERON

FSD

16

DEN

DCLK

DHSDVS

PCLKM

SCLKN

REFCLK

SCK

SIOCMD

CFMCFMN

CTMCTMN

VREF-RDRAM

2V5_

D

3.3V

_D

GN

D

LAMPEN

DAD1000

026_DMD_DAD1000

3.3V_D

SCPCK

SCPDISCPDO

SCPENZ

SR16STROBE

SR16MODE1SR16MODE0

SR16SEL1SR16SEL0

SR16ADDR3SR16ADDR2SR16ADDR1SR16ADDR0

EXT-ARSTZ

SR16OEZ

IRQZ

V12_D

VCC2

MBRST[0:15]

DDP1000_DATA

025_DMD_DDP1000_DATA

DMDSER

DG

E[7

:0]

DR

E[7

:0]

DB

E[7

:0]

TRC-L

SCTRL-L

LOADB-LZ

DCLK-L

SACCLKSACBUS

DD[0:63]

GND

PAGE_16024_DMD_RAMBUS

CTMNCTM

RQ[0:7]

DQA[0:8]

DQB[0:8]

2V5_D

REFCLK

SCLKN

PCLKMD

RC

GP

DZ

SIOCMD

SCK

CFMCFMN

VREF-RDRAM

3.3V_D

GND

PAGE_13021_DMD_DDP1000

3.3V_D

2V5_D

SR16OEZ

SR16MODE1


SR16MODE0

SR16SEL1SR16SEL0

CKMTR1

FSD

16

PUM

-AR

STZ

EXT-ARSTZ

CWTACH

CWINDEX

SCL0SDA0

MOSC

BINSEL0BINSEL1

MTRSELZMTRCLK

MTRDATA

DRCGPDZ

SR16STROBE

FLA

SH

-BU

SY

Z

GND

COSC

SCPDISCPDOSCPCK

SCPENZ

IRQZ

ECO-MODE

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

LAMPLIT

RESETZ

LAMPEN

LAMPLITZ

Q4_C

SCL_FSCLSDA

LAMP-SYNC

SCL_F

FAN_P

SDA_F

SDA_F

LMAPLIT

3.3V

3.3V_D

RESETZ

LAMPEN

SDASCL

LAMPLITZ

GND

VDD

2V5_DECO-MODE

VDD_D

FAN_P

V12_D

3.3V

VDD_D 3.3V_D

3.3V

3.3V_D

VDD

3.3V

VDD

V12_D

VDD

VDD

VDD_D

2V5_D

LAMPLIT

LAMP-SYNC

SCL_FSDA_F

LAMP-SYNCLAMPLIT

SCL_FSDA_F

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

4 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

To repair lamp light detect signal from ballast before send to DDP1000 and main board.

L: Lamp onH: Lamp off


3.3V for main board

3.3V for DDP1000

LAMPLITZ connected to NPN collection pin and R6 change to 0 ohm

Generate 10mA and 0 mA to ballast lamp sync signal

OPEN


OPEN

OPEN

L: ECO-MODEH: Normal

C9

0.1U25V Z

J704

20D0049108

12345678

R12 2KQ6

MMBT2222A

1

32

TP243

R78310K

J702

20D0038108

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

G1

G1

G2

G2

TP241

RC310K

R711 270

TP250

+ C82810U M20V

12

TP247

UL174AHC1G08

1

2

3

4

5

RC410K

C8

0.1U25V Z

L71280 OHM

CP80.1U

R71M

Q706

2N3904

1

32

R11100

TP242

TP244

C8230.1U K

C8260.1U K

+ C722U25V

12

CP10.1U

U4LD1117-3.3V

GN

D1

VOUT 2VIN3

VO 4

+ C82010U M20V

12

U5274AHC1G08

1

2

3

4

5

TP248

TP251

U3LD1117-3.3V

GN

D1

VOUT 2VIN3

VO 4

L744

80 OHM

C8270.1U K

Q1MMBT2222A

1

3 2

TP245

UC2

PCA9515DP

NC1SCL02SDA03GND4

VCC 8SCL1 7SDA1 6

EN 5

L71080 OHM

L713

80 OHM

+ CP310U M6.3V

12

TP249

TP252

L71180 OHM

TP246

C8240.1U K

R734 0

TP240

+C82110U M

20V

12

R735 0

R5100KF

+ C82922U6.3V

12

L714

80 OHM

R78410K

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SCL0

SDA0

SCL

SAD

SCL

SDA

3.3V_D

SDA0SDA

SCL SCL0

GND

3.3V_D

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

5 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

SW1 is the switch to choice DDP1000 I2C would be connected with Pixelwork I2C or not. J2 is the connector to DDP1000 I2C download by DDP1000 composer.

OPEN

OPEN

J2

20L2021003123

R194.7K

TP14

R184.7K

R16 0

SW122401380011

12

23

3

44

55

66

TP15

R21 0

TP16

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

RAIN_C

GAIN_C

BAIN_C

HSYNC

DDC5V_2

BIN_2

RED_GND

LUMA

CHROMA

CVBS

RIN_2

GIN_2

PC_5VIN_2PC-RXD

PC-TXD

BLUE_GND

GREEN_GND

RXD

TXD

BAIN_C

RAIN_C

GAIN_C

VSYNC_C

CONTROL

VDD

3.3V

HSYNC

CVBS

LUMA

CHROMA

GND

VDD VDD

3.3V

3.3V

VDD VDD

VDD

VDD

VDD

VDD

VDD

PC-RXD

PC-TXD

PC-RXD

PC-TXD

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

6 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

73.07414.0J0

73.07414.0J0

OPEN

DN705

BAV99

1

3

2

DG702BAV99

1

3

2

R7053.3K

C803220P J

R841

4.7K

TP283

CG1

0.1U

UH702

74AHCT1G142 4

53 1

DG7 1N41481 2

TP19

U9

AT24C02N-10SI-2.7A0 1

A1 2

A2 3

GND 4

VCC8

WP7

SCL6

SDA5

U711A74LVC125A

2 3

1

14

7

DG

12TZ

MC

5V1

12

CG4

0.1U

DG1

BAV99

1

3

2

TP28

R8010

TP25

R7063.3K

DG8 1N41481 2

R911 0

TP22

C722220P J

DG

13TZ

MC

5V1

12

TP20

U711B74LVC125A

56

4

14

7

DN706

BAV99

1

3

2

RG22 0

RG8 4.7K

DG3

BAV99

1

3

2

CG7010.1U

TP29

TP229

TP284

RG4 75

C723220P J

DG703BAV99

1

3

2

TP23

R7962K

R8030

R7223.3K

CG3150P J

J821

2210021551

C 4

. 2

G2 G2

. 1

Y 3

G1

G1

G3

G3

TP24

J820

2210278001

2

1

G1

G2

CG2

470P K

RG6 75

TP17

RG3 75RG23 0

RG21 0

TP280

R797 1K

DG10 TZMC5V11 2

RG10 4.7K

R7213.3K

TP18

TP21

DG9 TZMC5V11 2

L92022014015

1728394105

11

12

13

14

15

6

G1

G2

DG

712

TZM

C5V

11

2RG7 75

R795 0

L721 BEAD

RG5 75

TP282

DG6 1N414812

L720BEAD

C822220P J

R910 0

DG701BAV99

1

3

2

RG11 4.7K

R842

4.7K

L722 BEAD

RG9 4.7KD

G71

3TZ

MC

5V1

12

UH2

74AHCT1G142 4

53 1

DG

11TZ

MC

5V1

12

TP27

R7982K

C804220P J

DG2 1N41481 2

DG4

BAV99

1

3

2

C721220P J

DG5 1N41481 2

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

RLUMLUMA

VY0VY1

XR

I

VY2

ITRI

VY3

AI11

VY4

SCL

AI1D

VY5VY6VY7

VVSVHS

AI2D

VPEN

AI3D

XTAL

SDA

V33

VY[7:0]

VCLK_A

LLC

2

VFILD

LLC

1

VUV7VUV6

LLC1LLC2

VUV5

AI4D

VUV4

AI21

VUV3

R CHR

VUV2

CVBS RCVBS AI23

VUV1

VCLK

DECOE

VUV0

VUV[7:0]

CHROMA

XTAL

I

BAIN_V

RAIN_V

GAIN_V

VDD

VUV[7:0]

SCLSDA

V33

VY[7:0]

VHSVVS

VPEN

CVBS

VCLK

VFILD

LLC1LLC2

LUMA

CHROMA

GAIN_V

BAIN_V

AVDD

GND

RAIN_V

V33

VDD VDD AVDD

V33

AVDD

V33

V33

AVDD AVDDAVDD AVDD AVDD AVDD AVDD AVDD AVDD

LLC

2LL

C1

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

7 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

OPEN

CA630.047U K

C92

310

P J

R53

56

CA690.047U K

CA700.047U K

CA710.047U K

CA650.047U K

CA48

0.1U

R55

56

R64 0

CA44

0.1U

CA58

0.1U

Y124.576MHZ

+ CA1922U25V

12

C4022P J

CA55

0.1U

CA51

0.1U

CA660.047U K

CA47

0.1U

C300

0.1U

CA46

0.1U

+CA68

22U25V

12

R54

56

R58 18

CA49

0.1U

CA59

0.1U

C301

0.1U

CA50

0.1U

CA720.047U K

CA53

0.1U

CA43

0.1U

CA54

0.1U

CA620.047U K

CA640.047U K

CA610.047U K

R56 18CA45

0.1U

CA57

0.1U

UA6 LD1117-3.3V

GN

D1

VOUT 2VIN3

VO 4

R60 4.7K

CA20

0.1U25V Z

C4122P J

CA60

0.1U

R57 18

C92

510

P J

CA52

0.1U

U13SAA7118E

FSWM13AI11J2AI12K1AI13K2AI14L3AI1DK3AGNDC2AI21G4AI22G3AI23H2AI24J3AI2DH1AI31E3AI32F2AI33F3AI34G1AI3DF1AGNDAL2AI41B1AI42D2AI43D1AI44E1AI4DD3EXMCLRP3AOUTM1VSSA0M2VSSA1J4VSSA2H3VSSA3E4VSSA4C1VDDA0M3VDDA1K4VDDA2H4VDDA3F4VDDA4D4VDDA1AL1VDDA2AJ1VDDA3AG2VDDA4AE2

VS

SD

2D

7V

SS

D4

D10

VS

SD

6F1

1V

SS

D8

J11

VS

SD

10L5

VS

SD

12L9

VD

DD

2C

8V

DD

D4

C10

VD

DD

6F1

2V

DD

D8

J12

VD

DD

10M

5V

DD

D12

M9

VS

SD

1D

5V

SS

D3

D9

VS

SD

5D

11V

SS

D7

G11

VS

SD

9L4

VS

SD

11L8

VS

SD

13L1

1V

DD

D1

C5

VD

DD

3C

9V

DD

D5

D12

VD

DD

7H

12V

DD

D9

M4

VD

DD

11M

8V

DD

D13

M11

VS

S(x

tal)

A4

VD

D(x

tal)

B3

XTO

UT

A2

XTA

LOA

3X

TALI

B4

AD

P8

P6

AD

P7

M6

AD

P6

L6A

DP

5N

7A

DP

4P

7A

DP

3L7

AD

P2

M7

AD

P1

P8

ADP0 N8CLKEXT N6IPD7 K11IPD6 J13IPD5 J14IPD4 H13IPD3 H14IPD2 H11IPD1 G12IPD0 G14ICLK M14IDQ L13ITRDY N12IGPH K12IGPV K14IGP0 L14IGP1 K13ITRI L12HPD7 G13HPD6 F14HPD5 F13HPD4 E14HPD3 E12HPD2 E13HPD1 E11HPD0 D14

XPD6 A11XPD5 B10XPD4 A10XPD3 B9XPD2 A9XPD1 B8XPD0 A8XCLK A7XDQ B7XRDY A6XRH C7XRV D8

XTR

IB

11LL

CP

4LL

C2

N5

RTS

0M

10R

TS1

N10

RTC

OL1

0R

ES

P5

CE

N4

INT_

AP

9S

CL

N9

SD

AP

10A

SC

LKN

11A

LRC

LKP

12A

MC

LKP

11

TES

T1A

12TE

ST2

A13

TES

T3B

2TE

ST4

B12

TES

T5B

13TE

ST6

B14

TES

T7C

3TE

ST8

C4

TES

T9C

12TE

ST1

0C

13TE

ST1

1C

14TE

ST1

2D

13TE

ST1

3N

1TE

ST1

4N

2TE

ST1

5N

3TE

ST1

6N

13TE

ST1

7N

14TE

ST1

8P

2TE

ST1

9P

13

AMXC

LKM

12

TMS

D6

TCK

B6

TRS

TC

6TD

IB

5TD

OA

5

XPD7 C11

U12LD1117-3.3V

GN

D1

VOUT 2VIN3

VO 4

C92

410

P J

R6310K

R61 4.7K

CA670.047U K

CA56

0.1U

R59

10K

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

GBE2

GGE3

AVDD_AD

AD

RE

1

GBIN

AVDD_AD

GRE2

GVS

ADGE1

GBIN_A

GBE6GBE7

GRE7

AD

RE

2

AD

SO

G

GRIN

ADBE5

ADGE0

GGE[7:0]

SDA

GBE5

AD

RE

7

ADGE5

AVDD_AD

GRE4A

DR

E4

ADBE3

V33

GBE4

GCOAST

GBE0

AD

VS

GGINGAIN_C

VSYNC_C

GGE6

GGE0

AD

RE

0

ADBE1

ADGE3

ADGE7

GVMID

GRE6

GBE1

GRE3

PVDD

AD

RE

3

ADBE4

AD

RE

6

AD

HS

GGIN_A

GGE2

ADBE6

ADGE4

PVDD

GRE5

AVDD_AD

GGE5

GGE7

GBE3

GGE1

GGE4

GRIN_A

GBLKSPL

GRE1A

DR

E5

AVDD_AD

ADBE7

ADGE2

GHS

GRE[7:0]

ADGE6

RAIN_C

BAIN_C

GBE[7:0]

GVREF

ADBE2

GRE0

SCL

ADBE0

BAIN_VAVDD_AD

RAIN_V

GAIN_V

AD

CK

GFBK

AVDD

GAIN_C

RAIN_C

BAIN_C

PVDD

GFILT

REF_A

GVS

SDA

GBE[7:0]

VDD

GRE[7:0]

SCL

GND

GHS

GGE[7:0]

GBLKSPLGCOASTHSYNC

GAIN_V

VSYNC_C

RAIN_C

GAIN_C

BAIN_C

BAIN_V

RAIN_V

V33

GCLKGFBK

AVDD

VDD PVDD

V33V33

AVDD_AD

AVDD_AD

V33

PVDD

AVDD_AD

V33

AVDD_AD

AVDD_AD

V33

AVDD_AD

AVDD_AD

AVDD AVDD_AD

PVDD

SOGIN

GAIN_C

BAIN_C

RAIN_C

GAIN_C SOGIN

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

8 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

77.62203.0C177.62203.0C1

77.62203.0C1

77.62203.0C1

77.62203.0C1

77.62203.0C1

77.62203.0C1

68.00173.0F1

For Batman DVD noise solution

OPEN

OPEN

OPEN

OPENOPEN

OPENOPEN

OPEN

OPEN

OPEN

OPEN

CB82

0.1U

C61

0.1U25V Z

R860

0

R876 22

CB83

0.1U

CN

7 33P8

1

72

63

54

+ C85010U16V

12

RN1147

1234

8765

CN

3 33P8

1

72

63

54

RN9

47

1234

8765

C90

115

P K

C63

0.1U

R877 22

RD1 1.5K

CA79

0.1U

CB81

0.1U

C800.047U K

C883 1.8P J

C90

315

P K

C573

39N K

CB84

0.1U

RN10471234

8765

C51

0.1U

C65

0.1UR47 47

R812 22

CN

6 33P8

1

72

63

54

CN533P

81

72

63

54

R792 330

C81

0.1U

C54

0.1U

C55

0.1U

RN8 47

1234

8765

C53

0.1U

RN6 47

1234

8765

C68

0.1U

C56

0.1U

C52

0.1U

C790.047U K

UB16 LD1117-3.3V

GN

D1

VOUT 2VIN3

VO 4

C574

3900P K

CN

8 33P8

1

72

63

54

CN

2 33P8

1

72

63

54

RD23K

U15AD9883AKST-140

GND 1G7 2G6 3G5 4G4 5G3 6G2 7G1 8G0 9GND 10VDD 11B7 12B6 13B5 14B4 15B3 16B2 17B1 18B0 19GND 20GN

D21

VD

D22

VD

D23

GN

D24

GN

D25

VD

26V

D27

GN

D28

CO

AS

T29

HSY

NC

30V

SY

NC

31G

ND

32FI

LT33

PV

D34

PV

D35

GN

D36

MID

SC

V37

CLA

MP

38V

D39

GN

D40

GND41VD42BAIN43GND44VD45VD46GND47GAIN48SOGIN49GND50VD51VD52GND53RAIN54A055SCL56SDA57REF BYPASS58VD59GND60

GN

D61

VD

62G

ND

63V

SO

UT

64S

OG

OU

T65

HS

OU

T66

DA

TAC

K67

GN

D68

VD

D69

R7

70R

671

R5

72R

473

R3

74R

275

R1

76R

077

VD

D78

VD

D79

GN

D80

C66

0.1U

R793 330

C80233P J

LD1 80 OHM

C62

0.1U

C64

0.1U

RN1247

1234

8765R791 330

+ C83510U16V

12

C882 1.8P JR875 22

C884 1.8P J

C780.047U K

R565

3.3K

C90

215

P K

C671000P K

+C77

22U25V

12

CD110P J

CA80

0.1U

RN7 47

1234

8765

CN433P

81

72

63

54

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

D[0:15]

ROMOEnROMWEn

ROMOEn

ROMWPn

ROMWEn

VPP

VPPENVP1

3.3V

VP3

VP2

VPPON

A5A4

A14

A10

A5

A6

A15

A3A4

A11

A2

A19

A12

A16

A9

A9

A8A7

A13

A1

A14

A2

A17

A15

A16

A18A19

A3

A18

A1

A10

A12

A6

A11

A7

A17

A13

A8

A[19:1]

SCLD3

D1

D12

D0

D0

D14

D15

D9

D2

D2

D12D13

D5

D13

D4

D15

D10

D1

D6

D4

D10

D9

D14

D8

D11

D7

D7D8

D6

D3

D11

D5

FCEn

A0

ROMWEn

RESETn

RESET

BHENn

ICEn

SDA

D[0:15]

ROMWEnROMOEn

GND

ROMOEn

3.3V

ROMWEn

VPPEN

A[19:1]

SCLSDA

A0

BHENn

RESET

RESETn

VDD

VDD3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

ROMWEn

RESETn

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

9 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

PIXELWORKS SDK FOR TOSHIBA

OPEN

OPEN

U17

AT49BV8192A(T)

VCC 37

VPP 13

GND 46GND 27

D1 29

D9 30

D2 31

D10 32

D3 33

D11 34

D4 35

D12 36

D5 38

D13 39

D6 40

D14 41

D7 42

D15 43

D8 44

D16 45

A151 A142 A133 A124 A115 A106 A97 A88

A1717

A718 A619 A520 A421 A322 A223 A124 A025

A1648

CE26OE28WE11RP12WP14BYTE47

A1816

R903.3K

SW3

6240019001

12

43

RB110K

RA303.3K

CA30220P

R98 3.3K

RB2 47

UI574V1G14S

2 4

53

1

C330

220P K

UI3

74AHC1G32

A 1

B 2

GND 3

VCC5

Y4

JP1

20L2055050

1122334455667788991010111112121313141415151616171718181919202021212222232324242525

26 2627 2728 2829 2930 3031 3132 3233 3334 3435 3536 3637 3738 3839 3940 4041 4142 4243 4344 4445 4546 4647 4748 4849 4950 50

R86

1K

UI4

NCP302LSN31T1

CD5

NC4

VCC2

RESET 1

GND 3

CP50.1U

25V Z

Q102N39063 2

1

CI10.1U

C305

0.1UR871K

R330 1K

R88 1M

CP4

0.1U25V Z

Q112N3904

1

32 R89

10K

C90

0.1U

UI1

74V1G14S

2 4

53

1

U21

AT24C16N-10SI-1.8

A01

A12

A23

GND4

VCC 8

WP 7

SCL 6

SDA 5

C940.1U25V Z

R99 3.3K

UI2

74AHC1G32

A 1

B 2

GND 3

VCC5

Y4

RB3 47

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

VUV7

VUV2

VY6VY5

VY1

VUV6

VUV1

VUV5

VUV0

VY0

VUV4

VY4

VY7

VUV3

VY3VY2

GBE5

GGE1

GGE6

GBE1

GBE3

GGE4

GBE0

GRE1

GRE5

GGE0

GRE0

GGE3

GRE6

GGE2

GBE6

GRE7

GBE2

GRE2

GGE5

GBE7

GGE7

GRE4

GBE4

GRE3

RBE5

R DH

DRE7

RDV

DRE5

RBE7

RBE4

RRE1DRE2

RDK

DRE6

DRE3

RRE7

DRE1RRE2

DRE4

RDE

RRE6

RRE4

DRE0

RRE5

RBE6

RRE0

RRE3

AUDIO_VOL

POWERONRESETZ

DRO0DRO1DRO2DRO3DRO4DRO5DRO6DRO7

DGO0DGO1DGO2DGO3DGO4DGO5DGO6DGO7

DBO0DBO1DBO2DBO3DBO4DBO5DBO6DBO7

DBE5DBE6

DBE4

RBE0

RBE3RBE2 DBE2

DBE0

DBE7

DBE1

DBE3

RBE1

LAMPLITZ

X702

AUDIO_MUTA

RAMOEn

D10

A12A11

A9

D7

D1

A19

A13

DCKEXT

CS0n

D14

D3

D8

X704

TXD

D6

A18

WRn

D15

A5MCKEXT

A8X700X700

SDA

D12

A4

A2

D11

D9

D0

A15

A7

A1

D5

RAMWEn

D2

A16

A14

A6

RXD

SCL

D4

X701X701

X703

A17

A10

AUDIO_VOLA

IRRCVR

RESET

D13

A3

AUDIO_MUT

VPPEN

RGE0

RGE3

RGE1RGE2

DGE3

DGE7

DGE4RGE5

RGE7

DGE1DGE2

DGE6

DGE0

DGE5RGE6

RGE4

U16_A

CONTROL

VCLK

VFIELD

VVSVHS

VPEN

VY[7:0]

GGE[7:0]

GRE[7:0]

GVSGBLKSPLGHS

GFBK

GCLK

GBE[7:0]

GCOAST

TDO

TXD

ROMWEn

TCK

RXD

MCKEXT

ROMOEn

IRRCVR

TMS

A[19:1]

DCKEXT

RESET

D[0:15]

SDA

DVSDHS

DRE[7:0]

DCLK

DGE[7:0]

DBE[7:0]

A0

BHENn

DEN

VUV[7:0]

RESETZ

DRO[7:0]

DGO[7:0]

DBO[7:0]

SCLAUDIO_VOL

3.3V

CS0n

LAMPLITZ

GND

POWERON

AUDIO_MUT

ECO-MODE

KEYSTONE

CS1n

VPPEN

FAN_P

VDD

CONTROL

KEY8

V25

V25

V25 V25V25

V25 V25

V25V25

V25V25

V25 V25

V25

V3P

V3PV3P

V3P

V3P V3P

V3P

V3P

V3P

V3PV3P

3.3V

V3P

3.3V

3.3VV25

V3P

V25

V25P

V25

V25VDD

KEYSTONE

KEYSTONE

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

10 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

For 164B 10TK

OPEN

R105 0

C116

0.1U

C103

0.1U

+ C60322U25V

12

Power and GroundU22EPW166-10TK

GN

D1

D4

GN

D2

D7

GN

D3

D10

GN

D4

B11

GN

D5

A12

GN

D6

D14

GN

D7

D17

GN

D8

G17

GN

D9

K17

GN

D10

P17

GN

D11

T19

GN

D12

U17

GN

D13

W17

GN

D14

U14

GN

D15

W14

GN

D16

U12

GN

D17

U11

GN

D18

U9

GN

D19

U7

GN

D20

W6

GN

D21

W4

GN

D22

U4

GN

D23

L4G

ND

24K

4G

ND

25G

4

VD

D1

C7

VD

D2

C18

VD

D3

U20

VD

D4

V18

VD

D5

Y17

VD

D6

V12

VD

D7

V9

VD

D8

Y6

VD

D9

V3

VD

D10

K3

VC

C5

C14

VC

C1

C3

VC

C2

C10

VC

C3

C11

VC

C4

B12

VC

C6

G18

VC

C7

K18

VC

C8

P18

VC

C9

V14

VC

C10

Y14

VC

C11

V11

VC

C12

V7

VC

C13

L3V

CC

14G

3

TP5

RN19 47

1234

8765

RW703 2K

C112

0.1U

C970.1U

R106 0

C601

4.7U Z

C104

0.1U

RD4 0

C114

0.1U

C980.1U

C105

0.1U

Video Port

U22B

PW166-10TK

VY0D8VY1C8VY2B7VY3A7VY4B8VY5D9VY6C9VY7A8

VUV0B9VUV1A9VUV2B10VUV3A10VUV4D11VUV5A11VUV6C12VUV7B13

VCLKD12

VPENC13

VVSA14

VFIELDA15 VHSB14

C119

0.1U

C110

0.1U

C113

0.1U

R602 2K

C111

0.1U

RN18 47

1234

8765

RD5 0

C99

0.1U

C117

0.1U

R1022K

Misc

U22D

PW166-10TK

A0 P1A1 P2A2 N3A3 N4A4 R1A5 R2A6 T1A7 T2A8 R3A9 U1

A10 U2A11 R4A12 T3A13 V1A14 W1A15 V2A16 T4A17 U3A18 Y1A19 W2

D0 F4D1 F3D2 E1D3 F2D4 F1D5 G2D6 G1D7 H1D8 H4D9 H3

D10 H2D11 J1D12 J2D13 J4D14 J3D15 K1

RD M3WR M4

BHEN N2ROMOE M1ROMWE L2RAMOE L1RAMWE K2

CS0 M2CS1 N1

EXTINT E2

NMI D1

RESETE3

MCKEXTW13DCKEXTY13

TXDD3

IRRCVR0E4IRRCVR1D2

PORTA0C2PORTA1B1PORTA2B2PORTA3A1PORTA4C4PORTA5D5PORTA6B3PORTA7A2

PORTB0A3PORTB1C5PORTB2D6PORTB3B4PORTB4A4PORTB5C6PORTB6B5PORTB7A5

MODE2B6

CPUTCKA6

CPUTDOW3

MODE0A13

RXDC1

MODE1U5

CPUTMSD13

XTALIP3XTALOP4

RX21M F

R334 47

Graphics Port

U22A

PW166-10TK

GRE0M20GRE1N19GRE2N18GRE3N17GRE4N20GRE5P20GRE6P19GRE7R20

GGE0F18GGE1E19GGE2E20GGE3J18GGE4H20GGE5J19GGE6J20GGE7K19

GBE0D16GBE1A18GBE2C17GBE3B18GBE4A19GBE5B19GBE6A20GBE7D18

GRO0K20GRO1L17GRO2L18GRO3L19GRO4L20GRO5M18GRO6M17GRO7M19

GGO0E17GGO1C19GGO2B20GGO3C20GGO4E18GGO5F17GGO6D19GGO7D20

GBO0B15GBO1A16GBO2C15GBO3D15GBO4B16GBO5A17GBO6C16GBO7B17

GCLKH19GPENSOGG20GVSJ17GHSG19 GREF H18

GBLKSPL F19GCOAST F20

GFBK H17

U61

LM317M

GN

D1

VOUT 2VIN3

RK6 0

C101

0.1U

RN21 47

1234

8765

+ C9510U M6.3V

12

R103 47

L13BEAD

C106

0.1U

R6032K

C120

0.1U

TP4

R1012K

R107 0

RX11M F

C115

0.1U

RN23

471234

8765

RN25

471234

8765

R1081K

C108

0.1U

RN2247

1234

8765

C118

0.1U

RN20471234

8765

R104 2K

R808 47

+C96

10U M6.3V

12

Display Port

U22C

PW166-10TK

DRE0 R19DRE1 T20DRE2 R18DRE3 R17DRE4 T18DRE5 U19DRE6 T17DRE7 V20

DGE0 U18DGE1 V19DGE2 W20DGE3 W19DGE4 Y20DGE5 V17DGE6 U16DGE7 W18

DBE0 Y19DBE1 Y18DBE2 V16DBE3 U15DBE4 Y16DBE5 V15DBE6 W16DBE7 W15

DRO0 Y12DRO1 W11DRO2 Y11DRO3 U10DRO4 V10DRO5 W10DRO6 Y10DRO7 W9

DGO0 Y9DGO1 W8DGO2 V8DGO3 U8DGO4 Y8DGO5 Y7DGO6 W7DGO7 Y5

DBO0 V6DBO1 U6DBO2 W5DBO3 Y4DBO4 V5DBO5 Y3DBO6 V4DBO7 Y2

DCLK W12DVS V13DHS U13

DEN Y15

RN24 471234

8765

C100

0.1U

C102

0.1U

C109

0.1U

RN26 47

1234

8765

TP6

C107

0.1U

R10927

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DCKEXT U24_X1U24_X2

RMCK MCKEXT

U25_X1

POWERON

U25_X2

RDCK

POWERON

DCKEXT

MCKEXT

3.3V

GND

KEYSTONE

VDD

SDA

SCL

3.3V

3.3V

3.3V

3.3V

3.3V

VDD

VDD

3.3V

VDD

3.3V

KEYSTON_A

KEYSTON_A

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

11 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

65MHz

130MHz/41MHz

Note: keystone function IC and thermal senser IC, those two component should be placement as closed as possible.

S01 version I2C bus reversed and Pin8 connected to VDD new version change to 3.3V

MEMSIC: R93, C91, R94, R95, R92, RK1, OPEN; RK2, RK3, RK4 0ohmADI: RK1, RK2, RK3, RK4, R92 OPEN

OPEN

OPEN

68.00129.0D1

68.00129.0D1

RK8 0

R115

820K

R114820K

U19

XFILT7

YFILT6

ST1

T22

VDD8

COM3

XOUT 5

YOUT 4

C12310P D

C1210.1U

RK5 OPEN

CP6

0.1U25V Z

RK94.7K

RK3 OPEN

C890.1U

RK2 OPEN

U18 G751-2

A25

A16

A07

VCC 8

SDA 1

SCL 2

O.S. 3

GN

D4

L29 Z10C12410P D

U20

74AHC1G08

1

2

3

4

5

C125

10P D

Y3

16.257MHZ

R92 OPEN

C92

470N M

R113 22

U25

ICS501

X11X28

CLK 5S06S14

OE7 VDD 2

GND 3

RK1 0

R95

680K

L28 Z10

RK7 0

CK1 0.1U

Y216.257MHZ

C126

10P D

C1220.1U

R93 0

R112 22

C91

470N M

RK4 OPEN

R944.7K

C93

0.1U

U24

ICS501

X11X28

CLK 5S06S14

OE7 VDD 2

GND 3

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CS0n

D2

D4

D7

D5

D3

D0 D0D1

D3

D5

D7

D4

D6

D2D1

D[0:7]

D6

D[0:7]

IRRCVRIRRCVR1

IROUTIRVCC

LED5LED4

LED0

LED3LED2LED1

KEY8

KEY[7:0]

LED3LED2LED1LED0

LED4

KEY4

KEY7

KEY0

KEY4

KEY1

KEY6

KEY3KEY2

KEY0

KEY6

KEY5

KEY7

KEY5

KEY3KEY2KEY1

LED5

IRRCVR2IRVCC

IROUT

D[0:7]

CS0n

3.3V

CS1n

GND

RESETn

D[0:7]

IRRCVR

VDD

KEY8

VDD

3.3V3.3V

VDD

VDD

VDD

VDD

KEY[7:0]

KEY[7:0]

LED[5:0]

LED[5:0]

IRRCVR1

IRRCVR2

IRRCVR1

IRRCVR2

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

12 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

In version 2 PCB the power for this block is VDD_D but it is floating. I version 3 schematic we change to VDD net for this block power source.

IR receiver circuit

77.62203.0C1

77.62203.0C1 77.62203.0C1

OPEN

RN725 120 OHM12345

678

U27

74AHC244

1A121A241A361A482A1112A2132A3152A417

1G12G19

1Y1 181Y2 161Y3 141Y4 122Y1 92Y2 72Y3 52Y4 3

VC

C20

GN

D10

C1270.1U

R813

0

TP232

R7440

R957 0

TP34

CN

7014

70P

81

72

63

54

C812

0.1U

TP948

C801470P K

R2210K

C811 0.1U

U7

74AHC1G08

1

2

3

4

5

CN

703

470P 8

1

72

63

54

L802240 OHM

L801240 OHM

J4 20L2021020

1234567891011121314151617181920

TP44

TP949

TP233

TP41

R23 510

R958 0

TP35

U28

74LVC273CLR1 G

ND

10

CLK11

VC

C20

Q1 2Q2 5Q3 6Q4 9Q5 12Q6 15Q7 16Q8 19

D13D24D37D48D513D614D717D818

RN726 120 OHM12345

678

R857 0J813

20L2021004

1234TP37

C12

4.7U Z

CN

704

470P

81

72

63

54

CN

702

470P

81

72

63

54

TP45

TP47

R15 47

TP39

R7450

U6FM-6038LM-5A

OU

T1

GN

D2

VS

3

TP42

TP46

C81

647

0P K

RN727 120 OHM

12345

678

TP36

TP48

TP231

J913

20D0049103

123

R858 0

C81

5

470P KTP38RN728 120 OHM

12345

678

TP801

TP40

TP49

TP947

TP43

CP70.1U

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CRYSTALENPLL-VCCA

SR16OEZSR16STROBE

SR16ADDR2SR16ADDR3

SR16MODE1

SR16ADDR1SR16ADDR0

SR16SEL0SR16SEL1

FSD16

CWINDEXCWTACH

CKMTR1

COSC

SR16MODE0

EXT-ARSTZ

D RCGPDZ

PUM-ARSTZ

MTRDATA

MTRSELZMTRCLK

FLASH-BUSYZ

MOSC

SCL0

BINSEL1BINSEL0

SDA0

S CPENZ

SCP DIS CPDOSCPCK

ECO-MODE

IR QZ

CKMTR1

FSD16

PUM-ARSTZEXT-ARSTZ

SCL0SDA0

MOSC

BINSEL0BINSEL1

DRCGPDZ

SR16STROBE

FLASH-BUSYZ

GND

CWINDEX

MTRDATAMTRCLKMTRSELZ

3.3V_D2V5_D

CWTACH

SR16OEZ

SR16MODE1


SR16MODE0

SR16SEL1SR16SEL0

COSC

SCPENZ

SCPDISCPDOSCPCK

IRQZ

ECO-MODE

2V5_D

3.3V_D2V5_D

3.3V_D

2V5_D

2V5_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D

2V5_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D

2V5_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D

2V5_D 2V5_D

3.3V_D3.3V_D

3.3V_D

3.3V_D

3.3V_D

3.3V_D

3.3V_D

3.3V_D

3.3V_D

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

13 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

R124 MOSC Configuration

Install Crstal

Non Install Oscillator

P3P3V:AB21,AB20,AB19,AB8,AB7,AB6,AA22,AA5,Y22,Y5,W22,W5,H22,H5,G22,G5,F22,F5GND:AF26,AF25,AF21,AF16,AF15,AF11,AF6,AF1,AE25AE2,AE1,AD24,AD3,AC23,AC4,AB22,AB18GND:AB14,AB13,AB9,AB5,AA26,AA1,V22,V5,T26,T2,T1,P22,P5,N22,N5,L26,L1,J22,J5,F26GND:F1,E22,E18,E14,E13,E9,E5,D23,D18,D16,D14,D12,D10,D6,D4,C24,C18,C17,C14,C11GND:C8,C6,C5,C3,B26,B25,B19,B17,B14,B13,B11,B9,B8,B7,B5,B2,A26,A21,A16,A11,A6,A2,A1P2P5V:AC2,AB17,AB16,AB15,AB12,AB11,AB10,U22,U5,T22,T5,R22,R5,R1,M22,M5,L22,L5P2P5V:K22,K5,E21,E20,E19,E17,E16,E15,E12,E11,E10,E8,E7,E6,B15,GND:P11,P12,P13,P14,P15,P16,N11,N12,N13,N14,N15,N16,T11,T12,T13,T14,T15,T16,GND:R11,R12,R13,R14,R15,R16,M11,M12,M13,M14,M15,M16,L11,L12,L13,L14,L15,L16,A10,A15

DDP1000 DECOUPLING FOR +3.3VDDP1000 BULK DECOUPLING CAPS DDP1000 DECOUPLING FOR+2.5V

Extra test point request by TI and optical team phase-in at LP2stage.

OPEN

R12010K

C1480.1U

C1330.1U

C1420.1U

+ C14610U M6.3V

12

C1510.1U

TP321

C1390.1U

R12210K

+ C13610U M6.3V

12

U29E

DDP1000-C

P3P3V AB21P3P3V AB20P3P3V AB19P3P3V AB8P3P3V AB7P3P3V AB6P3P3V AA22P3P3V AA5P3P3V Y22P3P3V Y5P3P3V W22P3P3V W5P3P3V H22P3P3V H5P3P3V G22P3P3V G5P3P3V F22P3P3V F5

P2P5VAC2P2P5VAB17P2P5VAB16P2P5VAB15P2P5VAB12P2P5VAB11P2P5VAB10P2P5VU22P2P5VU5P2P5VT22P2P5VT5P2P5VR22P2P5VR5P2P5VR1P2P5VM22P2P5VM5P2P5VL22P2P5VL5P2P5VK22P2P5VK5P2P5VE21P2P5VE20P2P5VE19P2P5VE17P2P5VE16P2P5VE15P2P5VE12P2P5VE11P2P5VE10P2P5VE8P2P5VE7P2P5VE6P2P5VB15

GND AF26GND AF25GND AF21GND AF16GND AF15GND AF11GND AF6GND AF1GND AE25GND AE2GND AE1GND AD24GND AD3GND AC23GND AC4

GND P5GND N22GND N5GND L26GND L1GND J22GND J5GND F26GND F1GND E22GND E18GND E14GND E13GND E9GND E5GND D23

GND D18GND D16GND D14GND D12GND D10GND D6GND D4GND C24GND C18GND C17GND C14GND C11GND C8GND C6

GNDAB22GNDAB18GNDAB14GNDAB13GNDAB9GNDAB5GNDAA26GNDAA1GNDV22GNDV5GNDT26GNDT2GNDT1GNDP22

GNDB26GNDB25GNDB19GNDB17GNDB14GNDB13GNDB11GNDB9GNDB8

GNDB5GNDB2GNDA26GNDA21GNDA16GNDA11GNDA6GNDA2GNDA1

GND C5GND C3

GNDP11GNDP12

GNDP14GNDP15GNDP16GNDN11

GNDP13

GNDN12GNDN13GNDN14GNDN15GNDN16GNDT11GNDT12GNDT13GNDT14GNDT15

GND R11GND R12GND R13GND R14GND R15GND R16GND M11GND M12GND M13GND M14GND M15

GND L11GND L12GND L13GND L14

GND M16

GND L15GND L16GNDT16

GNDA10GNDA15

GNDB7

C1320.1U

R733 0

TP311

C1340.1U

C1430.1U

R490 47

C1520.1U

TP301

C1470.1U

L14120 OHM

C1400.1U

C1570.1U

C1490.1U

C1300.1U

R12110K

C1550.1U

+ C13710U M6.3V

12

C1350.1U

C1440.1U

C1530.1U

C1280.1U

U29D

DDP1000-C

DIO0R24DIO1R23DIO2P23DIO3R25DIO4T24DIO5T23DIO6U26DIO7T25DIO8U24DIO9V26DIO10U23DIO11U25DIO12V24DIO13W26DIO14V25DIO15V23DIO16W24DIO17Y26DIO18W25DIO19W23DIO20Y24DIO21Y25DIO22AB26DIO23Y23

APLLMD1AB23APLLMD0AC24MOSCNF2MOSCF3COSCAD25PLL_VCCAAE26CRYSTALENG4

USBCLKJ1USBDATPAE19USBDATNAC19SDA0AC22SCL0AE24

DIO24 AA24DIO25 AA25DIO26 AC26DIO27 AA23DIO28 AB25DIO29 AC25DIO30 AD26DIO31 AB24

OCLKA D2OCLKB E3

VSOUTZ P26FSD16 N24

DMDLD M3DCLKREF N2

PUM_ARSTZ D1EXT_ARSTZ F4

EXT_ARST E2

TSTPNT3 B23TSTPNT2 B22TSTPNT1 D21TSTPNT0 A23

SR16VCCEN L3DMDVCCEN L4

VCC2EN K1VBIASEN K3VRSTEN L2

DMDBIN3 E4DMDBIN2 B1DMDBIN1 C2DMDBIN0 D3

SR16STRB H1SR16OEZ J3

SR16ADDR3 G1SR16ADDR2 H3SR16ADDR1 J4SR16ADDR0 J2SR16MODE1 H4SR16MODE0 H2

SR16SEL1 K2SR16SEL0 K4

C1560.1U

C1380.1U

TP331

C1580.1U

C1410.1U

R5330

C1500.1U

C1450.1U

R124OPEN

R542OPEN

C1540.1U

C1310.1U

C1290.1U

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

LAMPLITZLAMPEN

RQ7RQ6

RQ4RQ5

RQ1RQ2RQ3

DQA6DQA7

RQ0

DQA8

DQA2

DQA4DQA5

DQA3

DQB8

DQA1

DQB5DQB6

DQB4

DQB2DQB3

DQB1DQB0

DQA0

RQ[0:7]

DQA[0:8]

DQB[0:8]

SCK

SIOCMD

CFMCFMNCTMCTMN

U5-D20U5-B21

TMS1

TDO2

TD1

TDO1

FLASH-BUSYZ

PUM-ARSTZ

DVSDHS

DENDCLK

FSD16

RESETZPOWERON

FLADDR19

FLADDR16FLADDR17FLADDR18


FLADDR12

FLADDR10FLADDR11

FLADDR9FLADDR8FLADDR7FLADDR6

FLADDR4FLADDR3

FLADDR5


FL-OEZFL-WEZFL-CSZ

FLDATA15

FLDATA12

FLDATA14FLDATA13

FLDATA8

FLDATA10FLDATA11

FLDATA9

FLDATA7FLDATA6FLDATA5

FLDATA2FLDATA3FLDATA4

FLDATA0

FLDATA1FLDATA0

FLDATA2FLDATA3

FLDATA1

FLDATA5

FLDATA11

FLDATA6FLDATA7

FLDATA4

FLDATA8

FLDATA14

FLDATA9FLDATA10

FLDATA15

FLDATA13FLDATA12

FLDATA[0:15]

TRSTZ

U5-C21

TMS2

ICTSENZ

TCK

DQB7

RQ[0:7]

DQB[0:8]

DQA[0:8]

GND

FLASH-BUSYZ

RESETZPOWERON

FSD16

DENDCLKDHSDVS

PCLKMSCLKNREFCLK

CTMCTMN

SCK

SIOCMD

CFMCFMN

VREF-RDRAM

2V5_D

LAMPLITZLAMPEN

3.3V_D

PUM-ARSTZ

3.3V_D

3.3V_D

3.3V_D

2V5_D

VREF-RDRAM

3.3V_D

3.3V_D

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

14 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

FLASH +3.3V DECOUPLING CAPS

GND:H6,H1P3P3V:G4NC:C4,B3,D3

TP10 1

U30

AM29LV800BB-120

RY/BY A3

DG0 E2DG1 H2DG2 E3DG3 H3DG4 H4DG5 E4DG6 H5DG7 E5DG8 F2DG9 G2DG10 F3DG11 G3DG12 F4DG13 G5DG14 F5DQ15/A-1 G6

A0E1 A1D1 A2C1 A3A1 A4B1 A5D2 A6C2 A7A2 A8B5 A9A5 A10C5 A11D5 A12B6 A13A6 A14C6 A15D6 A16E6 A17B2 A18C3 A19D4

RESETB4

BYTEF6

OEG1WEA4CEF1

GND H6GND H1

VDD G4

NC C4NC D3NC B3

TP11 1

C1610.1U

R126 47

TP12 1

R131 39.2F

C1590.1U K

R130 10K

TP13 1

R125 110F

C1620.1U

R127 47

TP9 1

R129 10K

R133 39.2F

C16368P J R128 10K

RAMBUS, JTAG, CUSTOMER INPUT

U29B

DDP1000-C

VSYNCZR26HSYNCZN25WCLKN23IVALIDM23OLACTM24SYNCVALID2/DI2E23CTRLN26FLDSYNCM26LAMPSTATP25LAMPCTRLP24

PWRGOODE1SYSRSTZG3

RD_VREF1D9RD_VREF0D11RD_AVDD0B12RD_AVDD1B10

TDO2C1TMS2C23TDO1M4TMS1B24TDIC22TRSTZD5TCKC4

PTSTENZB3ICTSENZA24IBMT_RIAF2IBMT_LTAD2POSTSTK25LSSDEND19

RQ0 D15RQ1 C15RQ2 A14RQ3 C13RQ4 A13RQ5 A12RQ6 C12RQ7 D13

DQA0 A7DQA1 D8DQA2 C7DQA3 A5DQA4 D7DQA5 B6DQA6 A4DQA7 B4DQA8 A3

DQB0 C16DQB1 A17DQB2 B16DQB3 A18DQB4 D17DQB5 A19DQB6 B18DQB7 C19DQB8 A20

RD_SCK A22RD_CMD B20RD_SIO C20

RD_CFM A8RD_CFMN C9

RD_CTM C10RD_CTMN A9

PCLKM C21SCLKN B21

REFCLK D20

C1600.1U

FLASH INTERFACE

U29A

DDP1000-C

FLDATA0AE23FLDATA1AE22FLDATA2AC21FLDATA3AF23FLDATA4AE21FLDATA5AD21FLDATA6AC20FLDATA7AF22FLDATA8AE20FLDATA9AD20FLDATA10AF20FLDATA11AD19FLDATA12AC18FLDATA13AE18FLDATA14AF19FLDATA15AD18

FLADDR0 AE17FLADDR1 AC17FLADDR2 AF18FLADDR3 AD17FLADDR4 AE16FLADDR5 AF17FLADDR6 AC16FLADDR7 AD16FLADDR8 AE15FLADDR9 AC14FLADDR10 AD15FLADDR11 AC15FLADDR12 AE14FLADDR13 AF14FLADDR14 AD13FLADDR15 AD14FLADDR16 AF13FLADDR17 AF12FLADDR18 AE13FLADDR19 AD12

FL_OE AD23FL_WE AD22FL_CS AF24

R132 39.2F

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

2.5VREFSENSER_A

CWINDEXCK100M MOSC

CWINDEXA

CWINDEXA

CWSENSOR

OPDIODE

COSCCK60M

3P3V

3P3V

3P3V

3.3V_D

VDD_D

CWINDEXMOSC

GND

COSC

VDD_D

VDD_D3.3V_D

3.3V_D

3.3V_D

CWINDEXA

CWINDEXA

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

15 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

68.00129.0D1

OPEN

open

C16610P J

TP53

TP55

L27 Z10

UY1

ICS501

X11X28

CLK 5S06S14

OE7 VDD 2

GND 3

US2

74AHC1G32

A1

B2

GND3

VCC 5

Y 4

C16710P J

Y520MHZ

C9210.1U

C930 27P J

RS110K

TP54

R91

8

0

R92

0

0

RS26.8K

C1700.1U

R51

8

0

C926

10P J

RS72K

C909

4.7u

RS5180

C910 27P J

Y901

30MHZ

1

3

2

4

C49322P J

RS410K

RS3330K U902 CY25812SCT

XIN/CLKIN1VSS2S13S04

XOUT 8VDD 7

FRSEL 6SSCLK 5

R913 39.2F

C1680.1U

R9270

RY1 820K

JS1

20L2021003123

C169

10P J

L16 120 OHM

R136 39.2F

RS675K

US1

LMC7225

OUTPUT1

V+2

INPUT+3

V- 5

INPUT- 4

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SCK DQA2

DQA6DQA7

DQA5

DQB2DQB1

DQB8

DQB5DQB6

CTMN

CFM

U7-C75

U15-20

U15-18

CTM

U15-C76

MULT1MULT0

CTMCTMN

SIO0SIO1

CMD

CFMN

RQ7

RQ6RQ0

RQ3DQB1

RQ2

RQ1RQ4

STOPZ

VDRCG

DQA0

DQA7

RQ5

DQB[0:8]

DQA6

DQB8

DQB6

RQ4

DQA5

RQ2

RQ

[0:7]

RQ3

RQ6DQB3

DQB7

DQB3

DQB2

DQB4

DQA1

DQB0

DQB7

DQB4

DQB5

DQA[0:8]

VTERM

DQA4

RQ5

DQA0

RQ1RQ0

DQA4

DQB0

RQ7

DQA1

DQA2

DQA3

DQA8

2V5_D

REFCLKSCLKNPCLKM

DRCGPDZ

SIOCMDSCK

CFM

CFMN

VREF-RDRAM

GND

3.3V_D

CTMN

CTM RQ[0:7]

DQA[0:8]

DQB[0:8]

CTMCTMN

VDRCG

VTERM VREF-RDRAM

VDRCG

2V5_D

2V5_D

3.3V_D

2V5_D

2V5_D

VDRCG

VTERM

VTERM

VTERM

VTERM

VTERM

2V5_D

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

16 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

RDRAM VDD DECOUPLING CAPS

VTERM BULK DECOUPLING CAPS

CDCR83 (DRCG) 3.3V DECOUPLING CAPS

GND:4,5,8,17,21VDRCG:3,9,16,22NC:19

VTERM DECOUPLING CAPS

GND:A1,A9,A12,B4,C9,D4,D9GND:E4,F9,G4,H4,J1,J9,J12P2P5V:A4,B9,C1,C4,C12,D8P2P5V:E9,F4,G1,G9,G12,H9,J4

OPEN

U32

R15475F

R13810K

C1960.1U

RN35 39

1234

8765

C2020.1U

C19068P J

C17610P J

C2040.1U

C1730.1U

C1990.1U

C18868P J

C1840.1U

R151

75F

R145 110F

C2060.1U

C1820.1U R152

39.2F

C1910.1U

R143 10K

U33 MIC39100-1.8BS

OUT 3IN1

GN

D1

2

GN

D2

4

C1800.1U

C1790.1U

RN34 39

1234

8765

R15375F

L17

120 OHM

RN32 39

1234

8765

U31 CDCR83

REFCLK2SYNCLKN7PCLKM6

MULT015MULT114

S024S123S213

PWRDNB12STOPB11

VDDIR1

VDDIPD10

CLK 20

CLKB 18

GND 4GND 5GND 8GND 17GND 21

VDD 3VDD 9VDD 16VDD 22

NC 19

R14010K

C1720.1U

C1930.1U

+ C18110U M6.3V

12

C1950.1U

C1970.1U

C1750.1U

R14939.2F

R14710K

R14256.2F

K4R271669D-TCS8

RQ0G1RQ1F2RQ2F6RQ3F7RQ4F1RQ5E7RQ6E6RQ7E2

SIO1J3SIO0J5

CTME1CTMND1CFMC7CFMND7VREFD2

NC1 J1DQB7 J7DQB6 H2DQB5 H6DQB4 H7DQB3 H1DQB2 G2DQB1 G6

DQA0 C1DQA1 C2DQA2 C6DQA3 B1DQA4 B7DQA5 B6DQA6 B2DQA7 A7

DQB0 G7

NC2 A1

CMDA5SCKA3

GNDA D5GND A6GND B3GND C5

GND E3GND D3

GND F5GND G3GND H3GND J6

VCMOSA2VCMOSJ2VDDAD6P2P5VB5P2P5VC3P2P5VE5P2P5VF3P2P5VG5P2P5VH5

C2030.1U

R150

75F

C1780.1U

C2050.1U

R14456.2F

RN31 39

1234

8765

C1770.1U

R148 39.2F

+ C171150U6.3V

12

C2070.1U

C1890.1U

R156121F

R146 39.2F

+ C200100U6.3V

12

C1870.1U

C1740.1U

RN36 39

1234

8765

R155

36.5F

C1920.1U

C1860.1U

R13910K

C18568P J

RN33 39

1234

8765

+ C19810U M6.3V

12

+ C201100U6.3V

12

R141 110F

C1940.1U

C18368P J

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DGE7DGE6

DGE3DGE4DGE5

DGE0

DGE2DGE1

DRE4

DRE7DRE6DRE5

DRE0

DRE3DRE2DRE1

DBE7DBE6

ADCLK-L

ASCTRL-LALOADB-LZ

ASACBUS

DBE4

DBE1DBE2

ATRC-L

ASACCLK

DBE3

DBE0

DGE[7:0]

DRE[7:0]

DBE[7:0]

DMDSER

DBE5

TRC-LATRC-L

ASACCLKASACBUS

ADD15

ADD50

ADD38

ADD8

ADD39

ADD52

ADD4

ADD56

ADD46

ADD47

ADD32

ADD25

ADD35

ADD41

ADD5

ADD11

ADD30

ADD62

ADD58

ADD59

ADD14

ADD21

ADD28

ADD24

ADD5

ADD56

ADD37ADD57

ADD47

ADD26

ADD36

ADD31

ADD25

ADD33

ADD23

ADD61

ADD21

ADD3

ADD54ADD60

ADD34

ADD34

ADD42

ADD6

ADD7

ADD40

ADD23

ADD13

ADD48

ADD49

ADD51

ADD27

ADD17

ADD46

ADD38

ADD[63:0]

ADD49

ADD11

ADD30

ADD50

ADD17

ADD55

ADD10

ADD36

ADD0

ADD28

ADD39

ADD18

ADD16

ADD55

ADD63

ADD45ADD63

ADD32

ADD43

ADD20

ADD62

ADD59

ADD15

ADD26

ADD8

ADD19ADD18

ADD3

ADD37

ADD13

ADD42

ADD61

ADD22

ADD16

ADD12

ADD57

ADD40

ADD14

ADD44

ADD24

ADD9

ADD31

ADD4

ADD53

ADD7

ADD27

ADD52

ADD45

ADD41

ADD33ADD53

ADD54

ADD60

ADD29

ADD29

ADD22

ADD10

ADD35

ADD19

ADD0

ADD48

ADD1

ADD58

ADD2

ADD12

ADD43ADD44

ADD51

ADD20

ASCTRL-L SCTRL-LALOADB-LZ LOADB-LZ

ADD2ADD6ADD1ADD9

DD[0:63]

SACCLKSACBUS

DD7

DD15

DD52

DD35

DD43

DD29

DD57

DD33

DD60

DD45

DD22

DD34

DD47

DD24

DD25

DD48

DD12

DD18

DD6

DD36

DD26

DD37

DD49

DD42

DD17

DD50

DD56

DD8

DD10

DD30

DD53

DD55

DD28

DD51

DD21

DD40

DD62DD63

DD3

DD44

DD4DD11

DD41DD58DD61

DD23

DD16

DD5

DD31

DD54

DD59

DD20

DD39

DD32

DD46

DD27

DD14DD13

DD19

DD2

DD0

DD1

DD38

DD9

DCLK-LADCLK-L

DMDSER

DGE[7:0]

DRE[7:0]

DBE[7:0]

TRC-L

SCTRL-LLOADB-LZ

SACCLKSACBUS

DD[0:63]

GND

DCLK-L

ATRC-L

ADCLK-LALOADB-LZASCTRL-LATRC-L

ASACBUSASACCLK

ASACCLKASACBUS

ASCTRL-LALOADB-LZ

ADCLK-L

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

17 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

RN40

22

3456

14131211

21

78 9

10

1516

RN43

22

3456

14131211

21

78 9

10

1516

RN39

22

3456

14131211

21

78 9

10

1516

R807 22

C80610P J

RN41

22

3456

14131211

21

78 9

10

1516

RN37

22

3456

14131211

21

78 9

10

1516

RN38

22

3456

14131211

21

78 9

10

1516

C807

10P J

INPUT AND DMD

U29C

DDP1000-C

DD0 AC11DD1 AF10DD2 AE11DD3 AD10DD4 AF9DD5 AC10DD6 AE10DD7 AD9DD8 AF8DD9 AE9DD10 AC9DD11 AD8DD12 AF7DD13 AE8DD14 AC8DD15 AD7DD16 AE7DD17 AF5DD18 AC7DD19 AD6DD20 AE6DD21 AF4DD22 AC6DD23 AE5DD24 AE4DD25 AF3DD26 AD5DD27 AD4DD28 AE3DD29 AC5DD30 AB4DD31 AC3DD32 AB3DD33 AD1DD34 AB2DD35 AA4DD36 AC1DD37 AA2DD38 AA3DD39 Y4DD40 AB1DD41 Y2DD42 Y3DD43 W4DD44 W2DD45 Y1DD46 W3DD47 V4DD48 V2DD49 W1DD50 V3DD51 U2DD52 U4DD53 V1DD54 U3DD55 U1DD56 T4DD57 T3DD58 R2DD59 P4DD60 R3DD61 R4DD62 P2DD63 P1

A0C25 A1D24 A2E24 A3C26 A4D25 A5E25 A6F23 A7D26 A8F25 A9F24

B0G23 B1E26 B2G25 B3G24 B4H23 B5H25 B6G26 B7H24 B8J23 B9J25

C0H26 C1J24 C2K23 C3J26 C4K24 C5L25 C6K26 C7L23 C8L24 C9M25

DCLK_L AE12LOADB_LZ AC12

SCTRL_L AC13TRC_L AD11

DCLK_R P3LOADB_RZ M1

SCTRL_R N1TRC_R N3

SACBUS M2SACCLK N4

DMDSERING2

D0A25

D1D22

RN45

22

3456

14131211

21

78 9

10

1516

RN42

22

3456

14131211

21

78 9

10

1516

RN44

22

3456

14131211

21

78 9

10

1516

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

MBRST8

MBRST7MBRST6MBRST5MBRST4MBRST3MBRST2MBRST1MBRST0

MBRST11MBRST10MBRST9

MBRST15MBRST14

MBRST12MBRST13

V5REG

VRST

VRST_SWL

VBIAS_SWL

VBIAS_LHI

VBIAS

P12V_FLT

MBRST[0:15]

3.3V_D

SCPCKSCPDISCPDOSCPENZ

SR16STROBESR16MODE1SR16MODE0SR16SEL1SR16SEL0


EXT-ARSTZSR16OEZ

IRQZ

V12_D

VCC2

MBRST[0:15]

3.3V_D

VCC2

3.3V_D

3.3V_D 3.3V_D

V12_D

Title

Size Document Number R ev.

Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

18 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

open open

The width of net MBRST[0:15] should be larger than 11mils and the distance between two net should be larger than 11 mils.

C7100.1U Z

TP219

L703

120 OHM

C704

0.1U Z

TP218

C7020.1U Z

C7140.1U Z

L70122UH

+ C7013.3U35V

12

C7090.1U Z

C7120.1U Z

C7064.7U Z

TP221

C7150.1U Z

R702

0

+ C73510U16V

12

R725

1K

L70222UH

R701

0

C7030.1U Z

U701

DAD1000

SCP_CLK56SCPDI57SCPDO42SCPENZ58

STORBE15MODE12MODE03SEL14SEL05

A316A217A118A019

DEV_ID145DEV_ID044

RESETZ59OEZ6

VCC54

V12_SWL152V12_SWL051

V12_350V12_248V12_111

VBIAS_RAIL780VBIAS_RAIL671VBIAS_RAIL570VBIAS_RAIL461VBIAS_RAIL340VBIAS_RAIL231VBIAS_RAIL130VBIAS_RAIL021

VBIAS9

VBIAS_SWL8

VBIAS_LHI10

OUT15 79OUT14 77OUT13 74OUT12 72OUT11 69OUT10 67OUT09 64OUT08 62

OUT7 39OUT6 37OUT5 34OUT4 32OUT3 29OUT2 27OUT1 24OUT0 22

IRQZ 43

VOFF_RAIL7 78VOFF_RAIL6 73VOFF_RAIL5 68VOFF_RAIL4 63VOFF_RAIL3 38VOFF_RAIL2 33VOFF_RAIL1 28VOFF_RAIL0 23

VOFF 49

V5REG 47

VRST_RAIL7 76VRST_RAIL6 75VRST_RAIL5 66VRST_RAIL4 65VRST_RAIL3 36VRST_RAIL2 35VRST_RAIL1 26VRST_RAIL0 25

VRST 13

VRST_SWL 12GN

D1

GN

D7

GN

D14

GN

D20

GN

D41

GN

D46

GN

D53

GN

D55

GN

D60

+ C7133.3U35V

12

TP220

C7110.1U Z

TP223

C7050.1U Z

C7070.22U K

R726

10K

C7084.7U Z

R2531K

TP222

D701MBR0540T1

12

TP217

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

OUTB

OUTA

ALVDD

BRAKE

MTRSELZMTRCLKMTRDATA

CD2CWDCD1

CRESCST

EXT-ARSTZ

MFILT1

OUTC

CWCTR

CWY3

ALVDD

CWCTR

MFILT

CWY2

CWY1

CWTACH

GND

V12_D

CKMTR1

EXT-ARSTZMTRSELZMTRCLKMTRDATA

VDD_D

CWTACH

V12_D

VDD_D

ALVDDVDD_D

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

19 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

Include Guard Ring Aroundthese components on top and buttom layers

See Motor Timing CAP. Chart

See Motor Timing CAP. Chart

Spare for reversed spin motor

TP57

DN11BAT54SW

21

3

U42 A8904SLB

VBB1VDD15BRAKEZ11

OSC16RESETZ20CSZ21CLOCK22DATAIN23

CD22CWD3CD124

CRES12CST4

SECDAT14FILTER13

OUTA 5

OUTB 8

OUTC 9

CNTRTAP 10

DATAOUT 17

GNDA 6GNDB 7GNDC 18GNDD 19

R203 1.5

C2423300P K

R194150

RX4 OPEN

R196150

R201

1K

C2435600P K

C2330.1U M

+ C23122U25V

12

TP60

C2391000P K

L19

80 OHM

RX3 OPEN

DN12BAT54SW

21

3

R198

1K

C2443300P K

R197 39.2F

C2370.1U K

TP58

C2450.22U K

C2340.1U M

DN14BAT54SW

21

3

L20

80 OHM

JC1

20K2002004

1234

C2461U K

R202

1K

C2470.022U K

DN13BAT54SW

21

3

R2061.5MF

C2381000P K

R199

1K

C2410.022U K

C2350.1U M

R205 1.5

C2360.1U K

R204 1.5

C2480.33U Z

R200

1K

R195150

TP59

U41

74V1G14S

2 45

3

1

C2401000P K

C2320.1U M

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DD54

DCLK-L

DD46

DD52

SACCLK

SCTRL-LTRC-L

SACBUS LOADB-LZ

DD44

DMDSER

DD56DD58

DD48DD50

DD63DD61DD60

DD57

BINSEL0

DD62

DD53

DD59

DD55

DD49DD51

DD32

DD42

DD38

DD40

DD34

DD36

DD24

DD30

DD22DD20

DD14

DD28

DD12

DD16

DD26

DD4

DD8

DD18

DD10

DD2

MBRST8

DD0

DD6

MBRST4

MBRST12MBRST14

MBRST10

MBRST6

MBRST2MBRST0

DD47DD45

DD43

DD39DD37

DD31

DD41

DD29

DD35DD33

DD27

DD23DD21

DD25

DD15

DD17

DD13

DD19

DD7

DD11

DD5

MBRST15

BINSEL1

MBRST13

DD9

DD1DD3

MBRST7MBRST5

MBRST9MBRST11

MBRST1MBRST3

MBRST[0:15]

DD[0:63]

VDD

3.3V_D

BINSEL0BINSEL1

DD[0:63]

MBRST[0:15]

GND

DMDSERLOADB-LZ

DCLK-L

VCC2

SACCLKSACBUSSCTRL-LTRC-L

3.3V_D VCC2

VDD

Title


Date: Sheet o f

Project Code


Model Name

PCB P/N PCB Rev.


48.J8601.S04

MAIN BOARD

20 20


99.J8677.B12-C3-304-004S04

ANGEL HU

<Size>

PB610099.J8677.001

1


<OEM/ODM>

Screw Holes

Optical Points

JP2

20L1066080

2468

101214161820222426283032343638404244464850525456586062646668707274767880

135791113151719212325272931333537394143454749515355575961636567697173757779

OPMARK6

OPMARK3

OPMARK1

OPMARK10

OPMARK9

OPMARK20

OPMARK5

OPMARK15

H3

HOLE-V8

1

2

3

4

5

6

7

8

9

JP3

20L1066080

2468

101214161820222426283032343638404244464850525456586062646668707274767880

135791113151719212325272931333537394143454749515355575961636567697173757779

OPMARK17

OPMARK19

H4

HOLE-V8

1

2

3

4

5

6

7

8

9

OPMARK12

OPMARK11

H6

HOLE-V8

1

2

3

4

5

6

7

8

9

OPMARK13

OPMARK14

H5

HOLE-V8

1

2

3

4

5

6

7

8

9

benq-ldp6100

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