BER Analysis of MLC NAND Flash Memoriesbased on an Asymmetric PAM Model

Stelios Korkotsides, Georgios Bikas, Efstratios Eftaxiadis and Theodore AntonakopoulosUniversity of Patras

Department of Electrical and Computer EngineeringPatras 26504, Greece

e-mails: stelkork@ece.upatras.gr, ece6805@upnet.gr, ece6740@upnet.gr and antonako@upatras.gr

Abstract—The reliability of multilevel NAND Flash memories,which are used extensively on solid-state drives, is stronglyaffected by their aging, ie. the number of applied program/erasecycles (P/E). A multilevel memory uses discrete voltage levelsto represent the various bit patterns and at the beginning ofthe life-time of such a device these voltage levels demonstratedistributions with very small variances, resulting to very low bit-error-ratio (BER). As the number of applied P/E cycles increases,the variance of the voltage levels also increases and that resultsto increased BER. In this paper, we present a general model forfour-level NAND Flash memories that can be used to estimatememories’ BER as a function of the used NAND technologyand the aging process. For that purpose, we use asymmetricPulse Amplitude Modulation with data-dependent channel noiseand we provide analytic expressions for the behavior of suchmemories, and we associate aging with noise conditions and usedtechnology.

Index Terms—NAND Flash, aging, asymmetric PAM, voltagedistributions.

I. INTRODUCTION

The last few years, remarkable technological achievementshave been demonstrated in the area of NAND Flash memory.Storage density and capacity have been increased and produc-tion cost has been suppressed, resulting to new storage devicesthat exceed other conventional storage technologies. The mainreasons that led to this achievement are the supported high datatransfer rates, the adjustment of endurance of various NANDtechnologies to specific application needs and the low powerdissipation that has been achieved, especially during erasingand programming.

In order to satisfy the constantly increasing storage needs,scaling of silicon technology and the use of Multi-level Cell(MLC) was employed [1]. Especially the achievements ofMLC increased the storage density and reduced the cost perbit significantly, but also affected the complexity, reliabilityand endurance of the devices. Except of the interference ofadjacent cells due to scaling, the challenge of low probabilityof erroneous detection between adjacent voltage levels wasalso introduced.

In this work, we present a model for studying the probabilityof errors on MLC NAND Flash memories. In this model,we use asymmetric Pulse Amplitude Modulation with data-dependent channel noise. The introduced noise is additive,follows the gaussian distribution but its variance depends on

the voltage level used during programming, thus it is datadependent. This noise model is based on measurements in [1]and appears in several experimental studies of non-volatilememories, such as [2], [3], [4], [5]. As it will be shown,there is a strong similarity between this model and the 4-states Pulse Amplitude Modulation (4-PAM) scheme that isused to transmit data over an additive, white gaussian (AWGN)communication channel [6]. The main differences betweenthe typical 4-PAM communication scheme and the proposedmodel of the NAND Flash memory cell is that the inter-symboldistance between adjacent levels is not fixed, but dependson the voltage levels, and statistical characteristics of theintroduced noise depend on the symbol that was written. Thatis why we use the term Asymmetrical 4-PAM for the analysisthat follows in the next sections. The main goal of this workis to study the behavior of critical quantities, such as SNR andBER, when the characteristics of memory cells change as thenumber of programming cycles increases. In this effort, wealso calculate the optimum detection thresholds between adja-cent levels and in all measurements these optimum thresholdsare used for bit error ratio (BER) calculations.

Section II presents the basic model used in our analysis,while in Section III we present the mathematical analysis ofthe used model. More specifically, subsection III-A presentsthe calculation of the optimum threshold voltage in adjacentlevels that use different noise distributions, while subsectionIII-B extends the previous analysis to a 4-levels NANDFlash cell. Subsection III-C presents the analysis of BER andthe signal-to-noise ratio (SNR) of such a cell. Section IVhighlights the effect of the various parameters of the abovemodel.

II. MLC NAND FLASH MODEL

In a NAND Flash memory cell, several noise sources affectthe achieved programming voltages and the sensed voltagesduring read. These noise sources force the level voltagesto fluctuate around their nominal values. These fluctuationscan be treated as stochastic signals which can be representedquite accurately with four gaussian distributions as shown inFig. 1. This has been confirmed with measurements of theinitially implemented MLC NAND flash memory [1] and, eversince, it has become the mainstream model of MLC NANDFlash memory cells. Moreover, it has been noticed that the

αL m1L L m2L

S1 S2 S3 S4

Gray Mapping

‘11’ ‘01’ ‘00’ ‘10’

κ1σ σ σ κ2σ

0 1T1 T2 T3

Normalized Voltage

Probability

Density

Function

1

Fig. 1. Voltage distributions of a 4-levels cell.

statistical characteristics of these voltage variations change asthe lifetime of the device progresses. More specifically, thestandard deviation of the sensed voltages increases and theirmean values shift to higher values.

The voltage distributions of Fig. 1 are based on[7], but inorder to be able to include in our model the aging effect,as well as to represent as many technologies as possible, weupgraded it to a fully parameterized model, ie. the noises aredefined at each voltage level and the inter-symbol distancesare not constant. For the following analysis, the level voltageshave been normalized to the dynamic range of the usedsensing circuit. Therefore, the standard deviations of the fourdistributions are defined as σ1 = κ1σ, σ2 = σ3 = σ andσ4 = κ2σ.

This approach can cover all different NAND Flash tech-nologies presented in the literature. For example, based on[8], κ1 = 2 and κ2 = 1 or in [9], κ1 = 1.5 and κ2 = 1.2. Inother cases, like those found in [10] and [7], other parametersare used: κ1 = 4 and κ2 = 2. Following the same approach,the nominal voltage levels are expressed as:

V1 = αL

V2 = (α+m1)L

V3 = (α+m1 + 1)L

V4 = (α+m1 +m2 + 1)L

(1)

In order to achieve lower BER, Gray coding is usually used,so that adjacent symbols differ in only one bit [7]. Duringvoltage sensing, voltage thresholds between adjacent levelsare specified that result to optimum detection. If Vi and Vi+1

are two adjacent levels (Vi+1 > Vi), the optimum voltagethreshold is the voltage value that minimizes the probabilityof erroneous level detection, and this is presented in the firstpart of next section.

III. THEORETICAL ANALYSIS OF ASYMMETRIC PAMA. Voltage thresholds between adjacent cells

We consider two adjacent voltage levels which are affectedby different noise sources, as shown in Fig. 2. The following

κσ σ

Vi Ti Vi+1

Normalized Voltage

CellDistribution

1

Fig. 2. Voltage distributions and threshold in two adjacent levels.

analysis can be applied in any aging condition of a cell [11].Let pe() denotes the probability of erroneous level detection.

Using the well-known gaussian distribution we get:

pe(Ti) = pi1

κσ√2π

+∞∫Ti

e− (x−Vi)

2

2(κσ)2 dx +

+pi+11

σ√2π

Ti∫−∞

e−(x−Vi+1)2

2σ2 dx

(2)

where pi and pi+1 are the probabilities to store informationat levels i and i + 1 respectively. In order to determine thethreshold that minimizes the probability of error, we have

dpedTi

= 0⇒(1− κ2

)T 2i + 2

(κ2Vi+1 − Vi

)Ti+

+

[V 2i − κ2Vi+1 + 2σ2 ln

(κpi+1

pi

)]= 0

(3)

B. Multi-level voltage thresholds

In order to analyze the 4-levels cell, we use the previousanalysis and we extended it to the three different cases ofadjacent levels shown in Fig. 1. Therefore, T1, T2 and T3 arethe roots of the following equations:

(1− κ21

)T 21 + 2

(κ21V2 − V1

)T1 +

+

[(V1)

2 − κ21V 22 + 2 (κ1σ)

2 ln

(κ1p2p1

)]= 0

(4)

2 (V3 − V2)T2 +[2σ2 ln

(p3p2

)+ V 2

2 − V 23

]= 0 (5)

(1− 1

κ22

)T 23 + 2

(1

κ22V4 − V3

)T3 +

+

[(V3)

2 − 1

κ22V 24 + 2 (κ2σ)

2 ln

(p4κ2p3

)]= 0

(6)

C. BER and SNR in Gray coding MLC

The most important characteristic of Gray codes is thatadjacent symbols differ in only one bit. This makes themvery attractive to be used inside a NAND Flash cell, sincethe probability of erroneously detecting a voltage level, thatdoes not belong to adjacent levels during sensing is very lowand in our BER analysis we consider the Gray mapping shownin Fig. 1.

The probability of bit error when symbol S1 is detected isgiven by:

P (eb|S1) =1√

2πκ1σ

[1

2

T2∫T1

e− (x−V1)2

2κ21σ2 dx+

T3∫T2

e− (x−V1)2

2κ21σ2 dx+

+1

2

+∞∫T3

e− (x−V1)2

2κ21σ2 dx

]=

=1

4

[erfc

(T1 − V1√2κ1σ

)+ erfc

(T2 − V1√2κ1σ

)−

− erfc(T3 − V1√2κ1σ

)](7)

where erfc(x) ≡ 2√π

∫∞xe−t

2

dt.

Using the same methodology, we calculate the bit errorprobabilities when symbols S2, S3 and S4 are detected. Wenow can compute the total probability of bit error by weightingthe above probabilities of error with the probability of writingthe respective symbols to the memory cell. For example, p1is the probability of programming S1 = 11, while p4 is theprobability of programming S4 = 10. Therefore:

P (eb) = p1P (eb|S1)+p2P (eb|S2)+p3P (eb|S3)+p4P (eb|S4)(8)

The signal to noise ratio of the sensed voltages is defined as:

SNR ≡ PsPnoise

=EsEnoise

=p1V

21 + p2V

22 + p3V

23 + p4V

24

p1(κ1σ)2 + p2σ2 + p3σ2 + p4(κ2σ)2

(9)

which is derived by treating symbols as discrete signals andtaking into account that the power spectral density of AWGNis equal to its variance.

IV. MODEL PARAMETERS AND PERFORMANCE RESULTS

In order to study the effect of the various parameters ofthe above model, we consider various NAND Flash tech-nologies and various probabilities of the programmed data.Table I shows the various NAND Flash technologies andthe respective noise distributions, while Table II shows thesymbol probabilities for various bit probabilities, where ρ isthe probability of bit ‘1’.

Using the parameters ρ, σ, κ1, κ2, α, L, m1, m2 and theoptimum voltage thresholds determined by using equations (4),(5), (6), we can estimate the expected BER as a function ofσ and we can associate σ with SNR.

TABLE INAND FLASH TECHNOLOGIES

Level 3 2 1 0Mean 0.2 0.525 0.655 0.85Deviation (1) 4σ σ σ 2σDeviation (2) 4σ σ σ σDeviation (3) σ σ σ σ

TABLE IISYMBOL PROBABILITIES

ρ = 0.25 ρ = 0.5 ρ = 0.75P (S1) 0.0625 0.25 0.5625P (S2) 0.1875 0.25 0.1875P (S3) 0.5625 0.25 0.0625P (S4) 0.1875 0.25 0.1875

0 10 20 30 40 50 60 70 80 90 10010

−5

10−4

10−3

10−2

10−1

BER

P/E cycles [K]

Fig. 3. MLC NAND Flash experimental BER versus P/E cycles.

Fig. 3 shows experimental results from a typical 4-levelsNAND Flash memory and how BER is associated with theaging on the memory. Aging is expressed by the number ofP/E cycles. The endurance of the experimental memory is10K P/E cycles and during this experiment we stressed thedevice an order of magnitude higher than its typical endurance.Depending on the used error correcting codes, the lifetime ofsuch a device is less than 50K P/E cycles.

Using the analysis of Section III, we can study the BER ofNAND cells modeled as asymmetric 4-PAM. Fig. 4 showsBER as a function of σ. Comparing the curves of Figs.3 and 4 we can easily conclude that the presented modeldescribes adequately a MLC NAND Flash memory. Similarly,Fig. 5 shows how SNR is associated with σ for differentbit probabilities. Combining the above two figures, we resultto Fig. 6 which shows the relation of SNR with BER forvarious bit and symbol probabilities. As it is shown in thisfigure, due to the asymmetric nature of the PAM model thataccurately represents the NAND Flash cells, the use of lineprecoding may improve the BER performance at the cost ofreduced storage efficiency due to overhead introduced by theline coding that results to non-equal bit probabilities.

Finally, using the NAND experimental results and thetheoretical analysis, we can associate aging (P/E cycles) withσ. Fig. 7 highlights this relation for different NAND models.

0.01 0.02 0.03 0.04 0.05 0.0610

−8

10−6

10−4

10−2

σ

BER

κ

1=4, κ

2=2

κ1=4, κ

2=1

κ1=1, κ

2=1

0.024 0.027 0.03

10−3

10−2

Fig. 4. BER as a function of σ for non-equally probable symbols (ρ = 0.25).

0.01 0.02 0.03 0.04 0.05 0.06 0.075

10

15

20

25

30

35

σ

SNR

[dB]

ρ=0.25ρ=0.5ρ=0.75

Fig. 5. SNR as a function of σ for non-equally probable symbols.

Such analysis is very helpful in the design of realistic NANDFlash emulators that can be used for real-time emulation ofstorage devices and systems.

V. CONCLUSIONS

In this paper we presented a model for 4-level NANDFlash memories that is based on asymmetric PAM with data-dependent additive noise. The analysis is independent to a spe-cific NAND Flash technology and is applicable to all knowntechnologies. By using the proper model parameters a specificNAND Flash technology can be accurately modeled and thiscan be exploited for developing realistic and accurate NANDFlash emulators. The presented analysis can be extendedeither to model NAND Flashes with more voltage levels,or to describe the behavior of other non-volatile memorytechnologies.

REFERENCES

[1] G. Atwood, A. Fazio, D. Mills, and B. Reaves, “Intel strataflash memorytechnology overview,” Intel Technology Journal, 1997.

[2] Z. Wang, M. Karpovsky, and A. Joshi, “Reliable mlc nand flashmemories based on nonlinear t-error-correcting codes,” in DependableSystems and Networks (DSN), 2010 IEEE/IFIP International Conferenceon, 2010, pp. 41–50.

[3] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction toflash memory,” Proceedings of the IEEE, vol. 91, no. 4, pp. 489–502,2003.

12 14 16 18 20 22 24 26 28 30 3210

−10

10−8

10−6

10−4

10−2

100

SNR [dB]

BER

ρ=0.25ρ=0.5ρ=0.75

Fig. 6. BER as a function of SNR for non-equally probable symbols.

0 20 40 60 80 100 1200.01

0.015

0.02

0.025

0.03

0.035

0.04

P/E Cycles [K]

σ

κ1=4 κ

2=2

κ1=4 κ

2=1

κ1=1 κ

2=1

Fig. 7. The relation of introduced noise and the P/E cycles.

[4] J. Brewer and M. Gill, Nonvolatile Memory Technologies with Emphasison Flash: A Comprehensive Guide to Understanding and Using FlashMemory Devices. Wiley. com, 2011, vol. 8.

[5] G. Dong, S. Li, and T. Zhang, “Using data postcompensation andpredistortion to tolerate cell-to-cell interference in mlc nand flashmemory,” Trans. Cir. Sys. Part I, vol. 57, no. 10, pp. 2718–2728, Oct.2010. [Online]. Available: http://dx.doi.org/10.1109/TCSI.2010.2046966

[6] J. Proakis and M. Salehi, Digital Communications, ser. McGraw-Hillhigher education. McGraw-Hill Education, 2007.

[7] B. Chen, X. Zhang, and Z. Wang, “Error correction for multi-level nandflash memory using reed-solomon codes,” in Signal Processing Systems,2008. SiPS 2008. IEEE Workshop on, 2008, pp. 94–99.

[8] S. Li and T. Zhang, “Improving multi-level nand flash memory stor-age reliability using concatenated bch-tcm coding,” Very Large ScaleIntegration (VLSI) Systems, IEEE Transactions on, vol. 18, no. 10, pp.1412–1420, 2010.

[9] Y. Maeda and H. Kaneko, “Error control coding for multilevel cellflash memories using nonbinary low-density parity-check codes,” inDefect and Fault Tolerance in VLSI Systems, 2009. DFT ’09. 24th IEEEInternational Symposium on, 2009, pp. 367–375.

[10] F. Sun, K. Rose, and T. Zhang, “On the use of strong bch codes forimproving multilevel nand flash memory storage capacity,” in IEEEWorkshop on Signal Processing Systems (SiPS): Design and Implemen-tation, 2006.

[11] Y. Cai, E. F. Haratsch, O. Mutlu, and K. Mai, “Threshold voltagedistribution in mlc nand flash memory: characterization, analysis, andmodeling,” in Proceedings of the Conference on Design, Automation andTest in Europe. EDA Consortium, 2013, pp. 1285–1290.