bicmos process
TRANSCRIPT
-
8/3/2019 Bicmos Process
1/22
ANALOG BiCMOS
-
8/3/2019 Bicmos Process
2/22
Introduction
What is BiCMOS?
BiCMOS technologycombines
Bipolarand CMOS transistors ontoa
single integratedcircuit wheretheadvantages ofbothcanbeutilized.
-
8/3/2019 Bicmos Process
3/22
Advantages ofCMOS overBipolar
Powerdissipation
N
ois
emarg
in
Packingdensity
Theabilityto integratelargecomples
functions withhighyields
-
8/3/2019 Bicmos Process
4/22
Advantages ofBipolaroverCMOS
Switching speed
Currents drive perunitarea
Noise perfomance
Analogcapability
Input/output speed
-
8/3/2019 Bicmos Process
5/22
Advantages ofBiCMOS Technology
Improved speedoverCMOS
Lowerpowerdissipationthan Bipolar
Flexible input/outputs
High performanceanalog
Latchup immunity
-
8/3/2019 Bicmos Process
6/22
Analog BiCMOS Complexity
Higherperformance
analogcircuits Reduceddesignefforts
Fasterdesigncycles
Higherwafercost
Longermanufacturingtime
Lowerprocess yields
Analog BiCMOS processes arecharacterizedbytheir
complexity,mostneeding15masks. Someup to 30 masks.
Advantages of complexity Disadvantages of complexity
-
8/3/2019 Bicmos Process
7/22
EvolutionofBiCMOS from CMOS
BiCMOS technologies havetendedtoevolvefrom CMOS
processes inordertoobtainthehighest CMOSperformance possible.
Thebipolarprocessing steps havebeenaddedtothecore
CMOS flow torealizethedesireddevicecharacteristics.
-
8/3/2019 Bicmos Process
8/22
FabricationEquipmentMolecularBeamEpitaxy
(MBE)
-
8/3/2019 Bicmos Process
9/22
FabricationEquipmentPhotoresist Spinner Bake-out Ovens
-
8/3/2019 Bicmos Process
10/22
FabricationEquipmentMaskAligner ReactiveIonEtching (RIE)
-
8/3/2019 Bicmos Process
11/22
FabricationEquipmentChemical VaporDeposition
(CVD)
Plasma Quest Sputter
-
8/3/2019 Bicmos Process
12/22
FabricationEquipmentPlasma Sputter Perk in-ElmerMBE
-
8/3/2019 Bicmos Process
13/22
FabricationEquipmentProbe Station ScanningElectron
Microscope (SEM)
-
8/3/2019 Bicmos Process
14/22
N-well CMOS StructureNMOS device,built ina15umthickP-epitaxiallayerontop ofP+substrate
PMOS transistor,built inan implanted N-wellapproximately5umdeep
P+ substrate is usedtoreducelatchup susceptibilityby providingalowimpedance patchthroughaverticalPNPdevice
Polysilicongates areusedforboththePMOS and NMOS transistors
-
8/3/2019 Bicmos Process
15/22
Adding NPN BipolarTransistorThe simplest waytoaddan NPNbipolartransistortothe previous CMOSstructure is byusingPMOS N-wellas thecollectorofthe Bipolardevice
and introducinganadditionalmasklevelfortheP-baseregion.
theP-base is approx1umdeep withadopinglevelofabout1e17atoms/cm^3
the N+ source/drain ion implantation step is usedfortheemitterand
collectorcontactofthebipolarstructure
theP+ source/drain ion implantation step is usedtocreateaP+base
contacttominimizethebase series resistance
-
8/3/2019 Bicmos Process
16/22
Contacts
-
8/3/2019 Bicmos Process
17/22
Contacts
EFnEc
Ev
EFi
qJs,n
qGs
n-type s/c
qJm
EFm
metal
qJBnqVbi
qJnDepl reg
-
8/3/2019 Bicmos Process
18/22
Pattern Shift NBL Shadow (1/2)
-
8/3/2019 Bicmos Process
19/22
Pattern Shift NBL Shadow (2/2)
Stacking faults
Anextra planeofatoms
Thelackofa planeofatoms
Other Causes
Temprature
Pressure
Waferpre-leaning
Growth precursor
-
8/3/2019 Bicmos Process
20/22
PIsolationvs. CDI
CollectorDiffusedIsolationPIsolation
-
8/3/2019 Bicmos Process
21/22
Keyfactorindeterminingoverallcircuit performanceand
density
CollectorDiffusedIsolation (CDI) N-wellusedtoformcollectorofNPN transistor
Baseandemitterconsistofsuccessivecounterdopingof
the well.
CDItransistors Saturate prematurely
Limits low-voltageoperation
Complicates devicemodeling
Causes undesired substrate injection
BiCMOS Isolation Consideration
-
8/3/2019 Bicmos Process
22/22
System-on-a-Chip Technology
personalInternetaccess devices
set-topboxes
thinclients
Applicationsof
BiCMOS Technology