Volume 4, Issue 5 SEP 2015

IJRAET

BIDIRECTIONAL BUCK–BOOST DC–DC

CHOPPER-MODE INVERTERS WITH HFL BY USING FUZZY LOGIC

CONTROLLER

AADEPU SATHEESH1 , MR. K. SHANKER2

1PG Scholor, St. Martin’s Engineering College, Hyderabad, Telangana, India 2Asst Professor St. Martin’s Engineering College, Hyderabad, Telangana, India

Abstract - A circuit configuration, a circuit

topological family, a buck-mode active clamped

circuit, and an on the spot output voltage feedback

management strategy of combined duplex buck–boost

dc–dc chopper-mode electrical converter with high-

frequency (HF) link (HFL) were projected and

absolutely investigated during this paper. The steady

principle characteristic and therefore the criterion

for the key circuit parameters with fuzzy logic got

during this paper. The circuit configuration consists

of 2 identical isolated duplex buck–boost dc–dc

choppers with an equivalent input and output filters.

These 2 choppers in parallel at input finish and serial

at output finish generate unipolarity curved pulse

breadth modulation current waveforms with positive

and negative [*fr1] low frequency cycles on an

individual basis. The circuit topological family

includes four circuit topologies, like one-transistor

mode. Taking the one-transistor mode circuit

topology as Associate in Nursing example, the

750VA48VDC/220V50HzAC example is meant and

enforced. The theoretical analysis and principle take

a look at show the inverters have glorious

performance.

Index Terms—Bidirectional power flow,

buck–boost dc–dc chopper, buck-mode active

clamped circuit, high-frequency (HF) link, inverter,

single-stage power conversion.

INTRODUCTION

The buck–boost dc–dc converter has

advantages such as simple topology, higher reliability

under overload or short-circuit conditions, and wide

use in the low power field [1]–[3]. However, this

converter has an inherent defect, i.e., the leakage

inductance energy of the high-frequency (HF) storage

transformer needs to be absorbed and inhibited. An

isolated buck–boost dc–dc converter with excellent

performance was obtained through active clamped or

resonant technology [4], [5]. The bidirectional buck–

boost dc–dc converter has important value on theory

and application in power conversion fields with

bidirectional power flow, such as electrical vehicles,

photo voltaic power supply systems of satellites,

battery charging and discharging, standby power

supplies, etc., and has gained much attention recently

[6], [7]. In particular, there are more problems to be

solved in the isolated bidirectional dc–dc converter

[8]. A unidirectional buck–boost mode inverter with

HF link (HFL) has the features of simple topology,

discontinuous operating mode, large total harmonic

distortion of the output current, low conversion

efficiency, and low output power [9]. A differential

buck–boost dc–dc converter mode inverter with HFL

has the features of two-stage conversion, circulating

current between two converters, and low efficiency

Volume 4, Issue 5 SEP 2015

IJRAET

[10]. A novel circuit configuration and the circuit

topological family of the combined bidirectional dc-

dc chopper mode inverters with HFL are proposed in

this paper. The inverter with HFL, which has only

single-stage power conversion and high conversion

efficiency, can be widely used in the inverting fields

such as those with dc generators, batteries,

photovoltaic cells, etc.

CIRCUIT TOPOLOGY FAMILY AND

CONTROL S TRATEGY

A. CIRCUIT CONFIGURATION AND

CIRCUIT-TOPOLOGY FAMILY

A circuit configuration and the circuit topological

family of combined bidirectional buck–boost dc–dc

chopper-mode inverters with HFL were proposed in

this paper, as shown in Fig. 1. While chopper I

outputs unipolarity sinusoidal pulsewidth modulation

(SPWM) current waveforms io1 with positive half

low-frequency (LF) cycle, chopper II is shut down

and freewheeling switch S25 is conducted, io2 = 0,

and chopper I generates the positive half cycle of

sinusoidal voltage uo filtered by capacitor Cf.

Conversely, while chopper II outputs unipolarity

SPWM current waveforms io2 with negative half LF

cycle, chopper I is shut down and freewheeling

switch S15 is conducted, io1 = 0, and chopper II

generates the half cycle of uo filtered by Cf. The

inverter has single-stage power conversion since only

one chopper is working at any time. When the power

flow is from source to the load, i.e., io1 > 0 or io2 >

0, the input dc voltage Ui is inverted to unipolarity

HF ac pulse currents ii1 and ii2 by the inverter. After

the galvanic isolation, transmission, and current

match by the HF storage transformers T1 and T2, ii1

and ii2 are rectified into unipolarity HF ac pulse

currents io1 and io2 by the rectifier. Then, io1 and

io2 are filtered into high-quality LF sinusoidal

voltage uo in ac load ZL by capacitor Cf. ii1 and io2

are filtered into smooth dc input current ii by the

input filter. When the power flow is from the load to

source, i.e., io1 < 0 or io2 < 0, the rectifying

switches are operating at inversion and the inverting

switches are operating at rectification. A circuit

topological family of the proposed inverter in cludes

four circuit topologies, namely, one-transistor mode,

two-transistor mode, interleaved one-transistor mode,

and in terleaved two-transistor mode, as shown in

Fig. 1(b)–(e). The voltage stress of the power

switches in the input inverter side of

(a)

(b)

(c)

Volume 4, Issue 5 SEP 2015

IJRAET

(d)

(e)

Fig. 1. Circuit configuration and circuit topological

family of the combined bidirectional buck–boost dc–

dc chopper-mode inverter with HFL. (a) Circuit

configuration. (b) One-transistor mode. (c) Two-

transistor mode. (d) Interleaved one-transistor mode.

(e) Interleaved two-transistor mode.

the one transistor mode circuit and two

transistor mode circuit are respectively about twice of

the input dc voltage and the input dc voltage, so the

former is suitable for low-input and low power

voltage inverter fields, and the later is suitable for

high input and low power voltage inverter fields. The

interleaved mode circuits shown in Fig. 1(d) and (e)

not only enlarge the output power but also increase

the number of power switches.

B. CONTROL STRATEGY

The output voltage instantaneous value

feedback control strategy is introduced in the

proposed inverter, as shown in Fig. 2. The frequency

divider by two circuits is used for producing HF

select signal us whose frequency is the switching

frequency, and the delay circuit is used for producing

dead time to realize zero-voltage switching

(ZVS) of power switches. The error voltage

amplifying signal ue is generated from the PI

regulator by comparing the output sinusoidal voltage

uo with reference sinusoidal voltage ur. The HF

SPWM signal uk1 and uk2 are separately generated

by comparing ue and –ue with the same unipolarity

triangular carrier wave uc. The HF select signal us

and its opposing signal us are generated, whose

square aveform usw is frequency divided by two.

The polarity select signals usy and usy of the positive

or negative half cycle of the output voltage are the

outputs of the zero-crossing comparator by

comparing ue with zero. The control signals of the

power switches are generated by the corresponding

logical and delay conversions of uk1, uk2, us, us, usy,

and usy. The output voltage can be adjusted and kept

stable by adjust ing the modulation depth of the dc

chopper and the amplitude of error signal ue when

the input voltage Ui or load ZL varies.

STEADY PRINCIPLES AND OUTPUT

CHARACTERISTIC

A. FOUR OPERATION MODES IN ONE LF

CYCLE

According to the direction of the chopper’s

power flow, the proposed inverter has four operation

modes A, B, C, and D in one LF cycle, as shown in

Table I. When analyzing operation modes, the

inverter’s load is the equivalent load of Cf and ZL in

parallel. Due to space con straints, this paper will

analyze a one-transistor mode shown in Fig. 1(b)

under equivalent inductive load. The steady principle

waveform of the proposed inverter in one LF output

voltage period is shown in Fig. 3. Under equivalent

inductive load, both load current io and the

Volume 4, Issue 5 SEP 2015

IJRAET

fundamental component of equivalent load

current ioe1 lag behind output voltage uo.

1) t = [t0−t1]: uo > 0, ioe1 < 0, chopper I is working

and chopper II is shut down, and the inverter is

operating in mode B. S13 is HF chopping, S11 is HF

conducted complementarily, and S25 is conducted.

Equivalent load feeds energy back to the source by

chopper I.

2) t = [t1−t2]: uo > 0, ioe1 > 0, chopper I is working,

chopper II is shut down, and the inverter is operating

in mode A. S11 is HF chopping, S13 is HF conducted

Fig. 2. Output voltage instantaneous value feedback

control strategy. (a) Block diagram.(b) Principle

waveforms

(b)

Volume 4, Issue 5 SEP 2015

IJRAET

TABLE I

OPERATION MODES OF THE PROPOSED

INVERTER IN ONE OUTPUT VOLTAGE PERIOD

Operation modes

Chopper I Chopper I Power Flow

Direction A Operating Shut-

down Positive

B Operating Shut-down

negative

C Shut-down

Operating Positive

D Shut-down

Operating negative

Complementarily , and S25 is conducted. The source

outputs energy to the equivalent load by chopper I.

3) t = [t2−t3]: uo < 0, ioe1 > 0, chopper I is shut

down and chopper II is working, and the inverter is

operating in mode D. S23 is HF chopping, S21 is HF

conducted complementarily, and S15 is conducted.

Equivalent load feeds energy back to the source by

chopper II.

4) t = [t3−t4]: uo < 0, ioe1 < 0, chopper I is shut

down, chopper II is working, and the inverter is

operating in mode C. S21 is HF chopping, S23 is HF

conducted complementarily, and S15 is conducted.

The source outputs energy to the equivalent load by

chopper II.

The operation modes’ sequence of the proposed

inverter under equivalent inductive load is B-A-D-C.

Similarly, the resistive and capacitive loads are A-C

and A-B-C-D, respectively. A special case is the

resistive load, whose intervals of energy feedback

operation modes B and D are short.

B. SWITCHING STATE EQUATIONS

The equivalent circuits of the proposed inverter in the

positive or negative half cycle of the output voltage

are bidirectional buck–boost dc–dc chopper I and

chopper II separately. Taking one-transistor mode

circuit in Fig. 1(b) as an example, suppose that r1 is

the equivalent resistance including the primary

winding resistance of the HF storage transformer and

the on resistance of S11 (S21); r2 is the equivalent

resistance including the secondary winding resistance

of the HF storage transformer and the on-resistance

of S13 (S23) and S25 (S15); and d is the duty cycle of

S11 (S21). Taking the positive cycle of the output

voltage as an example, the state equation of the

equivalent circuit in dTs is given by

⎩⎨

⎧퐿푑푖푑푡 = 푈 − 푟 푖

퐶푑푢푑푡 = −

푢푅

(1)

푐e state equation in (1 − d)Ts is given by

⎩⎨

⎧퐿푑푖푑푡 = −푢 − 푟 푖

퐶푑푢푑푡 = 푖 −

푢푅

(2)

By multiplying (1) by d and then adding the result of

multiplying (2) by (1 − d), assuming (dii1/dt) = 0,

(dio1/dt) = 0, (duo/dt) = 0, L1/L2 = (N1/N2) 2, N1Ii1

= N2Io1, r1/r2 = (N1/N2) 2, and RL = Uo/Io, the

steady-state values of the state variables are given by

푈 = −( )

(3)

퐼 =( )

(4)

Similarly, the current is derived by

퐼 =( )

(5)

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IJRAET

C. STEADY OUTPUT CHARACTERISTICS

Because S11 (S21) and S13 (S23) are HF

conducted complementarily, there is only continuous

current mode (CCM). The primary inductance current

has three kinds of situations: the initial value is

greater than zero; the initial value is less than zero

and the final value is greater than zero; and the initial

and final values are both less than zero. Since the

inductance current only has CCM, the ideal steady

(r1 = r2 = 0) output characteristic of the inverters is

given by

푈 = 푈 (6)

When the initial value of the primary inductance

current is zero, the load current is

퐼 = 퐼 = ( ) (7)

Fig 4 Rated output characteristics of the proposed

inverter.

IG is maximal when D = 1/2 from the

aforesaid equation. The maximum of IG is

퐼 = (8)

From (6) and (8), when the initial value of the

primary inductance current is equal to zero, the ideal

output characteristic of the proposed inverter is

derived

퐼 = 4퐼 퐷(1 −퐷) (9)

The rated output characteristics uo/(UiN2/N1) =

f(io/IG max) of the proposed inverter is shown in Fig.

4. When uo > 0 the output characteristic curve is in

the upper half-plane of Fig 4 D is the duty cycle of

chopper I. When uo < 0, the curve is in the lower

half-plane. D is the duty cycle of chopper II. Taking

the first quadrant for instance, curve A, determined

by (9), represents the output characteristics at zero

initial inductance current. The curves at the left and

right sides of A are the output characteristics at less

than and greater than zero of the initial inductance

current separately. The solid and dashed lines,

determined by (6) and (3), show the ideal and actual

states, respectively. uo decreases with increasing load

current. It shows that the proposed inverter has the

ability of working at four quadrants with strong

adaptability to various loads.

RESTRAINT OF TURN-OFF VOLTAGE

PEAKS OF POWER S WITCHES

A. BUCK-MODE ACTIVE CLAMPED CIRCUIT

A new buck-mode active clamped circuit is

proposed to restrain the turn-off voltage peaks of S11

and S21, as shown in Fig. 5, which is composed of

Dc1, Dc2, and Dc, clamped capacitance Cc, clamped

switch Sc, filtering inductance Lc, and Ci. Two

snubber circuits consisting of R13 and C13, R23 and

C23, respectively, restrain the turn-off voltage peaks

of S13 and S23. When the inverter is transmitting

power flow at the positive and negative directions,

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IJRAET

voltage peaks caused by leakage inductance exist in

S11 (S12) after being turned off in every switching

Fig 5 Buck-mode active clamped circuit of the

proposed inverter .

cycle, which can make Dc1 (Dc2)

conductive. In addition, the leakage inductance

energy of T1 charges Cc. When the terminal voltage

of Cc increases to a set value, Sc is conducted and the

energy of Cc feeds back to Ui. Meanwhile, the

terminal voltage of Cc decreases. Thus, it realizes

energy regeneration of the leakage inductance

energy. The buck-mode active clamped circuit is a

lossless circuit. When the inverter feeds energy back,

the clamped circuit will not affect the normal

operation of the inverter. Taking chopper I working

in energy-regeneration state, i.e., uo > 0, io < 0, as an

example, when S13 is on, S11 is off and the

homonymous end voltages of T1’s primary and

secondary windings are negative. Moreover, a very

small part of the energy, which is stored by T1’s N2,

is coupled to N1 and feeds energy back to Cc via

DC1, CC, and Ci (Ui and Li). When the terminal voltage of CC increases to a set value, Sc is

conducted and the energy of Cc feeds back to Ui.

When S13 is off, S11 is on and most of the energy

stored by N2 of T1 is coupled to N1 and feeds energy

back to the input supply. So, when the inverter is

working with positive and negative power flows, the

turn-off voltage peaks of S11 (S21) are inhibited by

the clamped circuit efficiently. In addition, when the

inverter feeds energy back, it will not affect the

inverter’s normal operation and the output waveform

quality.

B. ANALYSIS OF HF SWITCHES’

OPERATING PROCESS

Taking chopper I as an example, under an entirely

positive power flow, when iLc is continuous, the

principle waveforms of one Ts includes ten intervals,

as shown in Fig. 6. t = t0−t1: Sc is turned off at t0. Cc

stops to release energy, and its voltage stays constant.

iLc freewheels via Dc and decreases linearly, and its

energy feeds back to the source. udsc increases to

Cc’s voltage value then stays constant. t = t1−t2: S11

is turned off at t1. S11’s junction capacitor is

charging. The terminal voltage uds11 and ii1

increase. t = t2−t3: uds11 increases to Ui at t2. Since

then, uds11 continues to increase while uds13

decreases. The primary winding voltage u11 is

negative. ii1 decreases positively, and io1 increases

from zero. The voltage peak of uds11 caused by

the resonance between the leakage inductance and

S11’s junction capacitance is bigger than UoN1/N2 +

Ui, which makes Dc1 positively turned on. The

leakage energy is passed to Cc via Dc1. uCc and udsc

increase until Dc1 is reversely turned off.

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Fig. 6. Principle waveforms of one Ts under positive

power flow.

t = t3−t4: uds13 decreases to zero at t3. ii1 decreases

to zero. io1 flows through S13’s body diode and

starts to decrease positively. The stored energy of T1

releases to the load via S13’s body diode. t = t4−t5:

S13 is turned on at t4. When S13’s voltage drop is

smaller than that of the body diode, S13 realizes

ZVS. T1 releases energy to the output via S13. io1

continues to decrease positively, and iLc continues to

freewheel via Dc. t = t5−t6: S13 is turned off at t5.

T1 releases energy to the output via S13’s body

diode. io1 continues to decrease positively. t = t6−t7:

S11 is turned on at t6. uds11 decreases rapidly. The

primary winding voltage u11 of T1 is positive. ii1

starts to positively increase from zero, and io1 rapidly

decreases. t = t7−t8: io1 decreases to zero at t7. S13’s

body diode is turned off. The secondary winding

voltage u12 of T1 is negative. S13’s junction

capacitor and Cs13 are charged by the output voltage

and the secondary inductance voltage. Leakage

energy causes voltage peaks on uds13. io1 increases

negatively. ii1 increases positively and the current

peak appears in ii1. t = t8−t9: io1 negatively

decreases to zero at t8. The source and T1 form a

loop through S11. T1 stores energy, and ii1 increases

positively. t = t9−t10: Sc is turned on at t9. Cc starts

to discharge via Sc and Lc. The stored energy of Cc is

fed back to the source. udsc rapidly decreases to zero.

iLc starts to linearly increase. Sc is turned off at t10.

Moreover, the next HF switching period begins.

DESIGN CRITERIA OF THE KEY

CIRCUIT PARAMETERS

A. HF STORAGE TRANSFORMER TURN

RATIO

When input voltage Ui = Ui min, D = Dmax and the

peak output voltage uo = √2Uorms, determined by

(6). The turns ratio of the HF storage transformer is

given by

= √ ( )

(10)

B. CURRENT STRESS OF POWER SWITCHES

From (6), the variation law of duty cycle d is derived

by

푑(푡) = √/ √

(11)

The current flowing through S11 (S12) is the primary

inductance current of the HF storage transformer.

The peak, instantaneous, and effect values,

respectively, are

퐼 (푛)= ( )( )

+ ( ) (12)

푖 (푡) = 퐼 (푛) −퐷(푛)푇 푈

퐿

+푈퐿

[푡 − (푛 − 1)푇 ]

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(푛 − 1)푇 ≤ 푡 ≤ (푛 − 1)푇 + 퐷(푛)푇

(13)

퐼 (푛)

=1푇

푖 (푡) 푑푡

( ) ( )

( )

. (14)

In (12), ηn is the conversion efficiency of the nth

switching period. The effect value of ii1 in one LF

cycle is

퐼 =1푇

퐼 (푛)/

푇 (15)

where N = To/Ts is the number of the HF switching

periods in one LF cycle To. The current of S13 (S25)

is the secondary inductance current of the HF storage

transformer, the same with the current of switch S23

(S15). The peak, instantaneous, and effect values in

the nth Ts are, respectively, given by

퐼 (푛) =푁푁

퐼 (푛) (16)

푖 (푡) = 퐼 (푛)

−푈 (푛)퐿

[푡 − (푛 − 1)푇

− 퐷(푛)푇 ]

(푛 − 1)푇 + 퐷(푛)푇 < 푡 < 푛푇 (17)

퐼 (푛)

=1푇

푖 (푡) 푑푡( ) ( )

. (18)

The effect value of io1 in one LF cycle is calculated

[refer to (15)].

C. DESIGN OF BUCK-MODE ACTIVE

CLAMPED CIRCUIT

Every switching period, the stored energy of

the primary leakage inductance lleak1 of the HF

transformer is absorbed by

Fig. 7. Control circuit of active clamped switch Sc.

the junction capacitor Cs of S11 (S21) and Cc,

namely

12

(퐶 + 퐶 )푈 푓 =12퐶 푈 푓

=12푙 퐼 푓 (19)

In (19), UCc1 and UCc2 are, respectively, the before

and after-charging voltages of Cc in every Ts. The

maximum drain–source voltage of S11 (S21) can be

limited to √2UormsN1/N2 + Ui max when Cc is large

enough. Thus, Cc is given by

퐶

=푙 퐼 − 퐶 √2푈 푁

푁 + 푈

√2푈 푁푁 + 푈 − 푈

(20)

where UCc1 max is 0.9 ∼ 0.95(√2UormsN1/N2 + Ui

max) and it usually needs to be adjusted in the test.

D. VOLTAGE AND CURRENT STRESSES OF

ACTIVE CLAMPED SWITCH

The voltage stress of the switch SC is given by

푢 ≥푁푁

√2푈 + 푈 (21)

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The current stress of SC can be approximately

calculated by the feedback energy and clamped

capacitor voltage.

E. CONTROL OF ACTIVE CLAMPED

SWITCH SC

The control circuit of the clamped switch Sc is shown

in Fig. 7. The constant-frequency clock signal with

fixed duty cycle is generated by comparing the

triangle carrier signal uc with the dc reference

voltage ub. When the sampling signal kuCc (k is the

voltage-dividing coefficient) of the clamped capacitor

voltage is higher than the set value ub, the control

signal ugsc of SC can be obtained; if not, SC will shut

down. ub should be set according to the maximum of

Ui and uo and is given by

푈 =푁푁

√2푈 + 푈 ×1

50 (22)

FUZZY LOGIC CONTROLLER

In FLC, basic control action is determined

by a set of linguistic rules. These rules are

determined by the system. Since the numerical

variables are converted into linguistic variables,

mathematical modeling of the system is not required

in FC. The FLC comprises of three parts:

fuzzification, interference engine and defuzzification.

The FC is characterized as i. seven fuzzy sets for

each input and output. ii. Triangular membership

functions for simplicity. iii. Fuzzification using

continuous universe of discourse. iv. Implication

using Mamdani’s, ‘min’ operator. v. Defuzzification

using the height method.

Fuzzification: Membership function values are

assigned to the linguistic variables, using seven fuzzy

subsets: NB (Negative Big), NM (Negative Medium),

NS (Negative Small), ZE (Zero), PS (Positive Small),

PM (Positive Medium), and PB (Positive Big). The

Fig.(a) Fuzzy logic controller

partition of fuzzy subsets and the shape of

membership CE(k) E(k) function adapt the shape up

to appropriate system. The value of input error and

change in error are normalized by an input scaling

factor.

TABLE I

FUZZY RULES

Change

in error

Error

NB NM NS Z PS PM PB

NB PB PB PB PM PM PS Z

NM PB PB PM PM PS Z Z

NS PB PM PS PS Z NM NB

Z PB PM PS Z NS NM NB

PS PM PS Z NS NM NB NB

PM PS Z NS NM NM NB NB

PB Z NS NM NM NB NB NB

In this system the input scaling factor has been

designed such that input values are between -1 and

+1. The triangular shape of the membership function

of this arrangement presumes that for any particular

E(k) input there is only one dominant fuzzy subset.

The input error for the FLC is given as

E(k) = ( ) ( )

( ) ( ) (10)

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CE(k) = E(k) – E(k-1) (11)

Fig.(b) Membership functions

Inference Method: Several composition methods

such as Max–Min and Max-Dot have been proposed

in the literature. In this paper Min method is used.

The output membership function of each rule is given

by the minimum operator and maximum operator.

Table 1 shows rule base of the FLC.

Defuzzification: As a plant usually requires a non-

fuzzy value of control, a defuzzification stage is

needed. To compute the output of the FLC, „height‟

method is used and the FLC output modifies the

control output. Further, the output of FLC controls

the switch in the inverter. In UPQC, the active power,

reactive power, terminal voltage of the line and

capacitor voltage are required to be maintained. In

order to control these parameters, they are sensed and

compared with the reference values. To achieve this,

the membership functions of FC are: error, change in

error and output

The set of FC rules are derived from

u=-[αE + (1-α)*C]

Where α is self-adjustable factor which can regulate

the whole operation. E is the error of the system, C is

the change in error and u is the control variable. A

large value of error E indicates that given system is

not in the balanced state. If the system is unbalanced,

the controller should enlarge its control variables to

balance the system as early as possible. One the other

hand, small value of the error E indicates that the

system is near to balanced state. Overshoot plays an

important role in the system stability. Less overshoot

is required for system stability and in restraining

oscillations. During the process, it is assumed that

neither the UPQC absorbs active power nor it

supplies active power during normal conditions. So

the active power flowing through the UPQC is

assumed to be constant. The set of FC rules is made

using Fig.(b) is given in Table 1.

PRINCIPLE TEST The designed prototype: input voltage Ui =

40−60 V, output voltage Uo = 220 V/50 Hz, rated

capacity S = 750 VA, switching frequency fs = 50

kHz, maximum duty cycle D max = 0.65, soft ferrites

core LP3 PM 62 × 49 for T1, T2 (N2/N1 = 34/8), air

gap of 3.8 mm, input filtering capacitor Ci = 6 ×

2200 μF, output filtering capacitor Cf = 9.4 μF,

clamped capacitor Cc = 0.47 μF, clamped inductor

(a)

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(b)

(c)

(d)

(e)

(f)

Fig. 8. Experimental waveforms of the proposed

inverter under rated input voltage and different rated

loads. (a) Driving voltage ugs 11 (ugs 2 1 ) and

drain–source voltage uds 11 uds 2 1 of S11 (S21 ) in

the LF period.. (b) ugs13 (ugs23) and uds13 (uds23 )

of S13 (S23 ) in the LF period. (c) ugs15 (ugs25 ) and

uds15 (uds25 ) of S15 (S25 ) in Ts. (d) u11 of T1 in

the LF period. (e) uCc and u o. (f) u o and io at rated

resistive load. Lc = 300 μH, snubber capacitor C13 =

C23 = 1 nF, snubber resistance R13 = R23 = 100 Ω,

MOSFET IXFH80N20Q for S11 (S21), IGBT

IRP4PF50WD for S13 (S23), MOSFET FQA30N40

for S15 (S25), MOSFET IRF630 for SC, and

Schottky diodes STTH8R06D for Dc1, Dc2, and Dc.

The experimental waveforms of the inverter under

rated input voltage Ui = 48 VDC and rated load are

shown in Fig. 8. The envelope curve of the drain–

source voltage uds11 (uds21) of S11 (S21) in the half

LF cycle is the input dc voltage Ui of the half LF

period and Ui + uoN1/N2 of the half LF period, and

the drain-source voltage peaks are effectively

inhibited by the buck-mode active clamped circuit, as

shown in Fig. 8(a) and (b). The envelope curve of the

drain-source voltage uds13 (uds23) of S13 (S23) in

the half LF cycle is the zero voltage of the

half LF period and uo + UiN1/N2 of the half LF

period. The drain-source voltage peaks are inhibited

quiet well by an RC snubber circuit, as shown in Fig.

8(c) and (d). The envelope curve of the drain-source

voltage uds15 (uds25) of S15 (S25) in the half LF

cycle is the zero voltage of the half LF period and uo

of the half LF period, as shown in Fig. 8(e). The

envelope curve of the primary winding voltage u11

(u21) of the T1 (T2) in the half LF cycle is zero of the

half LF period and the bipolar two-state pulse (+Ui

and −uoN1/N2) of the half LF period, as shown in

Fig. 8(f). The driving voltage ugsc and drain-source

Volume 4, Issue 5 SEP 2015

IJRAET

voltage udsc of Sc are shown in Fig. 8(g).

The clamped capacitor voltage uCc is shown in Fig.

8(h). The output waveforms of the inverter under

rated input voltage and rated load have high quality,

as shown in Fig. 8(i). The maximum conversion

efficiency and THD are 91.3% and 1.3%,

respectively. The inverter has strong ability to adapt

to different nature load. The performance comparison

between the proposed inverter and other inverters

[9]–[12] is shown in Table II. In Table II, N1 and N2

or N3 and N4 separately represent the turns of the

primary and secondary windings of the HF

transformer. D represents the duty cycle of the

inverter, D1 and D2 separately represent the duty

cycle of the former and later stages in the two-stage

inverter. Therefore, the proposed and developed

inverter with HFL has higher conversion efficiency

due to its single-stage power conversion, lower total

harmonic distortion of the output voltage, and larger

output power than those of inverters with HFL [9],

[10], [12]. Moreover, it has higher conversion ratio

and efficiency than the inverter with HF pulse dc link

[11]. However, the proposed inverter has the

disadvantage that the utilization factor of each

chopper is not high, i.e., 50%.

CONCLUSION

1) The circuit configuration of the proposed inverters

is composed of two identical isolated bidirectional

buck–boost dc–dc choppers in parallel at the input

end and in series at the output end which generate

unipolarity SPWM current with positive and negative

half LF cycles separately.

2) The circuit topological family includes four circuit

topologies and adopts the instantaneous output

voltage feedback control strategy.

3) The inverter has four operation modes in the LF

cycle.

4) The steady principle characteristic curve and the

key circuit parameters of the inverter are obtained.

5) The turn-off voltage peaks are inhibited by the

active clamped circuit and improve the conversion

efficiency.

6) Theoretical analysis and experimental results have

shown the inverters have advantages of HF galvanic

isolation, simple topology, single-stage power

conversion, high efficiency, strong adaptability to

various loads, etc with fuzzy logic controller.

REFERENCES

[1] J. M. Alonso, J. Vina, D. G. Vaquero, G.

Martinez, and R. Osorio, “Analysis and design of the

integrated double buck–boost converter as a high

power-factor driver for power-LED lamps,” IEEE

Trans. I nd. Electron., vol. 59, no. 4, pp. 1689–1697,

Apr. 2012.

[2] E. Babaei, M. E. Seyed Mahmoodieh, and H.

Mashinchi Mahery, “Operational modes and output-

voltage-ripple analysis and design considerations of

buck–boost DC–DC converters,” IEEE Trans. I nd.

Electron., vol. 59, no. 1, pp. 381–391, Jan. 2012.

[3] F. Fongang Edwin, W. Xiao, and V. Khadkikar,

“Dynamic modeling and control of interleaved

flyback module-integrated converter for PV power

applications,” IEEE Trans. I nd. Electron., vol. 61,

no. 3, pp. 1377–1388, Mar. 2014.

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IJRAET

[4] Y.-H. Kim, Y.-H. Ji, J.-G. Kim, Y.-C. Jung, and

C.-Y. Won, “A new control strategy for improving

weighted efficiency in photovoltaic AC module type

interleaved flyback inverters,” IEEE Trans. Power

Electron., vol. 28, no. 6, pp. 2688–2699, Jun. 2013.

[5] S. H. Kang, D. Maksimovic, and I. Cohen,

“Efficiency optimization in digitally controlled fly

back DC–DC converters over wide ranges of

operating conditions,” IEEE Trans. Power Electron.,

vol. 27, no. 8, pp. 3734–3748, Aug. 2012. [6] H.

Seong, H. Kim, K. Park, G. Moon, and M. Youn,

“High step-up DC–DC converters using zero-voltage

switching boost integration technique and light-load

frequency modulation control,” IEEE Trans. Power

Electron., vol. 27, no. 3, pp. 1383–1400, Mar. 2012.

[7] G. Stahl, M. Rodriguez, and D. Maksimovic, “A

high-efficiency bidirectional buck–boost DC–DC

converter,” in Proc. IEEE 27th Annu. APEC,

Orlando, Feb. 5–9, 2012, pp. 1362–1367.

[8] K.-M. Yoo and J. Lee, “A 10-kW two-stage

isolated/bidirectional DC/DC converter with hybrid-

switching technique,” IEEE Trans. Ind. Electron.,

vol. 60, no. 6, pp. 2205–2213, Jun. 2013.

[9] T. Shimizu, K. Wada, and N. Nakamura,

“Flyback-type single-phase utility interactive inverter

with power pulsation decoupling on the DC input for

an AC photovoltaic module system,” IEEE Trans.

Power Electron., vol. 21, no. 5, pp. 1264–1272, Sep.

2006.

[10] N. Vazquez, J. Villegas-Saucillo, C. Hernandez,

E. Rodriguez, and J. Arau, “Two-stage

uninterruptible power supply with high power

factor,” IEEE Trans. Ind. Electron., vol. 55, no.

8, pp. 2954–2962, Aug. 2008. [11] D. Chen, “Parallel inverters with high frequency

pulse DC Link,” in Proc. IEEE APEC, Austin, TX,

USA, Feb. 24–28, 2008, pp. 1623–1627.

[12] D. Chen, “Novel current-mode AC–AC

converters with HF AC link,” IEEE Trans. Ind.

Electron., vol. 55, no. 1, pp. 30–37, Jan. 2008.

AADEPU SATHEESH

Completed B.Tech in Electrical & Electronics

Engineering in 2013 from Medak College of

Engineering and Technology Affiliated to JNTU

,Hyderabad and M.Tech in Power electronics in

2015(pursuing) from ST.MARTIN’S Engineering

College, Dhulapally, Hyderabad. His current research

Interests include simulation of Multilevel inverter.

E-mail id:

satheesh.aadepu@gmail.com

Mr. K. SHANKER Currently

working as Assistant Professor in

Department of Electrical & Electronics Engineering

St. Martin’s Engineering College, Hyderabad,

Telangana, India. He has completed his B. Tech.

Electrical and Electronics Engineering, in 2006

from CVSR College of Engineering, and M. Tech in

2010 from Gokaraju Rangaraju Institute of

Engineering and Technology, Hyderabad. His area

of interest includes Power electronics and Drives.

E-mail id: kethavath.shanker@gmail.com