KOLA ZA REALIZACIJUOSNOVNOH ARITMETIČKIH

OPERACIJA

ARITMETIČKA KOLA

Binary Adder-Subtractor

• Half adder– 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10

– two input variables: x, y

– two output variables: C (carry), S (sum)

– truth table x y C S0 0 0 00 1 0 11 0 0 11 1 1 0

S = x'y+xy'C = xy

the flexibility for implementation

S=x⊕y

S = (x+y)(x'+y')

S' = xy+x'y'S = (C+x'y')'

C = xy = (x'+y')'

• Full-Adder– The arithmetic sum of three

input bits

– three input bits• x, y: two significant bits

• z: the carry bit from the previous lower significant bit

– Two output bits: C, S

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

C

S = x'y'z+x'yz'+ xy'z'+xyzC = xy + xz + yz =xy + (x+y)z

S = z⊕ (x⊕y)= z'(xy'+x'y)+z(xy'+x'y)'= z'xy'+z'x'y+z((x'+y)(x+y'))= xy'z'+x'yz'+xyz+x'y'z

C = z(xy'+x'y)+xy= xy'z+x'yz+ xy

Binary adder - Ripple-Carry Adder

• Carry propagation– when the correct outputs are available

– the critical path counts (the worst case)

– (A0,B0,C0) > C1 > C2 > C3 > (C4,S3)

– > 8 gate levels

tadder = (N-1)tcarry + tsum

• Reduce the carry propagation delay– employ faster gates

– look-ahead carry (more complex mechanism, yet faster)

– carry propagate: Pi = Ai⊕Bi Pi = Ai+Bi

– carry generate: Gi = AiBi

– sum: Si = Pi⊕Ci

– carry: Ci+1 = Gi+PiCi

– C1 = G0+P0C0

– C2 = G1+P1C1 = G1+P1(G0+P0C0) == G1+P1G0+P1P0C0

– C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

POTPUNI SABIRAČMODIFIKOVANE ARHITEKTURE

iii bag ⋅= iii bap +=

iiii cgps ⊕⋅= ( )iiii cgpc +⋅=+1

LookAhead- Basic Idea

Co k, f A k Bk Co k, 1–, ,( ) Gk PkCo k 1–,+= =

AN-1, BN-1A1, B1

P1

S1

• • •

• • • SN-1

PN-1Ci, N-1

S0

P0Ci,0 Ci,1

A0, B0

– Logic diagram

• 4-bit carry-look ahead adder– propagation delay

ČETVOROBITNI SABIRAČ SA CLA(PARALELNIM PRENOSOM)

Look-Ahead: Topology

Co k, Gk Pk Gk 1– Pk 1– Co k 2–,+( )+=

Co k, Gk Pk Gk 1– Pk 1– … P1 G0 P0Ci 0,+( )+( )+( )+=

Expanding Lookahead equations:

All the way:

Co,3

Ci,0

VDD

P0

P1

P2

P3

G0

G1

G2

G3

Binary subtractor• A-B = A+(2’s complement of B) M=0 : S=A+B;

• 4-bit Adder-subtractor M=1 : S=A+B’+1

• Overflow– The storage is limited

– Add two positive numbers and obtain a negative number

– Add two negative numbers and obtain a positive number

– V=0, no overflow; V=1, overflow

4-5 Decimal Adder

• Add two BCD's– 9 inputs: two BCD's and one carry-in

– 5 outputs: one BCD and one carry-out

• Design approaches– A truth table with 2^9 entries

– use binary full Adders• the sum <= 9+9+1 = 19

• binary to BCD

• The truth table

• Modifications are needed if the sum > 9– C = 1

• K = 1

• Z8Z4 = 1

• Z8Z2 = 1

– modification: -(10)d or +6

• Block diagram

AKUMULACIONI SABIRA Č

AKUMULATOR R.

FUNKCIJE ARITMETIČKO-LOGIČKE JEDINICE (ALU SN74181

LOGIČKA ŠEMA ALU SN74181

Multipliers

A * B = A+A+A+A+A+A+ … +A

B puta se dodaje A

Višestruko sabiranje – B puta se dodaje A

Množač realizovan akumulacionim sabiranjem

Binary MultiplierPartial products – AND operations

The Binary Multiplication

x

+

Partial products

Multiplicand

Multiplier

Result

1 0 1 0 1 0

1 0 1 0 1 0

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 1

The Array Multiplier (X4b*Y 4b)

Y0

Y1

X3 X2 X1 X0

X3

HA

X2

FA

X1

FA

X0

HA

Y2X3

FA

X2

FA

X1

FA

X0

HA

Z1

Z3Z6Z7 Z5 Z4

Y3X3

FA

X2

FA

X1

FA

X0

HA

Z2

Z0

The MxNArray Multiplier— Critical Path

HA FA FA HA

HAFAFAFA

FAFA FA HA

Critical Path 1

Critical Path 2

Critical Path 1 & 2

Wallace-Tree Multiplier

6 5 4 3 2 1 0 6 5 4 3 2 1 0

Partial products First stage

Bit position

6 5 4 3 2 1 0 6 5 4 3 2 1 0

Second stage Final adder

FA HA

(a) (b)

(c) (d)

Wallace-Tree Multiplier

6 5 4 3 2 1 0 6 5 4 3 2 1 0

Partial products First stage

Bit position

6 5 4 3 2 1 0 6 5 4 3 2 1 0

Second stage Final adder

FA HA

(a) (b)

(c) (d)

Wallace-Tree Multiplier

Partial products

First stage

Second stage

Final adder

FA FA FA

HA HA

FA

x3y3

z7 z6 z5 z4 z3 z2 z1 z0

x3y2x2y3

x1y1x3y0 x2y0 x0y1x0y2

x2y2x1y3

x1y2x3y1x0y3 x1y0 x0y0x2y1

TABLICA MNOŽENJA U ROM-u M · N = P

a0

a1

a2

a3

a4

a5

a6

a7

d0

d1

d2

d3

d4

d5

d6

d7

ROM

256*8

m0

m1

m2

m3

n0

n1

n2

n3

p4

p5

p6

p7

p0

p1

p2

p3

N

M

P

Za tablicu množenja dva 8-o bitna broja potreban je ROM kapaciteta 64K*16Za tablicu množenja dva 16-o bitna broja potreban je ROM kapaciteta 4G*32

Constructing Big Mult’s from Small

• Can synthesize a 2b x 2b multiplier from four b x b multipliers and a three operand addition operation

AH AL

BLBH

AL BL

AL BH

BLAH

AH BH

4b product

b bits3b bits

AL BL

AL BH

BLAH

AH BH

Množač 8-o bitnih brojeva realizovan 4-o bitnim tablicama množenja i sabiračima

Redno-paralelni množač

Četvorobitni redno-paralelni množač

Sekvenca rada registara množača

Generator kontrolnih signala prethodnog množača

Kolo za deljenje binarnih brojeva A/B

Primer deljenja binarnih brojeva 1010000 / 0100

Primer deljenja binarnih brojeva 101 / 1000

Table Lookup Arithmetic Def’n

• The u-bit string is obtained by concatenating the input values to form the table address.

• The n-bit value is the contentof the table corresponding to that address.

• Given an m-variable functionf(xm-1, xm-2, …, x1, x0)

the table lookupevaluation of f requires the construction of a 2u x n table that holds, for each combination of input values (needing a total of u-bits to represent), the desired n-bit result.

Arithmetic by Table Lookup• Advantages

– memory is denser and can be made more robust than random logic

– reduces the cost of hardware development

– more flexible (allows last minute design changes)

– reduces the number of building blocks

• Disadvantages– slow for large tables

– table size grows exponentiallyin input size

Direct Table Lookup

• Unary(single variable) functions (1/x, ln x, x2) limited to 12 to 16 bits of operand precision (212

to 216 table)

• Binary functions (xy, x/y, xy) limited to 8 bits of operand precision (28+8=16table)

Operand(s)u bits

Result(s)n bits

2u x nTable

(ROM or RAM)

Indirect Table Lookup

SmallerTable(s)

(ROM or RAM)

PostprocessingLogic

Result(s)n bits

Operand(s)u bits Pr

e-pr

oces

sing

Logi

c

• One way to reduce the table size is to see if the binary function can be converted into a unaryfunction (requires pre- and postprocessing logic)

Much smaller than u !

Constructing Big Mult’s from Small

• Can synthesize a 2b x 2b multiplier from four b x b multipliers and a three operand addition operation

AH AL

BLBH

AL BL

AL BH

BLAH

AH BH

4b product

b bits3b bits

AL BL

AL BH

BLAH

AH BH

Množač 8-o bitnih brojeva realizovan 4-o bitnim tablicama množenja i sabiračima

Indirect Table Lookup Example

• Pre- and postprocessing hardware should be simple and fast

• Consider the multiplication identity that converts the problem to one of squaring

X * Y = ¼ [(X + Y)2 – (X – Y)2]

– Preprocessing does X+Y and X-Y– Two tables to lookup (X+Y)2 and (X-Y)2

– Postprocessing does subtract and 2-bit right shift

Indirect Multiplication

2** ROM(X+Y)2

Right shifter (¼)

X*Y (2n-bits)

X (n-bits)

Y (n-bits)

Subtractor

2** ROM(X-Y)2Subtractor

Adder

Indirect Multiplication

n +1 bits

2ncontentbits

2n+1addr bits

2** ROM(X+Y)2

Right shifter (¼)

X*Y (2n-bits)

X (n-bits)

Y (n-bits)

Subtractor

2** ROM(X-Y)2Subtractor

Adder