binary decision diagrams (bdd)pallab/testing_and_verification/lec-8-bdd.pdf · binary decision...
TRANSCRIPT
Binary Decision Diagrams (BDD)Binary Decision Diagrams (BDD)Binary Decision Diagrams (BDD)
Pallab Pallab DasguptaDasguptaProfessor, Dept. of Computer Science & Professor, Dept. of Computer Science & EnggEngg.,.,ProfessorProfessor--inin--charge, AVLSI Design Lab,charge, AVLSI Design Lab,Indian Institute of Technology KharagpurIndian Institute of Technology Kharagpur
Testing & VerificationDept. of Computer Science & Engg, IIT KharagpurTesting & VerificationTesting & VerificationDept. of Computer Science & Dept. of Computer Science & EnggEngg, IIT Kharagpur, IIT Kharagpur
2© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
ContentsContents
Motivation for Decision diagramsMotivation for Decision diagrams
Binary Decision DiagramsBinary Decision Diagrams
ROBDDROBDD
Effect of Variable Ordering on BDD sizeEffect of Variable Ordering on BDD size
BDD operationsBDD operations
Encoding state machinesEncoding state machines
Reachability Analysis using Reachability Analysis using OBDDsOBDDs
3© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Sample Analysis TaskSample Analysis Task
Logic Circuit ComparisonLogic Circuit Comparison
■■ Do circuits compute identical function?Do circuits compute identical function?
●● Basic task of formal hardware verificationBasic task of formal hardware verification
●● Compare new design to Compare new design to ““known goodknown good”” designdesign
A
CB
O1
T1
T2
ABC
O2
T3
4© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
A
C
BO1
T1
T2
ABC
O2T3
Diff
cc0
A
C
BO1
T1
T2
ABC
O2T3
Diff0
0
0
0
0 00
c1
A
C
BO1
T1
T2
ABC
O2T3
Diff1
1A
C
BO1
T1
T2
ABC
O2T3
Diff1
1
1
1
11
11
0
a
c1
1
Solution by Combinatorial SearchSolution by Combinatorial Search
Satisfiability FormulationSatisfiability Formulation■■ Search for input assignment giving Search for input assignment giving
different outputsdifferent outputs
Branch & BoundBranch & Bound■■ Assign input(s)Assign input(s)■■ Propagate forced valuesPropagate forced values■■ Backtrack when cannot succeedBacktrack when cannot succeed
A
C
BO1
T1
T2
ABC
O2T3
Diff1
1
0
0 0
a
c1
0a
b
c1
0
0
A
C
BO1
T1
T2
ABC
O2T3
Diff1
1
0
00
0
00
0
00
0A
C
BO1
T1
T2
ABC
O2T3
Diff1
1
0
00
1
11
1
11
0
a
b
c1
0
1
ChallengeChallenge
■■ Must prove all assignments failMust prove all assignments fail
■■ Typically explore significant Typically explore significant fraction of inputsfraction of inputs
■■ Exponential time complexityExponential time complexity
5© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Another ApproachAnother Approach
Generate Complete Representation of Circuit FunctionGenerate Complete Representation of Circuit Function■■ Compact, canonical formCompact, canonical form
■■ Functions equal if and only if representations identicalFunctions equal if and only if representations identical■■ Never enumerate explicit function valuesNever enumerate explicit function values■■ Exploit structure & regularity of circuit functionsExploit structure & regularity of circuit functions
A
C
B
O1
T1
T2
ABC
O2
T3
b
0 1
c
a
b
0 1
c
a
6© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Truth Table Decision Tree
■■ Vertex represents decisionVertex represents decision■■ Follow green (dashed) line for value 0Follow green (dashed) line for value 0■■ Follow red (solid) line for value 1Follow red (solid) line for value 1■■ Function value determined by leaf value.Function value determined by leaf value.
00001111
00110011
01010101
00010101
x1 x2 x3 f
Decision StructureDecision Structure
0 0
x3
0 1
x3
x2
0 1
x3
0 1
x3
x2
x1
7© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Binary Decision DiagramBinary Decision Diagram
DAG representation of Boolean functions DAG representation of Boolean functions
Operations on Boolean functions can be implemented as Operations on Boolean functions can be implemented as graph algorithms on BDDsgraph algorithms on BDDs
Tasks in many problem domains can be expressed entirely Tasks in many problem domains can be expressed entirely in terms of BDDs in terms of BDDs
BDDs have been useful in solving problems that would not BDDs have been useful in solving problems that would not be possible by more traditional techniques.be possible by more traditional techniques.
8© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Binary Decision Diagram (BDD)Binary Decision Diagram (BDD)
Each nonEach non--terminal vertex terminal vertex vv is labeled by a variable is labeled by a variable var(vvar(v)) and and has arcs directed toward two children has arcs directed toward two children ■■ lo(vlo(v)) (dotted line) corresponding to the case where the (dotted line) corresponding to the case where the
variable is assigned 0variable is assigned 0■■ hi(vhi(v)) (solid line) where the variable is assigned 1(solid line) where the variable is assigned 1
Each terminal vertex is labeled as 0 or 1Each terminal vertex is labeled as 0 or 1
For a given assignment to the variables, the value of the For a given assignment to the variables, the value of the function is determined by tracing the path form root to a function is determined by tracing the path form root to a terminal vertex, following the branches appropriatelyterminal vertex, following the branches appropriately
9© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
BDDsBDDs and Shannon’s Expansionand Shannon’s Expansion
ShannonShannon’’s Expansion: s Expansion: f = f = xfxfxx + + xx′′ffxx′′
BDD represents recursive application of ShannonBDD represents recursive application of Shannon’’s expansions expansion
ffxx′′ fx
x
f
10© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
■■ Assign arbitrary total ordering to variablesAssign arbitrary total ordering to variables●● e.g. e.g. xx11 < < xx22 < < xx33
■■ Variables must appear in ascending order along all Variables must appear in ascending order along all pathspaths
OK Not OK
PropertiesNo conflicting variable assignments along pathSimplifies manipulation
Ordered Binary Decision Diagram (OBDD)Ordered Binary Decision Diagram (OBDD)
x3
x2
x1
x1
x3
x1
x2
x3
x1
x3
11© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Merge equivalent leavesMerge equivalent leaves
0 0 0
Eliminate all but one terminal vertex with a given label and redirect
all arcs into the eliminated verticesto the remaining
Reduction Rule #1Reduction Rule #1
0 0
x3
0 1
x3
x2
0 1
x3
0 1
x3
x2
x1
x3 x3
x2
x3
0 1
x3
x2
x1
12© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
y
x
z
x
Merge isomorphic nodesMerge isomorphic nodes
y
x
z
x
y
x
z
x
If non-terminal vertices u and v havevar(u) = var(v), lo(u) = lo(v) andhi(u) = hi(v), eliminate one of themand redirect all incoming arcsto the other
Reduction Rule #2Reduction Rule #2
x3 x3
x2
x3
0 1
x3
x2
x1
x3
x2
0 1
x3
x2
x1
13© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Eliminate Redundant TestsEliminate Redundant Tests
y
x
y
If non-terminal vertex v haslo(v) = hi(v), eliminate v and
redirect all incoming arcs to lo(v)
Reduction Rule #3Reduction Rule #3
x3
x2
0 1
x3
x2
x1
x2
0 1
x3
x1
14© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Initial GraphInitial Graph Reduced GraphReduced Graph
Canonical representation of Boolean functionCanonical representation of Boolean function
For the same variable ordering, two functions equivalent if and For the same variable ordering, two functions equivalent if and only if only if graphs isomorphicgraphs isomorphic
●● Can be tested in linear timeCan be tested in linear time
(x1+x2)· x3
Reduced OBDD (ROBDD)Reduced OBDD (ROBDD)
0 0
x3
0 1
x3
x2
0 1
x3
0 1
x3
x2
x1
x2
0 1
x3
x1
15© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
ConstantsConstantsUnique unsatisfiable function
Unique tautology1
0
VariableVariable
Treat variableas function
Odd Parity
Linearrepresentation
Typical Function(x1 ∨ x2 ) ∧ x4
No vertex labeled x3
independent of x3
Many subgraphs shared
Some Example FunctionsSome Example Functions
x2
0 1
x4
x1
0 1
x
x2
x3
x4
10
x4
x3
x2
x1
16© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
b3 b3
a3
Cout
b3
b2 b2
a2
b2 b2
a2
b3
a3
S3
b2
b1 b1
a1
b1 b1
a1
b2
a2
S2
b1
a0 a0
b1
a1
S1
b0
10
b0
a0
S0
FunctionsFunctions■■ All outputs of 4All outputs of 4--bit adderbit adder■■ Functions of data inputsFunctions of data inputs
A
B
Cout
SADD
Shared RepresentationShared Representation■■ Graph with multiple rootsGraph with multiple roots■■ 31 nodes for 431 nodes for 4--bit adderbit adder■■ 571 nodes for 64571 nodes for 64--bit adderbit adder■■ Linear GrowthLinear Growth
Circuit FunctionsCircuit Functions
17© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Good OrderingGood Ordering Bad OrderingBad Ordering
Linear Growth0
b 3
a 3
b 2
a 2
1
b 1
a 1
Exponential Growth
a3 a3
a2
b1 b1
a3
b2
b1
0
b3
b2
1
b1
a3
a2
a1
(a1 < b1 < a2 < b2 < a3 < b3) (a1 < a2 < a3 < b1< b2 < b3)
Effect of Variable Ordering on ROBDD SizeEffect of Variable Ordering on ROBDD Size
)()()( 332211 bababa ∧∨∧∨∧
18© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
K = 2 K = n
0
b3
a3
b2
a2
1
b1
a1
a3 a3
a2
b1 b1
a3
b2
b1
0
b3
b2
1
b1
a3
a2
a1
Analysis of Ordering ExampleAnalysis of Ordering Example
)()()( 332211 bababa ∧∨∧∨∧
19© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Selecting a good Variable OrderingSelecting a good Variable Ordering
Intractable ProblemIntractable Problem
■■ Even when problem represented as OBDDEven when problem represented as OBDD
A good variable ordering should useA good variable ordering should use
■■ Local computabilityLocal computability
■■ Ordering based on power to control outputOrdering based on power to control output
ApplicationApplication--Based HeuristicsBased Heuristics
■■ Exploit characteristics of applicationExploit characteristics of application
●● Ordering for functions of combinational circuitOrdering for functions of combinational circuit
●● Traverse circuit graph depthTraverse circuit graph depth--first from outputs to first from outputs to inputsinputs
●● Assign variables to primary inputs in order Assign variables to primary inputs in order encounteredencountered
20© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Dynamic Variable OrderingDynamic Variable Ordering
RudellRudell, ICCAD , ICCAD ‘‘9393
ConceptConcept■■ Variable ordering changes as computation progressesVariable ordering changes as computation progresses
●● Typical application involves long series of BDD Typical application involves long series of BDD operationsoperations
■■ Proceeds in background, invisible to userProceeds in background, invisible to user
ImplementationImplementation■■ When approach memory limit, attempt to reduceWhen approach memory limit, attempt to reduce
●● Garbage collect unneeded nodesGarbage collect unneeded nodes●● Attempt to find better order for variablesAttempt to find better order for variables
■■ Simple, greedy reordering heuristicsSimple, greedy reordering heuristics
21© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
a3
b2 b2
a3
a2
a3
b1
b2
0
b3
b1
1
b2
a3
a2
a1
a3
b2
b3
b2
a3
a2
a3
b2
0
b1
b3
1
b2
a3
a2
a1
a2
a3
b1
b2
0
b3
b2
a3
1
b1
a2
a1
a3
b2
0
b3
b2
a3
a2
1
b1
a1
a3 a3
a2
b1 b1
a3
b2
b1
0
b3
b2
1
b1
a3
a2
a1
• • • a3
b2
0
b3
b2
a3
a2
1
a1
b1
BestChoices
Dynamic Reordering By SiftingDynamic Reordering By Sifting
■■ Choose candidate variableChoose candidate variable■■ Try all positions in orderingTry all positions in ordering
●● Repeatedly swap with adjacent variableRepeatedly swap with adjacent variable■■ Move to best position foundMove to best position found
22© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Function ClassFunction Class BestBest WorstWorst Ordering SensitivityOrdering SensitivityALU (Add/Sub)ALU (Add/Sub) linearlinear exponentialexponential HighHighSymmetricSymmetric linearlinear quadraticquadratic NoneNoneMultiplicationMultiplication exponentialexponential exponentialexponential LowLow
General ExperienceGeneral Experience■■ Many tasks have reasonable OBDD representationsMany tasks have reasonable OBDD representations■■ Algorithms remain practical for up to 100,000 node Algorithms remain practical for up to 100,000 node OBDDsOBDDs■■ Heuristic ordering methods generally satisfactoryHeuristic ordering methods generally satisfactory
Sample Function ClassesSample Function Classes
23© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
BDD OperationsBDD Operations
StrategyStrategy■■ Represent data as set of Represent data as set of OBDDsOBDDs
●● Identical variable orderingsIdentical variable orderings■■ Express solution method as sequence of symbolic operationsExpress solution method as sequence of symbolic operations■■ Implement each operation by OBDD manipulationImplement each operation by OBDD manipulation
Algorithmic PropertiesAlgorithmic Properties■■ Arguments are Arguments are OBDDsOBDDs with identical variable orderings.with identical variable orderings.■■ Result is OBDD with same ordering.Result is OBDD with same ordering.■■ ““Closure PropertyClosure Property””
24© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
The APPLY OperationThe APPLY Operation
Given argument functions f and g, and a binary operator <op>, Given argument functions f and g, and a binary operator <op>, APPLY returns the function APPLY returns the function f <op> gf <op> g
Works by traversing the argument graphs depth first Works by traversing the argument graphs depth first
Algebraic operations Algebraic operations ““commutecommute”” with the Shannon expansion with the Shannon expansion for any variable xfor any variable x■■ f <op> g = xf <op> g = x’’ (f|(f|x=0x=0 <op> g|<op> g|x=0x=0 ) + x ((f|) + x ((f|x=1x=1 <op> g|<op> g|x=1x=1))
25© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
The Apply AlgorithmThe Apply Algorithm
Consider a function f represented by a BDD with root vertex Consider a function f represented by a BDD with root vertex rrff
The restriction of f with respect to a variable x such that The restriction of f with respect to a variable x such that x x ≤≤ var(var(rrff) can be computed as :) can be computed as :
f | f | x = bx = b = r= rff , x , x < < var(var(rrff ))
= lo(r= lo(rff), ), x = x = varvar (r(rff) and b = 0) and b = 0
= hi(r= hi(rff), ), x = x = varvar (r(rff) and b = 1) and b = 1
The algorithm for APPLY utilizes the above restriction definitioThe algorithm for APPLY utilizes the above restriction definition.n.
26© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
The Apply AlgorithmThe Apply Algorithm
Each evaluation step is identified by a vertex from each of the Each evaluation step is identified by a vertex from each of the argument graphsargument graphs
Suppose functions f and g are represented by root vertices rSuppose functions f and g are represented by root vertices rf f andand rrgg
If rIf rf f and and rrgg are both terminalare both terminal vertices, terminate and return an vertices, terminate and return an appropriately labeled terminal vertex e.g. (Aappropriately labeled terminal vertex e.g. (A44, B, B33) and (A) and (A55, B, B44))
27© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
The Apply algorithmThe Apply algorithm
Let x be the splitting variable Let x be the splitting variable
( x= ( x= min(var(rmin(var(rff) ,) , var(rvar(rgg))))
BDDs for (f|BDDs for (f|x=0x=0 <op> g|<op> g|x=0x=0 ) and (f|) and (f|x=1x=1 <op> g|<op> g|x=1x=1 ) are computed by ) are computed by recursively evaluating the restrictions of f and g for value 0 arecursively evaluating the restrictions of f and g for value 0 and nd for value 1 for value 1
28© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Recursive Calls
ExampleExample
Initial evaluation with vertices AInitial evaluation with vertices A11, B, B11 causes recursive causes recursive evaluations with vertices Aevaluations with vertices A22, B, B22 and Aand A66, B, B55
b
0
d
1
c
a
A4 A5
A3
A2
A6
A1
0 1
d
c
a
B3 B4
B2
B5
B1
A4,B3 A5,B4
A3,B2
A6,B2
A2,B2
A3,B4A5,B2
A6,B5
A1,B1
29© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Apply operationApply operation
Reaching a terminal with a dominant value (e.g 1 for OR, 0 for Reaching a terminal with a dominant value (e.g 1 for OR, 0 for AND) terminates recursion and returns an appropriately labeled AND) terminates recursion and returns an appropriately labeled terminal (Aterminal (A55, B, B22 and Aand A33, B, B44))
Avoid multiple recursive calls on the same pair of arguments by Avoid multiple recursive calls on the same pair of arguments by a hash table (Aa hash table (A33, B, B22 and Aand A55, B, B22))
30© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Apply operationApply operation
Each evaluation step returns a vertex in the generated graphEach evaluation step returns a vertex in the generated graph
Apply reduction before merging the resultApply reduction before merging the result
Complexity of operation : O(mComplexity of operation : O(mff * m* mgg) where m) where mf f andand mmgg represent represent the number of vertices in the BDDs for f and g respectivelythe number of vertices in the BDDs for f and g respectively
31© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Recursive Calls Without Reduction With Reduction
ExampleExample
A4,B3 A5,B4
A3,B2
A6,B2
A2,B2
A3,B4A5,B2
A6,B5
A1,B1
0 1
d
c
b
11
c
a
C2
C4
C5
C3
C6
C1 0
d
c
b
1
a
32© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
ConceptConcept
■■ Effect of setting function argument Effect of setting function argument xxii to constant to constant kk (0 or 1).(0 or 1).
■■ Also called Cofactor operationAlso called Cofactor operation
k F xi –1
xi +1
xn
x1
F [xi =k]Fx equivalent to F [x = 1]Fx equivalent to F [x = 0]
Restrict OperationRestrict Operation
33© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
ImplementationImplementation
DepthDepth--first traversalfirst traversal
Redirect any arc into vertex v having Redirect any arc into vertex v having var(vvar(v) = x to ) = x to point to hi(v) for x =1 and lo(v) for x = 0point to hi(v) for x =1 and lo(v) for x = 0
Complexity linear in argument graph sizeComplexity linear in argument graph size
Restriction AlgorithmRestriction Algorithm
34© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Argument F
Restriction Execution ExampleRestriction Execution Example
0
a
b
c
d
1 0
a
c
d
1
Restriction F[b=1]
0
c
d
1
Reduced Result
35© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
■■ Express as combination of Express as combination of ApplyApply and and RestrictRestrict
■■ Preserve closure propertyPreserve closure property●●Result is an OBDD with the right variable Result is an OBDD with the right variable
orderingordering
■■ Polynomial complexityPolynomial complexity●●Although can sometimes improve with special Although can sometimes improve with special
implementationsimplementations
Derived OperationsDerived Operations
36© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
xi –1
xi +1
xn
x1
F ∃ ∃ xi F
1 F
0 F
xi –1
xi +1
xn
x1
xi –1
xi +1
xn
x1
Variable QuantificationVariable Quantification
■■ Eliminate dependency on some argument through Eliminate dependency on some argument through quantificationquantification
■■ Combine with AND for universal quantification.Combine with AND for universal quantification.
37© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Digital Applications of BDDsDigital Applications of BDDs
VerificationVerification■■ Combinational equivalence (UCB, Fujitsu, Synopsys, Combinational equivalence (UCB, Fujitsu, Synopsys, ……))
■■ FSM equivalence (Bull, UCB, FSM equivalence (Bull, UCB, MCC,ColoradoMCC,Colorado, Torino, , Torino, ……))
■■ Symbolic Simulation (CMU, Utah)Symbolic Simulation (CMU, Utah)
■■ Symbolic Model Checking (CMU, Bull, Motorola, Symbolic Model Checking (CMU, Bull, Motorola, ……))
SynthesisSynthesis■■ DonDon’’t care set representation (UCB, Fujitsu, t care set representation (UCB, Fujitsu, ……))
■■ State minimization (UCB)State minimization (UCB)
■■ SumSum--ofof--Products minimization (UCB, Synopsys, NTT)Products minimization (UCB, Synopsys, NTT)
TestTest
■■ False path identification (TI)False path identification (TI)
38© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Some Popular BDD packagesSome Popular BDD packages
CUDDCUDD (Colorado University Decision Diagram)(Colorado University Decision Diagram)
TUD BDD package (TUDD)TUD BDD package (TUDD)
BUDDYBUDDY
CMU BDDCMU BDD
InformationsInformations about the above BDD packages and someabout the above BDD packages and somemore details can be found at more details can be found at http://www.bddhttp://www.bdd--portal.org/portal.org/
39© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Finite State System AnalysisFinite State System Analysis
Systems Represented as Finite State MachinesSystems Represented as Finite State Machines
■■ Analysis TasksAnalysis Tasks
■■ State State reachabilityreachability
■■ State machine comparisonState machine comparison
■■ Temporal logic model checkingTemporal logic model checking
Traditional Methods Impractical for Large MachinesTraditional Methods Impractical for Large Machines
■■ Polynomial in number of statesPolynomial in number of states
■■ Number of states exponential in number of state variables.Number of states exponential in number of state variables.
■■ Example: single 32Example: single 32--bit register has 4,294,967,296 states!bit register has 4,294,967,296 states!
40© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Symbolic FSM RepresentationSymbolic FSM Representation
■■ Represent set of transitions as function Represent set of transitions as function δδ((OldOld, , NewNew))
●● Yields 1 if can have transition from state Yields 1 if can have transition from state OldOld to state to state NewNew
■■ Represent as Boolean functionRepresent as Boolean function●● Use variables for encoding statesUse variables for encoding states
41© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Nondeterministic FSM Symbolic Representation
o1,o2 encodedold state
n1, n2 encodednew state
00
10
01
11 o2
o1
1
n2
0
n1
o2
Symbolic FSM RepresentationSymbolic FSM Representation
42© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Rstate 0/1δold state
new state0/1
Given Compute
InitialR0
=
Q0
Reachability AnalysisReachability Analysis
•• Compute set of states reachable from initial state (QCompute set of states reachable from initial state (Q00 = 00) = 00)
•• Represent as Boolean function Represent as Boolean function R(R(SS))
43© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
R0
00
BreadthBreadth--First Reachability AnalysisFirst Reachability Analysis
■■ RRii –– set of states that can be reached inset of states that can be reached in ii transitionstransitions■■ Reach fixed point when Reach fixed point when RRnn = R= Rnn+1+1
●● Guaranteed since finite stateGuaranteed since finite state
00
10
01
11
R1R0
00 01
R2R1R0
00 01 10
R3R2R1R0
00 01 10
44© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
■■ RRii +1+1 –– set of states that can be reached within set of states that can be reached within ii +1 transitions+1 transitions●● Either in Either in RRii
●● or single transition away from some element of or single transition away from some element of RRii
Ri
δ
Ri
∃
Ri +1
old
new
Iterative ComputationIterative Computation
45© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Example: Computing Example: Computing RR11 from from RR00
o2
o1
1
n2
0
n1
o2
R0
00
R1
00 01
∃ Old [R0(Old) ∧ δ(Old, New)]
1
n2
0
n1
0
1
n2
0
n1
0 1 0
n1
46© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Powerful OperationsPowerful Operations■■ Creating, manipulating, testingCreating, manipulating, testing■■ Each step polynomial complexityEach step polynomial complexity
●● Graceful degradationGraceful degradation■■ Maintain Maintain ““closureclosure”” propertyproperty
●● Each operation produces form suitable for further Each operation produces form suitable for further operationsoperations
Generally Stay Small EnoughGenerally Stay Small Enough■■ Especially for digital circuit applicationsEspecially for digital circuit applications■■ Given good choice of variable orderingGiven good choice of variable ordering
Weak CompetitionWeak Competition
What’s good about What’s good about OBDDsOBDDs ??
47© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
DoesnDoesn’’t Solve All Problemst Solve All Problems■■ CanCan’’t do much with multiplierst do much with multipliers■■ Some problems just too bigSome problems just too big■■ Weak for search problemsWeak for search problems
Must be CarefulMust be Careful■■ Choose good variable orderingChoose good variable ordering■■ Some operations too hardSome operations too hard
What’s not good about What’s not good about OBDDsOBDDs??
48© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Zero Suppressed Zero Suppressed BDD’sBDD’s -- ZBDD’sZBDD’s
ZBDDZBDD’’ss were invented by were invented by Minato Minato to efficiently represent to efficiently represent sparsesparsesets. They have turned out to be extremely sets. They have turned out to be extremely usefuluseful in implicit in implicit methods for representing primes methods for representing primes (which usually are a sparse (which usually are a sparse subset of all cubes).subset of all cubes).
Different reduction rules.Different reduction rules.
49© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Zero Suppressed Zero Suppressed BDD’sBDD’s -- ZBDD’sZBDD’s
ZBDD Reduction Rule::ZBDD Reduction Rule:: eliminate all nodes where the eliminate all nodes where the thenthennode points to 0. Connect incoming edges to node points to 0. Connect incoming edges to elseelse nodenode
For ZBDD,For ZBDD, equivalent nodes can be shared as in case of equivalent nodes can be shared as in case of BDDsBDDs..
00 11
ZBDD:ZBDD:00
11
00 11
00
50© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
x0 + 2x1 + 4x2
Evaluating a MTBDD for a given variable assignment is similar Evaluating a MTBDD for a given variable assignment is similar to that in case of BDDto that in case of BDD
Very inefficient for representing functions yielding values overVery inefficient for representing functions yielding values overa large rangea large range
0 1
x0
2 3
x0
x1
4 5
x0
6 7
x0
x1
x2
MTBDDMTBDD-- MultiterminalMultiterminal BDDBDD
51© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
EVBDD EVBDD –– Edge value BDDEdge value BDD
EVBDDsEVBDDs can be used when the number of can be used when the number of
possible function values are too high for possible function values are too high for
MTBDDsMTBDDs..
Evaluating a EVBDD involves tracing a path Evaluating a EVBDD involves tracing a path
determined by the variable assignment, determined by the variable assignment,
summing the weights and the terminal node summing the weights and the terminal node
valuevalue
g
x2
4
2
x1
x0
0 1
52© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
*BMD( Binary Moment Diagrams )*BMD( Binary Moment Diagrams )
Features Features ■■ Used for Word level simulation/verificationUsed for Word level simulation/verification■■ CanonicalCanonical■■ Based on linear decomposition of a functionBased on linear decomposition of a function
Functional Decomposition :Functional Decomposition :f = (1f = (1--x) fx) f~x ~x + (x) f+ (x) fxx
= f= f~x ~x + x ( f+ x ( fxx -- ff~x~x) )
= f= f~x ~x + x ( f.+ x ( f.x x ) )
where where f.f.xx is the linear moment w.r.t. xis the linear moment w.r.t. x
53© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
X2
8 -20 42
X2
X1
Representing *BMDsRepresenting *BMDs
Graph :Graph :■■ ExampleExample
x1 x2 f
0 0 8
0 1 -12
1 0 10
1 1 -6
f = (1-x1)(1-x2)(8)+(1-x1)(x2)(-12)
+(x1)(1-x2)(10) + (x1)(x2)(-6)
= 8 - 20(x2) + 2(x1) + 4(x1*x2)
54© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
Weights combine multiplicatively along path from root to leaf Rules :weights of 2 branches relatively prime weight 0 allowed only for terminal vertices if one edge has weight 0, the other has weight 1
x
y y
8 -202 4
x
yy
1-5 2
2
2
BMD
* BMD
Edge Weights ( *BMDs )Edge Weights ( *BMDs )
55© Pallab © Pallab DasguptaDasgupta, Dept. of Computer Sc & , Dept. of Computer Sc & EnggEngg, IIT Kharagpur, IIT Kharagpur
ReferencesReferences
Graph Based Algorithms for Boolean Graph Based Algorithms for Boolean FucntionFucntion Manipulation, Manipulation, Randal E. Randal E.
Bryant, IEEE Transactions on Computers, Bryant, IEEE Transactions on Computers, VolVol CC--35, August 1986, pp. 67735, August 1986, pp. 677--691.691.
Symbolic Boolean Manipulation with Ordered Binary Decision Symbolic Boolean Manipulation with Ordered Binary Decision
Diagrams,Diagrams,
Randal E. Bryant, ACM Computing Surveys, 24(3), 1992, pp. 2Randal E. Bryant, ACM Computing Surveys, 24(3), 1992, pp. 29393--318318