bjt differantial pair

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University of North Carolina at Charlotte Department of Electrical and Computer Engineering

Laboratory Experimentation Report Name: Ethan Miller Date: June 3, 2015 Course Number: ECGR 3156 Section: L01 Experiment Titles: [1] BJT Differential Pair Lab Partner: Joseph Bumgardner, Experiment Numbers: 1 Angelo DeMatteo, Luke Stuemke Objectives:

This lab in tells the experimenter to be familiarize with a BJT differential pair biasing and to be able to conduct the operation of this amplifier to determine the singled and doubled differential gain, and common-mode differential gain.

Equipment List: Items Asset # MB-106 Breadboard 00000001 AFG310 Arbitrary Function Generator 00000002 Agilent InfiniiVision 2000-X Series Oscilloscope 00000003 E3612A Power Supply 00000004 Agilent 34461A 6 ½ Digital Multimeter 00000005 RC 10K 00000006 Re 250 00000007 RA & RB 2.2K 00000008 Rref 5.1K 00000009 C 100µF 00000010 Q2N3904 00000011 P-Spice/Orcad 00000012 Relevant Theory/Background Information:

A BJT differential pair amplifier with a current mirror consists of 4 transistors, shown in Figure 1, and is the most widely used for the input stage of an analog integrated-circuit (input stage of every op-amp). In addition, to this the differential amplifier, it also has the basis of a high-speed logic circuit which is much less sensitive to noise, and is easy to bias the amplifier without the need for bypass amplifier stage including coupling capacitors.

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Figure 1: Differential Pair Amplifier

For the basic operation to perform the differential pair and current mirror circuits have a pair of matching transistors. A pair of matching transistors are two transistors that have the same saturation current and base emitter voltage. To see how a BJT differential pair works, consider a case in which the two base terminals are connected together to form a common-mode voltage VCM. Since Q1 and Q2 are matched and by assuming the ideal bias current source I (infinite output resistance), the current will remain constant and formed a symmetry so that the current I is divided equally between the devices, IE1 = IE2 = I/2. The voltage at each collector will be as follows 𝑉𝑉𝐶𝐶𝐶𝐶 −

12𝛼𝛼𝛼𝛼𝑅𝑅𝐶𝐶 , and the difference between the collectors was 0 volts. Now let’s

say that the value of the common-mode input voltage varies, the current across the RC will still be divided in half and the voltage at the collectors will not change. Thus the differential pair does not react to changes in the common-mode.

Now let’s say that voltage at base two, VB2 has been set to a constant value of 0V and base voltage at one VB1 was 1V. In this case Q1 will turn on and is conducting all of the current I and Q2 is off. This happened because emitter voltage was .3V and the VB2 was 0V, which turned off Q2. For Q1 to be on the emitter base junction it had to be .7V (diode drop), which gave the emitter a .3V, and kept the Q2 in reverse bias. A similar process was done on the opposite side of the amplifier to VB2.

From, this case the differential pair responds to large differences in the signal/input voltage and in fact the amplifier also responds to relative small differences voltages to steer the entire bias current to one side or the other. In order to use the amplifier in the linear state there must be a few millivolts applied at the inputs. This insures that the current of one of the transistors will have a value of 𝐼𝐼

2− ∆𝛼𝛼.

ΔI is the proportional difference of the input voltage. The output voltage will then be ` taken between the two collectors which resulted in the following 2𝛼𝛼∆𝛼𝛼𝑅𝑅𝐶𝐶.

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Some important characteristic of the differential amplifier are calculating the differential gain AVD, single ended differential gain AVDSE, common-mode differential gain AVDCM and the common-mode rejection ratio CMMR. The differential gain was found by tacking the output voltage divided by the input voltage. The differential gain shows the difference between the output and the input when either inputs happened to change in an order of a few millivolts, shown in Equation 5. Along with this a single ended differential gain was also found and shown in Equation 6. In normal operation of a design the single ended differential gain is used to connect multiple circuits. In most case the gain is a form of the ratio the collector resistor divided by small-signal input resistance between the base and the emitter.

Often the CMMR is calculated in order to measure how much the rejection from the device of the unwanted input signal is relative to both of the input voltage. A differential amplifier is considered to be excellent if CMMR is infinite. In order to find this the differential common-mode gain must be found, shown in Equation 7. Then the CMMR is found in Equation 8.

As far as for the current source/current mirror, the basic operation is as follows the output current is approximate to reference current. Again, in order to achieve this both transistors are matched. The reference current flows from collector to the base of transistor, and since the collector and the base terminals are tied to each other the emitter current is the same as the reference current. Given that the transistors are matched, the base current is evenly split between the transistors and reference current is the same as the output current. After through some calculations the output current was found by the following 𝛼𝛼𝑟𝑟𝑟𝑟𝑟𝑟 = 1 + 2

𝛽𝛽 × 𝛼𝛼𝑜𝑜𝑜𝑜𝑜𝑜.

Experimental Data/Analysis: A BJT differential pair circuit was constructed to determine the differential gain, both single-ended and double ended, common-mode differential gain and common mode rejection ratio. Each circuit was biased to have the following parameters:

𝛽𝛽 = 100 𝑉𝑉𝐴𝐴 = 100𝑉𝑉 𝛼𝛼𝐶𝐶𝐶𝐶1,2 = 12𝛼𝛼𝐶𝐶𝐶𝐶𝐴𝐴,𝐵𝐵 𝑉𝑉𝑇𝑇 = 25𝑚𝑚𝑉𝑉 𝑉𝑉𝐵𝐵𝐵𝐵𝑜𝑜𝐵𝐵 = .7𝑉𝑉 𝑉𝑉𝐶𝐶𝐵𝐵1,2 = 6𝑉𝑉

𝑉𝑉𝑪𝑪𝑪𝑪 = −𝑉𝑉𝐵𝐵𝐵𝐵 = 15𝑉𝑉 𝛼𝛼𝐶𝐶𝐶𝐶𝐴𝐴,𝐵𝐵 ≅ 2𝑚𝑚𝑚𝑚 𝑅𝑅𝐴𝐴 = 𝑅𝑅𝐵𝐵 = 2.2𝐾𝐾𝐾𝐾 𝑅𝑅𝑟𝑟 = 250𝐾𝐾 𝑄𝑄1 ≜ 𝑄𝑄2 𝑄𝑄𝐴𝐴 ≜ 𝑄𝑄𝐵𝐵 𝛼𝛼𝐶𝐶1 = 𝛼𝛼𝐶𝐶2 𝛼𝛼𝐶𝐶𝐴𝐴 = 𝛼𝛼𝐶𝐶𝐵𝐵

Shown in Equations 1, 2 and 3 were solved to find certain resistor values for RC1,2 and Rref. In addition, to this the differential gain, both single-ended and double ended, common-mode differential gain and common mode rejection ratio were found to ensure the laboratory results were relatively close to the theoretical results, shown in Equations 4 through 8. Each circuit from the laboratory and P-spice were then plotted to show the difference in the results. The following diagram is the representation for the pre-lab biasing.

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Figure 2: Pre-lab BJT differential Pair Biasing Values

The following are circuit diagrams for the BJT Differential Pair. Along with the circuit diagrams for the P-Spice graphs of the following differential gains. Due to P-Spice simulations and the parameters used for the BJT certain values did not achieve the same value as the calculated value. For instance, the common-mode differential gain and the single ended differential gain were off. Reasons for this may evolve calculation or the wrong process of simulating the circuit in P-Spice.

Figure 3: Single-Ended Differential Gain Circuit

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Figure 4: Double Ended Differential Gain

Figure 5: Single Ended Differential Gain

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Figure 6: Common-Mode Differential Gain


During the lab session the circuit in Figure 1 was conducted to measure the DC bias voltages. In doing so the resistor values were changed and are listed in the equipment section. This was due to the fact of making sure that the current and voltages were bias right in compensating the difference of the matching transistors.

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Table 1 shows the measured bias values. Also, known that in the lab there was a replacement of the 500Ω potentiometer to 2KΩ potentiometer due to the fact of the 500Ω potentiometer did not change the collector-emitter voltages to the differential pair. A potentiometer was connected into the circuit to establish a 6 volts across the collector to emitter voltages, and to ensure the BJT was matched. As a result this made the over-all common-mode, singled and double ended differential gain change by a factor of one-third.

ICQ1 ICQ1 VCE1 VCE2 .96 mA .97 mA 6.00 V 5.88 V

ICQA ICQB VC1 VC2 1.95 mA 1.95 mA 5.33 V 5.21 V

RPOT1 RPOT2

1.004 KΩ .997 KΩ

Table 1: Measured Biased Values for the BJT Differential Pair

From constructing the circuit in Figure 3, the output voltage and the input voltage was measured to construct a tabular signal ended differential gain shown in Table 2. As shown in the table the input voltage did vary, this was not supposed to happen. Since the input resistance to the differential amplifier was connected to the voltage divider, the input voltage varied because the input resistance varies with frequency. When the change of frequency occurred, the input resistance was decreasing, which cause the input voltage to drop. In addition to this the input voltage and both of the output voltage was measured to ensure that the voltages were the same shown in Table 4. By applying the oscilloscope probe to the both of the output’s, the output voltage on Q2 was in phase with the input and output voltage on Q1 was out of phase by 90° with the input shown in Figure 8

Figure 8: Phase Difference between the Input (Green) and Output (Yellow)

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Table 2: Single-Ended Differential Gain Output Voltage at Q1

Another circuit was constructed in a similar fashion as in Figure 3, but the voltage divider was connected to the base of Q2. Again the output voltage and the input voltage was measured to construct a tabular signal ended differential gain shown in Table 3. In addition to this the input voltage and both of the output voltage was measured to ensure that the voltages were the same shown in Table 4. Also the phase difference was to be measured by applying the oscilloscope probe to the both of the output’s, the output voltage on Q1 was in phase with the input and output voltage on Q2 was out of phase by 90° with the input shown in Figure 8. When the voltage divider switched to the base of Q2, the output was the same as Q1. Also shown in Figures 8 and 10 are the oscilloscopes for the input and output voltages for Q1and Q2 signal-ended differential gain. [1]

Frequency (Hz) Vin pk-pk (mV) Vout+ pk-pk (mV) Gain (V/V) 2 15.39 76 4.938271605 10 54.62 266.6 4.880995972 20 70.1 333.4 4.756062767 100 78.8 373.4 4.73857868 1000 79.2 374.4 4.727272727 5000 75.2 356.3 4.738031915 20000 48.09 228.4 4.749428156 100000 12.85 47.7 3.712062257 500000 2.98 4.79 1.60738255 1000000 1.72 2.62 1.523255814

Table 3: Single-Ended Differential Gain Output Voltage at Q2

Frequency (Hz) Vin pk-pk (mV) Vout- pk-pk (mV) Gain (V/V) 2 22.5 82 3.64444 10 60 269 4.48333 20 76 338 4.44737 100 84 374 4.45238 1000 85 382 4.49412 5000 80 358 4.475 20000 51.1 233 4.55969 100000 17.1 51 2.98246 500000 2.9 3.63 1.25172 1000000 0 0 0

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Item Q1 Q2 Vout- 382 mV 373 mV Vout+ 382 mV 382 mV VIN 87 mV 84 mV

Phase Vout- 90° out of Phase with Vin In Phase With Vin Phase Vout+ In Phase With Vin 90° out of Phase With Vin

Table 4: Input to Output Relations

Figure 9: Single-Ended Differential Gain for Q1 Input (Green) and Output (Yellow)

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Figure 10: Single-Ended Differential Gain for Q2 Input (Green) and Output (Yellow)

In furthermore the differential circuit was constructed as in Figure 3, but with the voltage divider at Q2. Again the output voltage and the input voltage were measured to construct a tabular differential gain shown in Table 5. As shown in Figure 11, both of the outputs are shown on the oscilloscope. The measurement found that both of the inputs were the same, Thus the differential gain was double of the single-ended differential gain of both Q1 and Q2. To determine how good the differential pair was a common-mode gain was measured by connecting both of the inputs of Q1 and Q2 to a sinusoidal voltage of 4.0 V peak to peak at 1K Hz. The common-mode gain results are shown in Table 6. Two measurements were made on both of the outputs to ensure accuracy of the common- mode gain. The common-mode gain was found to be 20 mV peak to peak volts. This low common-mode gain gave the common-mode rejection ratio to about 54.84 DB. Since this had a low CMMR the amplifier would not be a stable differential pair to use in an IC or a design. Other considerations were that the calculation values did not come close to the lab results. This was most certainly caused by the emitter resistance was change to 1K and the input voltage varied with frequency.

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Figure 11: Differential Gain Voltage Output's Q2(green) Q1 (Yellow)

Frequency (Hz) Vin pk-pk (mV)

Vout+pk-pk (mV)

Vout- pk pk (mV)

Gain (V/V)

2 103 94 92 1.8058252 10 103 330 326 6.368932 20 103 422 418 8.1553398

1000 103 490 480 9.4174757 5000 103 478 478 9.2815534 10000 103 478 474 9.2427184 20000 103 470 466 9.0873786 100000 103 366 362 7.0679612 125000 103 330 326 6.368932 150000 103 297 293 5.7281553 200000 103 245 241 4.7184466 500000 103 113 111 2.1747573 1000000 103 58 56 1.1067961

Table 5: Differential Gain

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Frequenc

y (Hz) Vin pk-pk (V)

Vout- pk-pk (mV)

Gain (V/V)

Frequency (Hz)

Vin pk-pk (V)

Vout- pk-pk (mV)

Gain (V/V)

500 4.2 0.076 0.0180952

500 4.2 0.069 0.0164286

1000 4.2 0.072 0.0171429

1000 4.2 0.074 0.017619

2000 4.2 0.076 0.0180952

2000 4.2 0.074 0.017619

5000 4.2 0.098 0.0233333

5000 4.2 0.082 0.0195238

10000 4.2 1.204 0.2866667

10000 4.2 0.01093 0.0026024

Table 6: Common-Mode Differential Gain

Laboratory Computation BJT Differential Pair Basing:

𝑚𝑚𝐴𝐴𝐴𝐴𝐴𝐴𝑚𝑚𝐴𝐴:𝛽𝛽 = 100 𝑉𝑉𝐴𝐴 = 100𝑉𝑉 𝛼𝛼𝐶𝐶𝐶𝐶1,2 = 12𝛼𝛼𝐶𝐶𝐶𝐶𝐴𝐴,𝐵𝐵 𝑉𝑉𝑇𝑇 = 25𝑚𝑚𝑉𝑉 𝑉𝑉𝐵𝐵𝐵𝐵𝑜𝑜𝐵𝐵 = .7𝑉𝑉 𝑉𝑉𝐶𝐶𝐵𝐵1,2 = 6𝑉𝑉

𝑉𝑉𝑪𝑪𝑪𝑪 = −𝑉𝑉𝐵𝐵𝐵𝐵 = 15𝑉𝑉 𝛼𝛼𝐶𝐶𝐶𝐶𝐴𝐴,𝐵𝐵 ≅ 2𝑚𝑚𝑚𝑚 𝑅𝑅𝐴𝐴 = 𝑅𝑅𝐵𝐵 = 2.2𝐾𝐾𝐾𝐾 𝑅𝑅𝑟𝑟 = 250𝐾𝐾 𝑄𝑄1 ≜ 𝑄𝑄2 𝑄𝑄𝐴𝐴 ≜ 𝑄𝑄𝐵𝐵 𝛼𝛼𝐶𝐶1 = 𝛼𝛼𝐶𝐶2 𝛼𝛼𝐶𝐶𝐴𝐴 = 𝛼𝛼𝐶𝐶𝐵𝐵 𝑅𝑅𝑟𝑟𝑟𝑟𝑟𝑟 = 0𝑉𝑉−𝑉𝑉𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵−𝑅𝑅𝐴𝐴𝐼𝐼𝐵𝐵𝐴𝐴−𝑉𝑉𝐵𝐵𝐵𝐵

𝐼𝐼𝑟𝑟𝑟𝑟𝑟𝑟= 0𝑉𝑉−.7𝑉𝑉−(2.2𝐾𝐾𝐾𝐾×2𝑚𝑚𝐴𝐴)+15𝑉𝑉

2𝑚𝑚𝐴𝐴= 4.95𝐾𝐾𝐾𝐾 (𝐸𝐸𝐸𝐸𝐸𝐸. 1)

𝑅𝑅𝑟𝑟𝑟𝑟𝑟𝑟 ≅ 4.88𝐾𝐾𝐾𝐾 𝑓𝑓𝑓𝑓𝑓𝑓𝑚𝑚 𝑃𝑃𝐴𝐴𝑃𝑃𝑃𝑃𝑃𝑃𝐴𝐴/𝑂𝑂𝑓𝑓𝑂𝑂𝑂𝑂𝑂𝑂 ∴ 𝛼𝛼𝑟𝑟𝑟𝑟𝑟𝑟 = 1 + 2

𝛽𝛽 × 𝛼𝛼𝐶𝐶𝐵𝐵 ≅ 2𝑚𝑚𝑚𝑚

𝑉𝑉𝐶𝐶𝐵𝐵1,2 = 𝑉𝑉𝐶𝐶1,2 − 𝑉𝑉𝐵𝐵1,2 = 6𝑉𝑉 (𝐸𝐸𝐸𝐸𝐸𝐸. 2) 𝑉𝑉𝐶𝐶1,2 = 6𝑉𝑉 + 𝑉𝑉𝐵𝐵1,2 = 6𝑉𝑉 + 𝑉𝑉𝐵𝐵𝐵𝐵𝑜𝑜𝐵𝐵 = 6𝑉𝑉 − .7𝑉𝑉 = 5.3𝑉𝑉 𝑅𝑅𝐶𝐶1,2 = 𝑉𝑉𝐶𝐶𝐶𝐶−𝑉𝑉𝐶𝐶1,2

𝛼𝛼𝐼𝐼𝐶𝐶𝐶𝐶1,2= 15𝑉𝑉−5.3𝑉𝑉

1𝑚𝑚𝐴𝐴×(1) = 9.7𝐾𝐾𝐾𝐾 𝑤𝑤ℎ𝐴𝐴𝑓𝑓𝐴𝐴,𝛼𝛼 = 𝛽𝛽𝛽𝛽+1

≅ 1 (𝐸𝐸𝐸𝐸𝐸𝐸. 3)

REE Output Resistance of the Current Mirror: 𝑅𝑅𝐵𝐵𝐵𝐵 = 𝑉𝑉𝑇𝑇𝑟𝑟𝑇𝑇𝑇𝑇

𝐼𝐼𝑇𝑇𝑟𝑟𝑇𝑇𝑇𝑇 𝑓𝑓𝜋𝜋𝐴𝐴 = 𝑓𝑓𝜋𝜋𝐵𝐵 = 𝑉𝑉𝑇𝑇

𝐼𝐼𝐶𝐶𝛽𝛽 = 1.25𝐾𝐾𝐾𝐾 𝑓𝑓𝑟𝑟 = 𝑟𝑟𝜋𝜋

𝛽𝛽+1= 12.37𝐾𝐾 𝑓𝑓0𝐴𝐴 = 𝑓𝑓0𝐵𝐵 = 𝑉𝑉𝑎𝑎

𝐼𝐼𝐶𝐶= 50𝐾𝐾𝐾𝐾

𝑔𝑔𝑚𝑚 = 𝐼𝐼𝐶𝐶𝑉𝑉𝑇𝑇

= .080𝑆𝑆 𝑅𝑅𝐵𝐵𝐵𝐵𝐴𝐴 = (𝑓𝑓𝑟𝑟‖𝑓𝑓0𝐵𝐵 + 𝑅𝑅𝐴𝐴)𝑅𝑅𝑟𝑟𝑟𝑟𝑟𝑟+ 𝑓𝑓𝜋𝜋𝐵𝐵 = 2.77𝐾𝐾𝐾𝐾

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0 = 𝑔𝑔𝑚𝑚𝑉𝑉𝜋𝜋 − 𝛼𝛼𝑇𝑇𝑟𝑟𝑇𝑇𝑜𝑜 + 𝑉𝑉𝑇𝑇𝑟𝑟𝑇𝑇𝑇𝑇−(−𝑉𝑉𝜋𝜋)𝑟𝑟0𝐵𝐵

𝑤𝑤ℎ𝐴𝐴𝑓𝑓𝐴𝐴,−𝑉𝑉𝜋𝜋 = 𝛼𝛼𝑇𝑇𝑟𝑟𝑇𝑇𝑜𝑜(𝑅𝑅𝐵𝐵‖𝑅𝑅𝐵𝐵𝐵𝐵𝐴𝐴) 𝑅𝑅𝐵𝐵𝐵𝐵 = 𝑓𝑓0 1 + 𝑔𝑔𝑚𝑚𝑅𝑅𝐵𝐵‖𝑅𝑅𝐵𝐵𝐵𝐵𝐴𝐴 + 𝑅𝑅𝐵𝐵‖𝑅𝑅𝐵𝐵𝐵𝐵𝐴𝐴

𝑟𝑟0 = 4.96𝑀𝑀𝐾𝐾 ≅ 5𝑀𝑀𝐾𝐾 (𝐸𝐸𝐸𝐸𝐸𝐸. 4)

Small-Signal Differential Voltage Gain AVD

𝑓𝑓𝜋𝜋1 = 𝑓𝑓𝜋𝜋2 = 2.5𝐾𝐾𝐾𝐾 𝛼𝛼𝐵𝐵1 = −𝛼𝛼𝐵𝐵2 𝑆𝑆ℎ𝑓𝑓𝑓𝑓𝑜𝑜 (𝑂𝑂𝑃𝑃𝐴𝐴𝐸𝐸) 𝑂𝑂𝐴𝐴𝑓𝑓𝑓𝑓𝐴𝐴𝐸𝐸𝑜𝑜 𝑀𝑀𝑃𝑃𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓

𝑚𝑚𝑉𝑉𝑉𝑉 = 𝑉𝑉𝐵𝐵𝑜𝑜𝑇𝑇𝑉𝑉𝑖𝑖𝐵𝐵

= 𝑉𝑉𝑂𝑂𝑂𝑂𝑇𝑇2−𝑉𝑉𝑂𝑂𝑂𝑂𝑇𝑇1𝑉𝑉1−𝑉𝑉2

= 2𝑅𝑅𝐶𝐶1,2𝐼𝐼𝐵𝐵1𝛽𝛽

−2𝐼𝐼𝐵𝐵1𝑟𝑟𝜋𝜋1,2+𝑅𝑅𝑟𝑟(𝛽𝛽+1)= −34.95 𝑉𝑉

𝑉𝑉 (𝐸𝐸𝐸𝐸𝐸𝐸. 5)

𝑉𝑉𝑂𝑂𝑂𝑂𝑇𝑇2 − 𝑉𝑉𝑂𝑂𝑂𝑂𝑇𝑇1 = −𝑅𝑅𝐶𝐶2𝛼𝛼𝐵𝐵2𝛽𝛽 − (−𝑅𝑅𝐶𝐶1𝛼𝛼𝐵𝐵1𝛽𝛽) = 2𝑅𝑅𝐶𝐶1,2𝛼𝛼𝐵𝐵1𝛽𝛽

𝑉𝑉1 − 𝑉𝑉2 = 𝑓𝑓𝜋𝜋1𝛼𝛼𝐵𝐵1 + 𝑅𝑅𝑟𝑟𝛼𝛼𝐵𝐵1(𝛽𝛽 + 1) + 𝑅𝑅𝑟𝑟𝛼𝛼𝐵𝐵2(𝛽𝛽 + 1) + 𝑓𝑓𝜋𝜋2𝛼𝛼𝐵𝐵2

= −2𝛼𝛼𝐵𝐵1 𝑓𝑓𝜋𝜋1,2 + 𝑅𝑅𝑟𝑟(𝛽𝛽 + 1)

Small-Signal Single Ended Differential Voltage Gain AVDSE

𝑓𝑓𝜋𝜋1 = 𝑓𝑓𝜋𝜋2 = 2.5𝐾𝐾𝐾𝐾 𝛼𝛼𝐵𝐵1 = −𝛼𝛼𝐵𝐵2 𝑆𝑆ℎ𝑓𝑓𝑓𝑓𝑜𝑜 (𝑂𝑂𝑃𝑃𝐴𝐴𝐸𝐸) 𝑂𝑂𝐴𝐴𝑓𝑓𝑓𝑓𝐴𝐴𝐸𝐸𝑜𝑜 𝑀𝑀𝑃𝑃𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓

𝑚𝑚𝑉𝑉𝑉𝑉𝑉𝑉𝐵𝐵 = 𝑉𝑉𝐵𝐵𝑜𝑜𝑇𝑇𝑉𝑉𝑖𝑖𝐵𝐵

= 𝑉𝑉𝑂𝑂𝑂𝑂𝑇𝑇2𝑉𝑉1−𝑉𝑉2

= −𝑅𝑅𝐶𝐶2𝐼𝐼𝐵𝐵2𝛽𝛽

−2𝐼𝐼𝐵𝐵1𝑟𝑟𝜋𝜋1,2+𝑅𝑅𝑟𝑟(𝛽𝛽+1)= −17.47 𝑉𝑉


𝑉𝑉𝑂𝑂𝑂𝑂𝑇𝑇2 = −𝑅𝑅𝐶𝐶2𝛼𝛼𝐵𝐵2𝛽𝛽

Small-Signal Single Ended Common Mode Differential Voltage Gain AVDCM

𝑓𝑓𝜋𝜋1 = 𝑓𝑓𝜋𝜋2 = 2.5𝐾𝐾Ω 𝛼𝛼𝐵𝐵1 = 𝛼𝛼𝐵𝐵2 𝑉𝑉1 = 𝑉𝑉2 𝑅𝑅𝐵𝐵𝐵𝐵 𝑂𝑂𝐴𝐴𝑓𝑓𝑓𝑓𝐴𝐴𝐸𝐸𝑜𝑜 𝑀𝑀𝑃𝑃𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓

𝑚𝑚𝑉𝑉𝑉𝑉𝐶𝐶𝑉𝑉 = 𝑉𝑉𝐵𝐵𝑜𝑜𝑇𝑇𝑉𝑉𝑖𝑖𝐵𝐵

= 𝑉𝑉𝑂𝑂𝑂𝑂𝑇𝑇1𝑉𝑉1

= −𝑅𝑅𝐶𝐶1𝐼𝐼𝐵𝐵1𝛽𝛽𝐼𝐼𝐵𝐵1(𝑟𝑟𝜋𝜋+(𝛽𝛽+1)[250+2𝑅𝑅𝐵𝐵𝐵𝐵]) = −960.36µ 𝑉𝑉


𝑉𝑉𝑂𝑂𝑂𝑂𝑇𝑇1 = −𝑅𝑅𝐶𝐶1𝛼𝛼𝐵𝐵1𝛽𝛽

𝑉𝑉1 = 𝛼𝛼𝐵𝐵1(𝑓𝑓𝜋𝜋 + (𝛽𝛽 + 1)[250 + 2𝑅𝑅𝐵𝐵𝐵𝐵]) Single Ended Common Mode Rejection Ratio CMMR 𝑂𝑂𝑀𝑀𝑀𝑀𝑅𝑅 = 20𝐿𝐿𝑂𝑂𝐿𝐿 |𝐴𝐴𝑉𝑉𝑉𝑉𝑉𝑉𝐵𝐵|

|𝐴𝐴𝑉𝑉𝑉𝑉𝐶𝐶𝑉𝑉| = 85.19 𝐷𝐷𝐷𝐷 (𝐸𝐸𝐸𝐸𝐸𝐸. 8) Voltage Divider Basing: 𝑉𝑉𝑖𝑖𝐵𝐵 = 𝑅𝑅2

𝑅𝑅2+𝑅𝑅1× 𝑉𝑉𝑉𝑉 𝑤𝑤ℎ𝐴𝐴𝑓𝑓𝐴𝐴,𝑅𝑅2 = 1𝐾𝐾𝐾𝐾 𝑉𝑉𝑖𝑖𝐵𝐵 = 100𝑚𝑚𝑉𝑉𝑝𝑝𝑝𝑝−𝑝𝑝𝑝𝑝 𝑉𝑉𝑇𝑇 = 1𝑉𝑉𝑝𝑝𝑝𝑝−𝑝𝑝𝑝𝑝

∴ 𝑅𝑅1 = 𝑅𝑅2×𝑉𝑉𝑇𝑇 𝑝𝑝𝑝𝑝−𝑅𝑅2×𝑉𝑉𝑖𝑖𝐵𝐵 𝑝𝑝𝑝𝑝𝑉𝑉𝑖𝑖𝐵𝐵 𝑝𝑝𝑝𝑝

= 1𝐾𝐾𝐾𝐾×500𝑚𝑚𝑉𝑉𝑇𝑇 𝑝𝑝𝑝𝑝−1𝐾𝐾𝐾𝐾×50𝑚𝑚𝑉𝑉𝑖𝑖𝐵𝐵 𝑝𝑝𝑝𝑝50𝑚𝑚𝑉𝑉𝑖𝑖𝐵𝐵 𝑝𝑝𝑝𝑝

= 9𝐾𝐾𝐾𝐾 (𝐸𝐸𝐸𝐸𝐸𝐸. 9)

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𝐿𝐿𝑂𝑂𝐿𝐿 𝑂𝑂𝑀𝑀𝑀𝑀𝑅𝑅 = 20𝐿𝐿𝑂𝑂𝐿𝐿 |𝐴𝐴𝑉𝑉𝑉𝑉𝑉𝑉𝐵𝐵|

|𝐴𝐴𝑉𝑉𝑉𝑉𝐶𝐶𝑉𝑉| = 54.84 𝐷𝐷𝐷𝐷 (𝐸𝐸𝐸𝐸𝐸𝐸. 10) Conclusions: In this experiment the BJT differential amplifier was constructed and tested for measurements of the following current and voltage biasing, single-ended differential gain on both Q1 and Q2, differential gain and the common-mode differential gain. When testing the circuit the potentiometer was changed from 500 ohms to 1K ohm, this made the overall gain decrease by a one-third. Other considerations involve the common-mode gain which was found to be low, this made the common-mode rejection ratio to be low. As results showed a low CMMR which will not be used for an IC or any practical design amplifier. Post Lab:

Figure 12: Single-Ended Differential Gain of Q1

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Figure 13: Single-Ended Differential Gain of Q2

Shown in Figures 12 and 13 are the lab results for both signal-ended differential gain for Q1 and Q2. Both of the graphs above have roughly the same differential gain. Since both of this had the same differential gain meant that the current through the collector and emitter were the same as well as the collector to emitter voltage. Having the same values ensured that the differential amplifier was conducting in the linear region.

Figure 14: Differential Gain of BJT Amplifier

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Shown in Figures 14 and 15 are the lab results for differential gain and the common-mode gain. The differential gain had a gain that was double the amount of the single-ended differential gain. This only happed because the differential amplifier was biased correct. Also shown is the common-mode differential gain, this shown that the gain was relatively small. Since this amount was small, this meant the differential amplifier did not show signs of any movement or change the two collector currents. The common-mode rejection ratio was calculated and found to be 54.84 DB. This was found to not to be a good CMMR. Reason for this could be the input voltage was changing due to frequency.

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List of Attachments: Original Data Sheet References: [1] Lab Handout “BJT Differential Pair”

This report was submitted in compliance with UNCC POLICY STATEMENT #105 THE CODE OF STUDENT ACADEMIC INTEGRITY, Revised August 24, 2008 (http://www.legal.uncc.edu/policies/ps-105.html) (ECM).

[2] A. . S. Sedra and K. C. Smith, Sedra/Smith Microelectronic Circuits, Oxford New York: Oxford University Press, 2010.

http://www.legal.uncc.edu/policies/ps-105.html

bjt differantial pair

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