BJT Fixed Bias

ELEC 121

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BJT Biasing 1For Fixed Bias Configuration:• Draw Equivalent Input circuit• Draw Equivalent Output circuit• Write necessary KVL and KCL Equations• Determine the Quiescent Operating Point

– Graphical Solution using Loadlines– Computational Analysis

• Design and test design using a computer simulation

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Complete CE Amplifier with Fixed Bias

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Fixed Bias and Equivalent DC Circuit

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Fixed-Bias Circuit

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DC Equivalent Circuit

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Base-Emitter (Input) Loop

Using Kirchoff’s voltage law: – VCC + IBRB + VBE = 0

Solving for IB: CC BE

B B

V - VI =

R

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Collector-Emitter (Output) Loop

Since: IC = IB

Using Kirchoff’s voltage law: – VCC + IC RC + VCE = 0Because: VCE = VC – VE

Since VE = 0V, then: VC = VCE

And VCE = VCC - IC RC Also: VBE = VB - VE

with VE = 0V, then: VB = VBE

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BJT Saturation Regions

When the transistor is operating in the Saturation Region, the transistor is conducting at maximum collector current (based on the resistances in the output circuit, not the spec sheet value) such that:

CC CE Csat

C

CEwhere

V - VI =

RV = 0 .2 V

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Determining Icsat

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Determining ICSAT for the fixed-bias configuration

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Load Line Analysis

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Load Line AnalysisThe end points of the line are : ICsat and VCEcutoffFor load line analysis, use VCE = 0 for ICSAT, and IC = 0 for VCEcutoff

ICsat:

VCEcutoff:

Where IB intersects with the load line we have the Q pointQ-point is the particular operating point: • Value of RB

• Sets the value of IB

• Where IB and Load Line intersect• Sets the values of VCE and IC.

CE

C

CC Csat V 0V

C

CE CC I 0mA

VI =

R

V = V

|

|

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Circuit values effect Q-point

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Circuit values effect Q-point (continued)

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Circuit values effect Q-point (continued)

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Load-line analysis

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Fixed-bias load line

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Example

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DC Fixed Bias Circuit Example

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Loadline Example Family of Curves