blecs-combiner presentation

BLECS-Combiner Presentation

Context

Functionalities BP and alarms table

Memory contents

State

Some questions

Next steps

1

BLECS-Combiner Context

IC BLECF

BLECS

CIBUS Unmascable Beam Permit

BLETCN°1

BLETC N°16

IC BLECF

Cre

ate

1

BLECSBLETC

N°1BLETC N°16

Cre

ate

2

LastBLECS

BLETCN°1

BLETC N°16

Cre

ate

n

CIBUS Mascable Beam Permit

HV1 + HV2

IC BLECF

IC BLECF

IC BLECF

IC BLECF

IC Ionization chamberBLECF BLM data acquisition card Current to FrequencyBLETC BLM data processing and Threshold ComparatorBLECS BLM Combiner and SurveyCIBUS Controls Interlocks Beam User SingleHV High Voltage power supply

1 to 4 crate connected in series with the BLECSSame connection between BLECS and between BLECS and CIBUSLast BLECS control the HV but all can read the HV voltage

2

BLECS-Combiner Functionalities

BEAM PERMIT TRANSMISSIONBeam Permit lines transmission from the Threshold comparators (TC) to the CIBU (Interlock network), tagging. BEAM ENERGY CONVERSION & DISTRIBUTIONReceive the energy from the CTRV, converse it in 5 bits value and distribute it to the whole create.

ANALOG GENERATION AND ACQUISITIONControl and Monitoring of the high voltage (HV) for the ionization chambers

TESTSRelated to the Beam InterlockRelated to the Beam EnergyRelated to the HV

VOLTAGES SURVEYHV and low voltage with level comparators

3

BEAM PERMIT LINE CONTROL

‘A’

User.Permit.A+

User.Permit.A-

D1

D2

R1

R2

IC1

T2T1 R4

Q Inv. Q Beam permit1 0 PERMIT

Normal states0 1 DUMP1 1 DUMP

Fault state0 0 DUMP

One shot output state


Q

Q

OFF ON

Lines from BLECS (Up)

Lines from FPGA (frequency > 1MHz) Transient voltage suppressors @ BLECS output ?4

BLECS-Combiner FunctionalitiesBEAM PERMIT LINE CONTROL

Rating Unit

Uout(ON) 5 V

Uout(OFF) -5 V

±Iomax25 mA

BLECS Beam permit output spec

Uout(ON) = 5V

Uout(OFF) = -5V

±Iomax = 25 mA

5

Beam permit related parts

Beam Permit from TC (M)

Beam Permitdecision unit

Post-mortemand

Login

Beam Energy Failure

Beam Permit from TC (U)

Beam Permit from BLECS (UA)

Beam Permit from BLECS (UB)

Beam Permit from BLECS (MA)

Beam Permit from BLECS (MB)

Beam Permit to CIBU (UA)

Beam Permit to CIBU (UB)

Beam Permit to CIBU (MA)

Beam Permit to CIBU (MB)

Test Failure

FPGA

Clock from BOBRTime Stamps (orbit counter)


Dump table6

Beam permit related parts

Beam Dump (M & UM)

Beam permit

Power Supplies Comparators

LogicP

0 C

on

ne

cto

r

BLECS

BLETC

P2

Co

nn

ect

or

BLECSor CIBUS

CISV

Beam Energy (Serial)


Beam permit

HV1

HV2 Comparators

VME PS 4x

P0 PS 3x

12 lines

FPGA

Tests

Post-mortem

Beam info


Beam permitdecision unit

7

Beam Energy related parts


P0

Co

nn

ect

or

P2

Co

nn

ect

or



FPGA

Energy conversion & add informations

CTRV

BLETC

Serial reception (redundant A and B)

Counters: Frame, CRC error, Lost of FrameToggle bit

Translation 16 bits to 5bits, hard coded conversion table

Substitution of the original value by any value (in test mode only)

Additional information (tests commands for the TC) on the reminded free bits (see tests functionalities section further)

Serial transmission to up to 16 TC receivers in parallel

Scenario CRC error Lost Frame Comment Action

1 No No Normal operation Normal

2 A or B - Threshold Error>? per second warning

3 - A or B Threshold Error>? per second warning

4 No A & B No Beam Energy reception Highest Energy is send & error bit ‘1’

Dump table8

Beam Energy


Dump table9

CT

RV

Beam Energy test setup on BA5


2

P2

CT

G

C

PU

B

LET

C

B

LET

C

B

LET

C

B

LEC

S

1

P2

P0

P0

P0

P0

CT

RP

3 4

562021

10

ANALOG GENERATION

The high voltage power supplies for the ionization chambers are controlled by analog signals 0-10V.There is an analog sum done between the 2 outputs of the DAC, the modulation signal is attenuated with a

potentiometer digitally controlled.

To HV supplyAnalog

SUMPot digitallyControlled

(8 bits steps)

Modulation

Offset

FPGA

FPGA

16 bitsDAC8532

RCFilter

Zenner 6.8V

Close to the connector (P2)

BLECS output HV output

Voltage step 0.153 mV 45.8 mV

Voltage range 6.8 V 2040 V

Modulation range peak-peak 78V to 100mV 23mV to 30V


BLECS-Combiner-Schematics-Rev111

http://ab-div-bdi-bl-blm.web.cern.ch/ab-div-bdi-bl-blm/Electronics/BLECS_Combiner/BLECS-Schematics/Rev1/BLECS-Combiner-Schematics-Rev1.zip

ANALOG ACQUISITION

The high voltage power supplies have analog output monitors to view the voltage and current levels, there is 1 channel for the current and 2 channels of digitalization for the voltage (offset and low frequency modulation)

ADC

LPFilter

Instrumentationamplifier

Digital pot.

Digital pot.GAIN

Offset compensation

From the HV voltage monitoring

LPFilter

BufferFrom the HVcurrent monitor

FPGA

FPGA

Buffer


BLECS input @ the HV [V] @ the HV [I]

Adc resolution (DC) 13 bits 1.22 mV 366 mV 2.44A

Adc resolution (AC) G = 150 8.1 V 2.44 mV

Measured noise (2*StdDev) 1.61 mV 481.6 mV @ 1502V 4.8A @ 11.7

BLECS-Combiner-Schematics-Rev1Dump table12


System test

Consistency test

Manual actions

Internal Timer request

User request

Expert request

TESTSRelated to the Beam InterlockRelated to the Beam Energy Related to the HV

(CPU): cpu based test, the decision passed/failed is given by the CPU to the BLECS which will release the beam permit to true (beam allowed)

BLECS-Combiner Functionalities: Tests

Dump table

HV Modulation

Beam Permit Lines

Consistencytest

(CPU)

BPBIS test:Beam Permit

to Beam interlock

(CPU)

HV Step TestsIndividual tests

The tests are triggered by the CPU (Sequencer?) and are activated by the BLECS only if the Beam info indicate that there is no beam permit. For some tests, the result can only be computed by the CPU.

The result will be written on the combiner in order that it gives the beam permit again.

Energytest

13

CONSISTENCY It controls the threshold table by changing the energy and reading the logging. CPU based testHVLF Low frequency modulation of the HV Modulation of the HV power supplies an analysis of the Running Maxincluding HVAT step of the HVBPTC - Beam Permit Lines from TC Test of the lines between BLETC and last BLECS (before CIBU)

SYSTEM TEST (by Timer, User & Expert)It include all the standard test to be done within 12 to 24hours: Consistency, BPTC, HVLF.CONSISTENCY (by User & Expert)It controls the threshold table by changing the energy and reading the login. CPU based testBPBIS (by BIS User, Expert?)Test of the lines between BLECS and LHC Beam Interlock System. CPU based testEnergy Test (by User ?). The master of CTRV send a sequence of energy. The BLECS check for this sequence.

Beam Energy CRCContinuous check of the correct reception of the Energy valuesHV monitoringContinuous check of the U & I for the 2 power supplies with ADC & comparators.VME Supplies monitoringContinuous check of the 5V, 3.3V and ±12V with comparators.P0 Floating SuppliesContinuous check of the 5V and ±15V with comparators.

CONTINUOUS CHECK

SYSTEM TESTdetails


Dump table14

Continuous checks on the frame (arrives every ms):CRC errors on the data reception.Lost Frame. Time out in case of no reception on time.Lost Energy value. Time out in case of no new energy (every second)Energy test (by User, Expert?)Test of the Energy values changes. The CTRV master initiate a known sequence of different energy values. The BLECS check for it when it was asked for.

Related to Beam Energy


Dump table15

CONSISTENCY (by User & Expert)It verify the threshold table by changing the energy in the BLECS and reading the login on the BLETC. Needs a result of the comparison from outside to be written inside the BLECS BPTC - Beam Permit Lines from TC Test of the lines between BLETC and last BLECS. (see further slides)Use of the Beam Status from the BIS (CIBUS interface) to know when to accept change on threshold table

Beam Energy (0 to 31)[5 bits]

Error bit[1 bit]

SofResetTC [1bit]

System under Test

Unmaskable Beam Info [1

bits]

Maskable Beam Info [1 bits]

BPL Unmaskable test activation [1 bit]

BPL Maskable test activation

[1 bit]

Beam Permit Line test TC Card Number

[4 bits]

Bit position [15..11] [10] [9] [8] [7] [6] [5] [4] [3..0]

Broken link state*

31 (highest) 1 0 0 1 1 0 0 0

CTRV transmission specification1. ”10010000” header (8 bits)2. Energy value (16 bits)3. Toggle bit + ”000” (4 bits)4. CRC (4 bits)

Energy value (16 bits)

CRC check, errors countersTime out check, errors counters Conversion

BLECS transmission specification1. ”10010000” header (8 bits)2. Composite data (16 bits)3. Toggle bit + ”000” (4 bits)4. CRC (4 bits)

To maximum 16 TC in parallel

BLECS-Combiner Functionalities: TestsRelated to Beam Energy

16

* Applied when transmission is broken.

BPLBIS (by BIS User, Expert?)Test of the lines between last BLECS before the CIBU and LHC Beam Interlock System. CPU based testBPTC - Beam Permit Lines from TC Test of the lines between BLETC and last BLECS (before CIBU)

Access by the CPU of the Beam Permit outputs lines: Only when no beam Only one line can be modified, all the others should be “Beam permit away” (false) Because of the Daisy chain structure between the BLECS, all the 3 (for one IP)

have to be tested at the same time.

Related to Beam Interlock


Dump table17

Access by the CPU of the Beam Permit outputs lines: Only when no beam Only one line can be modified, all the others should be “Beam permit away” (false)

Procedure for the BPL to BIS test


Dump table

1) Request the BPL to BIS test: Activate UBPBISTR (User Beam Permit to BIS Test Request) 2) The system waits for the Beam Info to go ‘False’ in order to enter in the test3) Ones inside the test, all the beam permit lines goes ‘false’4) Then it is possible to put only one beam permit line (A or B) to ‘true’ for maskable and unmaskable lines5) The test ends when the result of this test is given to the board by writing in the correct register bit

‘1’ for passed and ‘0’ for failed.

18

BLECS 1

Task :Identify the last crate in the chain (the one which touch the CIBU)


Last crate identification


HV crate

BLECS 2

VCC

100k GND

5k

FPGA

If the FPGA input = ‘1’ there is no BLECS under. Means there is the CIBU and this is the last BLECS before CIBU.

BLECS 2

BLECS 3

BLECS 4

Top to VCCIt see top position

It see bottom position

P2.A30

P2.A29

BLECS 1

VCC

100k GND

5k

FPGA

P2.A30

P2.A29

If the FPGA input = ‘0’ there is another BLECS under. Means this is not the last BLECS before CIBU.

19

BLECS

Task :1) Notify the other BLECS that the

system is under test.2) Last crate received beam permit away

(Beam Dump)


Commune lines between crate

BLECS

Ope

n d

rain

line

s


BLECS

BLECS

20

Commune lines between crate

Open drain lines with dedicated IC: OD1 & OD2


21Line direct FPGA to FPGA (200 Ohm between IO) simulation of OD with pull-up OD3

BLECSBLECS

BLECSBLECS

BLECSBLECS

BLECSBLECS

OD

1

OD

2

OD

3

Signalization needed:1)The system is under test (the last crate keep the beam permit lines low)2)The last crate has received the beam permit low(See BPTC test)3)Request 100pA test level4)Request “Modulation level “ of the HV+ Modulation of the HV

Name OD1 OD2 OD3 Description

Normal operation 1 1 1

Beam permit indication from the la combiner before the CIBUS

x x 0 OD3 can change to indicate BP is false by the last crate before CIBUS (See BPTC test)

System under test(all test except Modulation)

0 1 x The HV level goes at 100pA when any test starts

System under test Request Modulation level and Modulation.

0 0 x

BLECS

Principle BPTC (Beam permit from BLETC to last BLECS)


BLECS

BLECS

Last BLECS

From any BLETC to the last BLECS before the CIBUOne crate after each otherThe tested crate send an info “crate under test”The last BLECS should know it position and send a feedback saying “I received the beam dump”

1. The CPU initiate the test on one of the crate2. The BLECS check the Beam info to see if the test is allowed, otherwise waits3. The BLECS notify the other crate by changing the state of the OD1 line4. The last BLECS put the beam permit away and wait for Beam Dump5. The tested BLECS test the first TC by sending

the command thought the energy serial connection.6. The beam dump should start from the TC and pass thought all BLECS needed

to arrive to the last BLECS.7. The Last BLECS receive the Beam Dump and notify the tested crate by

pulling the OD2 line.8. The tested BLECS receive the Beam Dump notification and start to test the next TC

and so on till the last TC.

OD1 OD2

22

HVLF overview


23

BLETCThreshold

Comparators

HV(Vin*300)

BLECSCombiner and

survey

Control0-6.8V

Real excitation signal

BLM chamber

HV 0-2000VBLECFCurrent toFrequency

Current

OpticalLink

VME

SURFACE

TUNNEL

BLECS-Combiner Functionalities: Flash param

24

Parameter 2: Set voltage modul. (peak-peak)Parameter 2: Set voltage modul. (peak-peak)

Parameter 1: Set HV voltage value Parameter 1: Set HV voltage value

Parameter 3: Set frequency modul.Parameter 3: Set frequency modul.

MT

FM

TF

Result 1: PhaseResult 1: Phase

Result 1: GainResult 1: Gain

LS

AL

SA

Modulation 1: VoltagePeriod




HV normal operationHV normal operation

HV HVCFCHV HVCFC

HV HVRDACHV HVRDAC

HV HVRGOHHV HVRGOH

HV peak HVCFCHV peak HVCFC

HV peak HVRDACHV peak HVRDAC

HV peak HVRGOHHV peak HVRGOH

Present TC board tablePresent TC board table

Present CFC board tablePresent CFC board table

Status table “TestCFC”Status table “TestCFC”

Status table “RSTDAC”Status table “RSTDAC”

Status table “RSTGOH”Status table “RSTGOH”

Present channel tablePresent channel table

HV Diff HV1 & HV2HV Diff HV1 & HV2

LSALSAFlashFlash

RegistersRegisters

CPUCPU

Expert GUI

Expert GUI

TrimTrim

ROMROM

Per

cra

teP

er c

rate

Fro

m C

rate

th

roug

h C

PU

Fro

m C

rate

th

roug

h C

PU

Rsum tableRsum table

SWITCH “Enable write register”

SWITCH “Enable write register”

Modulation 1: Gain min & maxPhase min & max



Modulation 2: Gain min & maxPhase min & maxM

onit

orM

onit

orP

er I

PP

er I

P

HVLF related parts

1 TC

RAM256x32bits

Phase & Gaintracking

Decision Unit

Thresholds

TCMax.16

RAM256x32bits


Decision Unit

Thresholds

RAM256x32bits


Decision Unit

Thresholds

Real ExcitationSignal

NVMemory

First glance:Excitation Signal frequency 30mHz or 100mHzSample per period 256 for the reference and 1s/Exitation signal for the RunMax (Use the Login)Number of period min. 3Number of channel in parallel 16 (1 TC)Total time for one create 3*1/0.3Hz*16TC = 160s


RAM256x16bits

CH1

CH2

CH16

VMERAM

256 Channelsx32bits

update everyLogin

25

HVLF first results


Result modulation 30mHz Result modulation 100mHz

Gain StdDev Phase StdDev

In this test, there were two methods working in parallel: Simple and double cross-correlation Further investigations needed to ameliorate, select one of the two and fine pitch the method.

There are only 4 channels connected with a chamber for this test. There can be easily identified them on the result of the measurements below.

26

http://ab-div-bdi-bl-blm.web.cern.ch/ab-div-bdi-bl-blm/Electronics/BLECS_Combiner/BLECS-measurements/Modulation_PT8_11May/Result_CorrelationImmediat&DoubleCorrelation_30mHz.txt

http://ab-div-bdi-bl-blm.web.cern.ch/ab-div-bdi-bl-blm/Electronics/BLECS_Combiner/BLECS-measurements/Modulation_PT8_11May/Result_CorrelationImmediat&DoubleCorrelation_100mHz.txt

Test command &Test Result for

Beam Permit to BIS

StatusTest Results

Alarms

Crate setup infoRunnMax

Start TestsResults Tests:1) Consistency

2) Threshold to BPL

Energy ValueBeam info stateTest commandsCombiner SN?

BLECS-Combiner Functionalities: Data transfers

BLECS

BLETCN°1 to 16

CPU

VME

P0 Serial

CIBUS

BICEthernet

27


TestDecision unit

TestDecision unit

Systemtest

Systemtest

Test requestsDecision unit

Consistencytest

Consistencytest

28

HVLF modulationtest

HVLF modulationtest

Test resultsTest results

There is a second method of HV survey which use comparators with fixed level connected to the FPGA for analysis.

BLECS-Combiner Functionalities: HV survey

Comparators threshold:V monitor higher: 2100 => limit of IC capacitorV monitor lower: 500I monitor higher: 18mAV monitor lower: 0.5mA

The two HV (voltage and current) are monitored by one ADC at a rate of 6.94 kHz, some logic can be implemented to survey any changes:Threshold comparison with a value determined by the location (for I, depend on the number of ionization chamber connected)

PT8 first test: around 0.6 to 0.7mA

BLECS-Combiner-Schematics-Rev1Questions Dump table 29


Low Voltage power supplies Survey

VME: 5V, 3.3V, ±12VAnalog: 5V, ±15V

BLECS-Combiner Functionalities: LV survey

Use comparators to detect any failure and :1) Count the number of failure / per LOGIN reading (1s)

if ripples => ~100 per second2) Measure length of the failure ? (resolution 25ns)

BLECS-Combiner-Schematics-Rev1Questions Dump table 30


BLECS-Combiner FP

System Operational System in test Test Requested Post Mortem

HighVoltage failed BeamEnergy failed ObitClock failed DUMP

UA in UB in MA in MB in

UDL MDL UBI MBI

UA out UB out MA out MB out

Vref1 Vdc1 Vmon1 Imon1 Vref2 Vdc2 Vmon2 Imon2

Analog outputSelect analog output

CLK inputs

Inputs A & B

Outputs A & B

VME access led

Beam permit input

Beam permit output

Dump lines / Beam info

Questions 31

BLECS-Combiner BP and alarms table

BLECS-MemoryMapping

Source AlarmLow

AlarmMedium

Alarmhigh

Dump PM record

Comment Link

Beam permit IN x x 4 lines: UA, UB, MA, MB from another BLECS Slide 6

P0 Beam Permit x x 2 lines: U, M from the BLETC

HV current comparator

If low or high

Low limit = 0.5mA, High limit = 18mA Slide 10

Slide 18

HV current ADC If low or high

limits are depending on load

HV voltage Comparator

1 or 2 failed If 1&2

down for 1s

If 1&2 down for

x sec.HV voltage ADC If Instable 1 or 2 failed

Time limited instability

Low voltage If ripple If down Characterization of the PS, Ripple level determination.

Slide 19

System test If test failed Slide 12

Consistency test If test failed Slide 11

BPLBIS If test failed Beam permit to the Beam Interlock System Slide 13

32

http://ab-div-bdi-bl-blm.web.cern.ch/ab-div-bdi-bl-blm/Electronics/BLECS_Combiner/BLECS-Documents/BLECS-MemoryMapping/BLECS-MemoryMapping.pdf

BLECS-Combiner Memory contents

PM SRAMPost mortemBD SRAMBeam Dump, content to be definedXtra SRAMExtra, content to be definedFlash ROMFlash memory for saving parametersLOGINLogged status and principal results (Read only) TEST RESULTSResult of the last tests. To be saved after every testsControl / Status RegistersStatus of the Create: (nbr. TC, nbr. Channels, RunMax for modulation, ...)DAB64x Control / Status Registers

BLECS-MemoryMapping33

http://ab-div-bdi-bl-blm.web.cern.ch/ab-div-bdi-bl-blm/Electronics/BLECS_Combiner/BLECS-Documents/BLECS-MemoryMapping/BLECS-MemoryMapping.pdf

BLECS-Combiner Memory contentsLOGINLogged status and principal results (Read only)


BLECS-Combiner Memory contents

PM SRAM

This is the first attempt of the post mortemdefinition. To be reviewed


BLECS-Combiner State

Function description Hardware FPGA code Test

Beam permit from TC Completed partial Not started

Beam permit to CIBU Completed Partial Partial

Beam Energy Completed Partial Partial

Analog generation Completed Completed Partial

Analog acquisition Partial Partial Partial

Test Beam Interlock Partial Partial Not started

Test Beam Energy Completed Completed Not started

Test HV Partial Partial Not started

VME Partial Partial Partial

Estimation of the work completion:

36

BLECS-Combiner Some questions

Hardware: missing function, improvements?

Front panel: Is there all the needed information / devices ?

HV survey: What could be the levels of current to define thresholdWhat are the levels (Vlower and Vhigher)

Low Voltage survey: Method of process the comparators output. Counter? Time measurements?

BLECS-Combiner-Schematics-Rev1

view

view

view

37

BLECS-Combiner next steps

FPGA code correction and functions addition, use of the second iteration (available).

Hardware completion for a third revision.

Test bench development for the test of the production boards.

Validation of the third prototype.

Production of the boards (45)

Completion of the test bench (Hardware, software)

38

Combiner functionalitiesANALOG GENERATION

SCHEMATIC

39

Combiner functionalitiesANALOG ACQUISITION

40

Combiner functionalitiesBEAM PERMIT CONTROLPCB Implementation Beam Dump lines from the TC

Beam permit lines from previous combiner to next combiner or BIS

41

Combiner functionalitiesANALOG DIGITAL CONVERSIONS

PCB Implementation Analog generation for the 2 HV PS

RC filter close to the connector to cut the eventual high frequencies induced by the digital components

Digitalization of the information coming from the 2 HV power supplies

42

Combiner functionalitiesVOLTAGES SURVEY 1) HV SUPPLIES2) VME & P0 floating PS

Survey VME PS

Survey HV PS

Survey P0 floating PS

43

blecs-combiner presentation

Documents

blecs mabeam permit

blecs uabeam permit

blecs ubbeam permit

blecs mbbeam permit

related partsbeam permit

cibu mabeam permit

cibu uabeam permit

cibu ubbeam permit