bolometer read-out in the cuore approach (that is thinking to...

Lumineu, Paris, 13 Jan 2014 g.pessina -1-

Bolometer read-out in the CUORE approach(that is thinking to stability in very long runs)

… and Lorenzo Cassina and Andrea Giachero and Claudio Gotti and Matteo Maino

Gianluigi PessinaINFN and Università di Milano Bicoccahttp://pessina.mib.infn.it

http://pessina.mib.infn.it/


Summary of the speeches

• CUORE in short;

• CUORE specifications and set-up in short;

• Electronics readout approach.


CUORE in short (1)

CUORE is an array of 988 TeO2 crystals readout with NTD thermistors.

Its purpose is the study of the 0-

of Te.


CUORE in short (2)

A dedicated refrigerator was built to house the detector structure.

The refrigerator has 2 main characteristics:

1) The capability to cool down to 5 mK such a stuff, with a very big volume;

2) To be as much as possible radio- pure.


CUORE in short (3): system requirements

The 0-

study needs periods of data taking that must be very long, the longer the better.

The stability of the response of the whole system must be very stable and the calibrating particle source should be used seldom.

Considering the view from the Electronics side this means a requirement of stability at level of a few ppm (part-per-million).

This high level of stability reflects on every part, not only the very front- end.


CUORE in short (4): system specifications

Crystals are very heavy, >500 g and held at 10 mK.

The NTD thermistor is the sensor. Our thermistors have a few tens of M

impedance at that temperature, let’s say 50 M.

Consequence:

1) The detector signal is very slow, few Hz of BW.

2) The parasitic capacitance does not affect the signal up to a few hundreds pF.

We adopted a room temperature readout, with DC detector biasing, taking care of the connecting link.


CUORE in short (5): system specifications

The room temperature readout is attractive for several reasons:

1) saving of space inside the fridge;

2) saving of number of connections inside the fridge;

3) yield and easy maintenance;

4) no heating injection to the detectors;

5) …


Electronics simplified set-up

Troom

Troom

Troom We need only 2 wires to connect the detector and 2 wires to connect the calibrating/stabilizing pulser.

This is a very simplified schematic scheme.

The Detector is current DC biased, since the value of the load resistors is >> the detector impedance.


Electronics set-up, more details

K

K =Kapton

= PEN =Constantan

Links to the detectors: PEN and glue Kapton boards.

Bias and load resistors

Main board

X6

Main boardGlue. Logic

Backplane

Pre SS

DetectorsVery front-end (on the fridge)

Calibration Pulse Gen.

Heater Pulser, ppm stab

Antialiasing

Small Faraday Cages

Close to the DAQ

DAQ

Bessel Filter

x12

Glue Logic

Bessel FilterBessel

Power supply system

Linear Supply, 9 V, 5 V, ppm stab

DC/DC 48 V to 12/6 V

48 V AC/DC

Glue Logic from DAQ to ALL blocks

Temperature stabilization of

det. holder


Front-end configuration (1)

First main benefit from differential readout:+

-

+

-

CUORE has many channels and there is a packaging of the connection wires. Cross-talk would be very important if not addressed.The differential configuration is a good choice for its suppression.

Our wiring system is based on the differential readout, which is important for a number of reasons.The reading preamplifier is differential voltage sensitive.



Cross-talk originates from the parasitic capacitance, CCR , between nearby detectors.

If the 2 connecting wires of each detector are close together the parasitic capacitance between every preamplifier input and a whatever other detector wire is the same.

As a consequence the induced signal is similar for both inputs: this signal is cancelled at the output of the preamplifier since the output is proportional to the difference of the inputs.

CH1

cP +

-cP

CH2

cP +

-cP

CCR

Cross-talk largely suppressed.



cP +

-cP

The differential configuration is not only useful for cross-talk suppression.

Any disturbance that induces a similar signal to both inputs is attenuated; and there are several of such effects: EMI interferences, ground loops, certain form of mechanical vibrations of the wires, …


Front-end configuration (4): Load resistors

+

-

Detector

RB

RL /2

RL /2

CP

Fridge

The differential readout would not be effective if the detector biasing had not the same nature: we do so.

Again for saving number of connections inside the fridge the load resistors are located at room temperature. Minimization of their noise is obtained if their value is very large. In our case RL has a value of 60 G.

The DC voltage bias, VBIAS , and RL system has been studied in the CUORE setup for having a stability of better than 50 - 80 ppm/°C.

-VBIAS

+VBIAS


Front-end configuration (5): Load resistors

Very large value resistors are normally in thick-film technology whose thermal stability is not good as for metal-film counterpart.

Although we have selected company able to obtain very good thermal drift with their products, 50 ppm/°C, we have developed a custom array that improves this results further.

5 G 25 G 10 M

In the our custom resistors the absolute drift is of the order and less than 100 ppm/°C.

Nevertheless their relative matching is in the 50 ppm/°C.

IEEE TNS, V. 49, p. 1808-1813, 2002.

1/f noise from these resistors has been optimized for this process: 1/f noise is small if the electric field per unit length is low and we selected long resistors.

http://pessina.mib.infn.it/Biblio/Biblio_Articoli/IEEE TNS V 49 p 1808 1812 2002.pdf


Front-end configuration (6): Preamplifier

What about noise of such a configuration?

In a differential configuration with have more series noise and parallel noise. The parallel noise of the load resistors is also a concern.



+

-

Our differential preamplifier is configured as an instrumentation amplifier. This way its input impedance is large, although there are only 2 transistors, 2 sources of noise, instead of 4.

+

-

-

+

Alta Frequenza, Vol. 56, N.8, p. 347-351, 1987;NIMA, Vol. A370, p.220-222, 1996;IEEE TNS, V.44, p.416-423, 1997;NIMA, Vol. 444A, p. 111-114, 2000;NIMA, Vol. 444A, p. 132-135, 2000;2009 NSS Conference Record;IEEE TNS, V. 49, p. 2440-2447, 2002.

Series noise is increased a factor of 2 with respect to the single input preamplifier.

http://pessina.mib.infn.it/Biblio/Biblio_Articoli/Alta Frequenza V 56 p 347 351 1987.pdf

http://pessina.mib.infn.it/Biblio/Biblio_Articoli/NIMA V A370 p 220 222 1996.pdf




http://pessina.mib.infn.it/Biblio/Biblio_Articoli/2009 IEEE NSS Conf Rec N13-042 pp 389 395 2009.pdf




1 10 100 1k 10k2

3

4

5

6

7

8910

Frequency (Hz)

Serie

s no

ise

(nV/

H

z)

Series noise = 5.5 nV/Hz @ 1HzSeries noise = 3.5 nV/Hz @ 10kHz

Preamplifier No.1067

IEEE NS, Vol. 51, pp. 2975-2982, 2004.

J. of Low Temp. Phys., Vol.151, p.964-970, 2008.

The JFET of our preamplifiers are semi-custom, studied for having negligible 1/f noise.

This way DC or AC coupling has no effect on noise performance.


http://pessina.mib.infn.it/Biblio/Biblio_Articoli/Journal of Low Tem Phy V 151 p 964 970 2008.pdf



+

-

RL /2

RL /2

RB

Preamplifier parallel noise takes advantage from the differential configuration.

Its contribution is made partially common mode

½

½

2Gi

2Gi

The input noise due to the 2 sources, supposed similar, is therefore:

2

222 GBi

iZv

(The noise in the single ended configuration is a factor of 2 larger, although the parallel source present is only one)



The sum of the Gate currents of both inputs at 40 °C is 160 fA, while at 30 °C is 64 fA.

0 10 20 30 40 50 60 70 800

0.5

1

1.5

2

2.5

3

T (°C)

IG (p

A)

IG(pA)40% RHcurve fit

R2 = 0.9999

y = 4.119e-3*exp( 9.113e-2*x )

Expected parallel noise is:

0.11 fA/Hz @ 40 °C;

0.07 fA/Hz @ 30 °C.

In the developed JFETs the gate current is very small, and its noise is not important although the transistor does not operate a cryogenic temperature.Parallel noise from JFETs is negligible compared to that of the load resistors.


Front-end configuration (11): Linear Power Supply

2011 NSS Conference Record;RSI, V. 70, p. 3473-3478, 1999.

Linear voltage supply:

The linear voltage supply we developed is used also as a reference for both the front-end and the detector biasing.

The actual version features about 5 ppm/°C of drift and a noise of a few tens of nV/Hz.

REC

TIFI

EDIN

PU

T V

OLT

AGE

4700F

4700F

POLARITY INVERSION:

PROTECTION REALIZED VERSION

PAPER VERSION

10 VREGULATED

VOLTAGE

10 VREGULATED

VOLTAGE

OVER/UNDER VOLTAGE

PROTECTION

OVER/UNDER VOLTAGE

PROTECTION

OVER/UNDER VOLTAGE

PROTECTION

+10V

-10V

CURRENT LIMIT AND

TRIP TIMING

CURRENT LIMIT AND

TRIP TIMING

VIN+

VIN-

VIN+

VIN-

V+

V-

VPAS+

VPAS-

4700

4700

http://pessina.mib.infn.it/Biblio/Biblio_Articoli/NSS 2011 NP2.S-89 06154540 2011.pdf

http://pessina.mib.infn.it/Biblio/Biblio_Articoli/Review of Scientific Instruments V 70 p 3473 3478 1999.pdf


Front-end configuration (12): Calibrating Pulser

IEEE TNS, V. 50, p. 979-986, 2003

RH

Fire

VREF SW

tW

The principle of operation of our pulser is very simple:

Very stable Reference voltage,1 ppm/°C

DAC + Buffer

Heather on thecrystal at cold

Decision logic circuit, -controller based,having e few 10 of ps jitter.

NTD




Outputstage

Amplitudeselector

CPLD

V-refgenerator

Digitaltransceiver

OUTS

Thermalcompensation

5V

12 bitsSCLSDA

Clock

Clock request

Selector

AUX Analog OUT

Supply voltageB

US C

ON

NEC

TOR

OU

TPUT C

ON

NEC

TOR

2 bitsbits

Simplified schematic of the actual version. New version has the logic simplified by the latest generation of ARM-Cortex -controller.



CLOCKfrom clock generator

OUTPUTPULSE

Here one example of generated pulse.

The measured signal time drift is of theactual version:

5.2 ppm/°C, for 100 s pulse width.

0.56 ppm/°C, for 1 ms pulse width.

With such a pulse we are able to fire the detectors with an accuracy close to that of the particle source, with arbitrary frequency.

As a consequence, the calibrating particle source is placed very seldom, monthly or so.



Conclusive remark:

The new pulser is more versatile in fw.

So it is not only exploitable as a pulser, but also to generate a square whose frequency and amplitude can be programmed.

This way the accuracy of the wave will be very stable and usable to AC bias the detector.

We have to verify, but square frequency up to at least 10 KHz will be affordable.

Furthermore: AC or DC biasing is tied to the value of the detector impedance, and series 1/f noise. This instrument allows to switch from AC to DC biasing on purpose. Just from the DAQ/control room terminal.

bolometer read-out in the cuore approach (that is thinking to...

Documents