bonding technologies for 3d-packaging · 2011. 11. 21. · cu-sn phase diagram 1. before bonding 3....

Bonding Technologies for 3D-Packaging

Dresden University of Technology / Electronics Packaging Laboratory

October 12th 2011

NanoZEIT seminar @ SEMICON Europa 2011 Dresden

Karsten Meier, Klaus-Juergen Wolter

Bonding Technologies for 3D-Packaging ElectronicsPackagingLaboratory

October 12th 2011

slide 2

[Eniac: European technology platform nanoelectronics, http//:nano.sdu.dk/PDF/Nanoelectronics-SRA(2).pdf, 2005, p. 31.]

System integration by SoC or SiP solutions offer advantages regardingdesign efforts, performance, power efficiency, device size, package &process cost, …


October 12th 2011

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Content

Introduction

3D-integration technologies

Bonding technologies for Package-on-Package

Die-to-Wafer technologies

Conclusions


October 12th 2011

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Introduction: Status of System in Package

[Roellig M., Beiträge zur Bestimmung vonmechanischen Kennwerten an produktkonformenLotkontakten der Elektronik, Dissertation,Technische Universität Dresden, 2008]


October 12th 2011

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Introduction: Young Researchers Group

Concepts

Technology

Production

Research focusing on

- concepts- technology- production

of/for highly reliable 3D-Microsystems[Tummala, R., PRC Georgia Tech, USA]


October 12th 2011

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Content

Introduction




Conclusions


October 12th 2011

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[Smith L., Solid StateTechnology, Vol. 54,Issue 7, 2011]

Stacked BGA-PoP with wire bonds or FC interconnects [Pahlke S., Beiträge zur Second-Level-Charakterisierung von 3D-Package-onPackage, Diploma Thesis, TechnischeUniversität Dresden, 2011]

FC interconnect wire bonds

Package-on-Package: Principles

TMV-PoP

Interposer-PoP

[Das R. N. et al., ECTC, 2011]

[Cheah B. E. et al., ECTC, 2011]

TSV-PoP


October 12th 2011

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Package-on-Package

Pro’s & Con’s:

+ Compatible to common SMT processes

+ Integration of passive components

+ Chip design independent from package

+ Testability, cost effective, high reliability

- Limited integration density compared to SiC solutions

- Warpage of sub-packages

Applications:

Smart phones, tablet PCs, SSD drives, …

Memory (die stack) on top of logic/processor unit (single die)

High density memory package (multiple die stack PoP)


October 12th 2011

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Package-on-Package: Reliability of Solder Bonds

PoP devices in e.g. smart phonesface moderate thermal cycles butserious mechanical drops

Solder joints still remain one of themajor failure sites, especially at thebottom package

Detailed knowledge on soldermaterial behaviour (creep, highstrain rate) leads to optimisedreliability

Selection of solder alloy essentiallyeffects the PoP lifetime

63 %-lifetime of 14x14 mm² PoP under -40/+125 °C30 min dwell TCT and 12x12 mm² PoP under dropimpact*up to 1750 TCT cycles no significant failure

[Pahlke S., Beiträge zur Second-Level-Charakterisierung von 3D-Package-onPackage, Diploma Thesis, TechnischeUniversität Dresden, 2011]


October 12th 2011

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Package-on-Package: Reliability of Solder Bonds

The use of underfiller significantlyenhances the PoP solder jointreliability

Application to all PoP-levels toprevent a failure site shift

Selection of underfiller has to matchboth thermo-cycling and drop loadsas well as processing and cost needs

Adhesion to the package isimportant

63 %-lifetime of 14x14 mm² PoP under -40/+125 °C30 min dwell TCT and 12x12 mm² PoP under dropimpact without or with underfill*up to 1750 TCT cycles no significant failure

[Pahlke S., Beiträge zur Second-Level-Charakterisierung von 3D-Package-onPackage, Diploma Thesis, TechnischeUniversität Dresden, 2011]


October 12th 2011

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Package-on-Package: Future Developments

stacked thin dies

SLID interconnects

ACANWF interconnect

Si-interposer

TSVs

TMVs

organic interposer

solder balls

PoP design - Integration of novel interconnect technologies:

solder ball or Cu pillar (2nd level)TSV (interposer or 1st level)SLID (stacked dies)nanowire-filled adhesive film (ACANWF, bottom die)organic or silicon interposer

compliancyhigh density, shorthigh density, no re-meltvery high density, TIMmatching CTE


October 12th 2011

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Content

Introduction




Conclusions


October 12th 2011

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Die-to-Wafer: SLID – Motivation & Concept

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w.m

etal

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Cu-Sn phase diagram

1. before bonding 3. complete transition to IMCs

SLID

Cu-SnAu-Sn

Cu-SnAg…

thermostable joints (IMCs)

enables multistacking of chips

small joints (


October 12th 2011

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Die-to-Wafer: SLID

Research goals:

Study diffusion kineticsAdjust cleaning processOptimisation of bonding conditionsReliability characterisation

Backscattered SEM image of the Cu/Sninterconnect showing intermetallicphases (Cu6Sn5, Cu3Sn) and voids


October 12th 2011

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Die-to-Wafer: Self Alignment – Principles

Self-alignment for electronics packaging:

Well-known phenomenon with SMT: self-alignment by liquid solder

Reflow

magnetic:

S.B. Shetye et al.,University of Florida

by liquid: electrostatic:

J. Dalin, J. WildeUniversität Freiburg

surfacetension

Capillary action

Various research on self-alignment in the past:

Basic principle: force on the component to minimise free energy


October 12th 2011

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Die-to-Wafer: z-Self Alignment

3D die stacking – assembly of warped thin dies:

z-self alignment to reduce die warpageUse capillary action

Influence of intitial warpageWetting behaviourGeometry effects (pitch, gap height, volume of the liquid)Behaviour of the liquid (viscosity, curing demands)Temperature effects (intrinsic stresses)Enable integrated interconnect process

substrateliquid

warped die


October 12th 2011

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Die-to-Wafer: z-Self Alignment

Orientation of the initial warpage (die size 10x10 mm², 50 µm; warpage 47 µm)

23.8

5.7

0

10

20

30

40

50

concave convex

die

war

page

[µm

]initial state under capillary action

die warpageorientation:

concave

convex

Warpage reduction by >85%


October 12th 2011

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Die-to-Wafer: Nanowire arrays for 3D bonding

Active die

Cu bumps

ACANWF

InterposerTSV Passivation layer SiO2 Adhesion promoter(SiO2, TaN, …) Si TSV (Cu)

Chip level

ACANWF

Film filled with vertically oriented nano-scaled interconnects:

Ongoing demand for higher I/Os and smaller sizeNeed for compliant interconnectsNeed for thermal management

Template processing (thinning, create nano-sized pores)Pore fillingTransition of nanowires into film (ACANWF)


October 12th 2011

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Die-to-Wafer: Nano Wire Arrays for 3D Bonding

a)SEM images of AAO template

b)Scheme of the electrodepositionof NWs in AAO membranes

c)SEM images of electrodeposited Ag NWs still inside the template

p = 100 nm, d = 50 nm

l = 20 µm


October 12th 2011

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Typical diameters: 5…20 µmAspect ratio: up to 1:10 (ITRS predicts 20:1)Isolation (SiO2) 400 nmBarrier-Layer (Ta/TaN) respectively 80 nmSeed-Layer (Cu) 600 nm

[Lerner et al., FutureFab, Issue 26, 2008]

[Wolf et al., ESTC, 2010]

[Powel et al., IITC, 2008]

[Wolf et al., ESTC, 2010]

TSV-layers

Cu-filled TSVs (d=20µm)

Etched Si (Bosch process)

Scallops in Si and SiO2-isolation layer

[Laviron et al., ECTC, 2009]

unfilled TSVs (d=5µm)

Die-to-Wafer: TSV - dimensions


October 12th 2011

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Die-to-Wafer: TSV – Cu grain structure

Cu grain structure influences mechanical behaviour

Strong anisotropy depending on crystal orientationSmall size TSVs potentially contain only a few grain orientationsMechanical behaviour is essential for simulation work (FEM)Model performance restricts covering actual grain structure

Analyse Cu grain structure depending on TSV size, processingand annealing conditions (EBSD)Model a characteristic section of one TSVDetermine an effective material description

EBSD mapping: [001] Inverse pole figure


October 12th 2011

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Die-to-Wafer: TSV - FEM

Cu grain structure influences mechanical behaviour

2D FEM model automatically build from a EBSD measurement(grain structure and orientation)Application of tensile loadsDetermine effective elastic behaviour

Early result: Important for smaller TSVs (


October 12th 2011

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Content

Introduction




Conclusions


October 12th 2011

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Conclusions

Two major SiP approaches within 3D integration:

die stacks – KGD, performance, high integration, …

PoP – testability, cost effective, flexibility, medium integration, …

PoP technology:

Package for mobile applications – ongoing development & improvement

Good TCT and drop reliability – design for low warpage

Potential D2W-technologies:

SLID for die stacking w/o re-melting – key factors planarity and cleaning

z-self alignment by capillary action for warpage reduction

ACANWF shows potential for high density interconnections

TSV simulation studies demand detailed but efficient material models

Thank you!

[email protected]

+49 351 463 36 594

bonding technologies for 3d-packaging · 2011. 11. 21. · cu-sn phase diagram 1. before bonding 3....

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