bottom half – ch 0-5 placed & routed fe ps proc fifo trig osc rx/shap adc dac vme
DESCRIPTION
Remaining board design work Test pulser (sch+layout) Input signal routing (goes around test pulser stuff, do that 1 st ) +1.5V reference (sets ADC input common-mode) A few more connections to define on main/vme FPGA offset DAC control switching regulator phase control status LED’s sub new FET part for RX power supply (prototype ran too hot) pcb mechanical – handle mounts, VXS connector placement thermal vias for ADC chips some bypass caps to be added still local trigger (multiplicity sum line and trigger comparator) +2.5V linear regulator (for VCCAUX & digital signals), Xpower estimate work to check 1 st Then: channel step & repeat copy to mezzanine board flip connectors to bottom for mezzanine board Then: clean silkscreen final DRC review, review, review… fabricateTRANSCRIPT
Bottom half – ch 0-5 placed & routed
FEPS
PROC
FIFOTRIG
OSC
RX/SHAP
ADC
DAC
VME
Top half
JTAG
PS
MAIN
FE
VME
FLASH
Remaining board design work • Test pulser (sch+layout)• Input signal routing (goes around test pulser stuff, do that 1st)• +1.5V reference (sets ADC input common-mode)• A few more connections to define on main/vme FPGA• offset DAC control• switching regulator phase control• status LED’s
• sub new FET part for RX power supply (prototype ran too hot)• pcb mechanical – handle mounts, VXS connector placement• thermal vias for ADC chips• some bypass caps to be added still• local trigger (multiplicity sum line and trigger comparator)• +2.5V linear regulator (for VCCAUX & digital signals), Xpower estimate work to check 1st
Then:
• channel step & repeat• copy to mezzanine board• flip connectors to bottom for mezzanine board
Then:
• clean silkscreen• final DRC• review, review, review…• fabricate