boylestad electronics multiple choice q&a chapter (13)
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boylestad electronics multiple choice q&a chapter 13TRANSCRIPT
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Site Title: Electronic Devices and CircuitTheory
Book Author: Boylestad
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Chapter 13 > Multiple Choice
Date/TimeSubmitted:
October 12, 2012 at 12:46 AM(UTC/GMT)
Summary of Results
20% Correct of 35 Scored items:
7 Correct: 20%
28 Incorrect: 80%
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1. Which of the following is not a linear/digital IC?
Your Answer: Phase-locked loop
Correct Answer: Passive filter
2. Which of the following circuits is (are) linear/digital ICs?
Your Answer: Timers
Correct Answer: All of the above
3. Which of the following is (are) the results of improvements built into acomparator IC?
Your Answer: Outputs capable of directly driving a variety of loads
Correct Answer: All of the above
4. How many comparators does a 339 IC contain?
Your Answer: 2
Correct Answer: 4
5. This circuit is an example of a ______.
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Your Answer: comparator
6. A 311 IC is an example of an eight-pin DIP that can be made to function as a_____.
Your Answer: D to A converter
Correct Answer: comparator
7. A 339 IC is an example of a fourteen-pin DIP that can be made to functionas a _____.
Your Answer: D to A converter
Correct Answer: comparator
8. What is the function of a ladder network?
Your Answer: Changing a digital signal to an analog signal
9. What is (are) the level(s) of the input voltage to a ladder-networkconversion?
Your Answer: 0 V or Vref
10. What is the level of the output voltage of a ladder-network conversion?
Your Answer: A fixed digital value Vref
Correct Answer: The analog output voltage proportional to the digitalinput voltage
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11. What is the voltage resolution of an 8-stage ladder network?
Your Answer: Vref /256
12. Which of the slope intervals of the integrator does the counter in theanalog-to-digital converter (ADC) operate?
Your Answer: Negative
Correct Answer: Both positive and negative
13. What is the first phase of the dual-slope method of conversion?
Your Answer: Setting the counter to zero
Correct Answer: Connecting the analog voltage to the integrator for afixed time
14. When is the counter set to zero in the dual-slope method of conversion?
Your Answer: At the end of the charging of the capacitor
15. Which of the following devices is (are) a component of a digital-to-analogconverter (DAC)?
Your Answer: All of the above
16. At which of the following period(s) is the counter advanced (incremented) indual-slope conversion?
Your Answer: During both the charging and discharging of the capacitorof the integrator
Correct Answer: During the discharging of the capacitor of the integrator
17. What is (are) the input(s) to the comparator in the ladder-networkconversion of an ADC?
Your Answer: Analog input voltage
Correct Answer: Both staircase and analog input voltage
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18. What is the maximum conversion time of a clock rate of 1 MHz operating a10-stage counter in an ADC?
Your Answer: 1.024 s
Correct Answer: 1.024 ms
19. What is the minimum number of conversions per second of a clock rate of 1MHz operating a 10-stage counter in an ADC?
Your Answer: 697
Correct Answer: 976
20. On which of the following does the conversion depend in ladder-networkconversion?
Your Answer: Digital counter
Correct Answer: Comparator
21. This circuit is an example of a _____.
Your Answer: 555 timer
Correct Answer: ladder network
22. This figure is a block diagram of a(n) _____.
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Your Answer: DAC
Correct Answer: ADC
23. Calculate the frequency of this circuit.
Your Answer: 450 Hz
Correct Answer: 128 Hz
24. The 555 timer IC is made up of a combination of linear comparators anddigital flip-flops.
Your Answer: False
Correct Answer: True
25. Which application best describes this 555 timer circuit?
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Your Answer: Bistable multivibrator
Correct Answer: Astable multivibrator
26. Which application best describes this 555 timer circuit?
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Your Answer: Bistable multivibrator
Correct Answer: Monostable multivibrator
27. Which of the following best describes the output of a 566 voltage-controlledoscillator?
Your Answer: None of the above
Correct Answer: Both square- and triangular-wave
28. Which of the following best describes limitations for the 566 VCO?
Your Answer: fo < 1 MHz
Correct Answer: All of the above
29. Determine the free-running frequency for this circuit.
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Your Answer: 533.3 kHz
Correct Answer: 53.33 kHz
30. Determine the free-running frequency when R3 is set to 2.5 k .
Your Answer: 212.9 kHz
Correct Answer: 116.39 kHz
31. The voltage-controlled oscillator is a subset of the "test bench" functiongenerator.
Your Answer: False
Correct Answer: True
32. Which of the following applications include a phase-locked loop (PLL) circuit?
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Your Answer: Tracking filters
Correct Answer: All of the above
33. How many Vcc connections does the 565 PLL use?
Your Answer: 3
Correct Answer: 2
34. The timing components for a PLL are 15 k and 220 pF. Calculate the free-running frequency.
Your Answer: 181.8 kHz
Correct Answer: 90.91 kHz
35. Which of the following frequencies is associated with the 565 frequency-shiftkeyed decoder?
Your Answer: Both 1070 Hz and 1270 Hz