breaking the 32 gb/s barrier: pcb materials, simulations

Breaking the 32 Gb/s Barrier:

PCB Materials, Simulations,

and Measurements

Fundamentals of PCB Materials and Fabrication as They Relate to Ultra High Speed Signaling Speaker - Lee Ritchey, Speeding Edge

Part 1:

TOPICS

1. Fundamentals of PCB Materials and Fabrication as Relates to Ultra High Speed Signaling- Lee Ritchey, Speeding Edge

2. Fundamentals of Matching Measurements with Simulations for PCB Channels- Heidi Barnes and Tim Wang, Keysight

3. Using Test Fixtures as Standards for Benchmarking 3D Solvers and Measurements to 32 Gb/S- Al Neves, Wild River

13-TU2 Breaking the 32 Gb/s Barrier: PCB Materials, Simulations, Measurements

2

• Achieving repeatable, predictable simulation and fabrication results requires detailed knowledge of the materials and fabrication processes involved in the manufacture of PCBs used in very high speed data paths.

• Many of the disconnects between simulations and measurements can be traced to failure to understand and control some of these variables when designing test and production PCBs.

• This section of this tutorial is intended to provide the materials and process information needed to succeed with the design and measurement of these very high speed data paths.

• The two sections that follow this one, Matching Measurements to Simulations and Using Test Fixtures as Standards, will complete this tutorial.

Fundamentals of PCB Materials and Fabrication as Relates to Ultra High Speed Signaling- Lee Ritchey, Speeding Edge


3

Topics to be Covered in Materials and Fabrication

1. Materials used to fabricate PCBs

2. Fabrication methods

3. Fabrication process flow

4. Potential signal integrity problems with materials and fabrication

5. Documentation required to achieve repeatability and reliability when designing PCBs


4

Materials Used to Fabricate PCBs

• There are three basic building block used to fabricate PCBs. These are:

1. Copper foils

2. Prepregs or uncured glass/resin composites

3. Laminates made from glass/resin composites that have copper foils on both sides of the cured glass/resin composite.

• There are dozens of resin systems and many glass weave styles.


5

Copper Foils

• Copper foils are available in a number of thicknesses. Among these are: half ounce (0.7 mils, 18 microns) thick, one ounce (1.4 mils, 36 microns) thick and 2 ounce (2.8 mils, 72 microns) thick.

• Copper foils have a variety of surface finishes from very smooth to quite rough. The rough surface finishes were formulated to create a strong bond between the copper surface and the resin used in the laminate.

• Some common surface finishes are: RTF (reverse treat, the most common finish), VLP (very low profile) and HVLP ( ultra low profile)


6

Prepregs

• Prepregs or “B” stage material is a woven glass cloth saturated with resin that is not fully cured.

• Prepregs are the “glue” layers that bond all of the layers of a multilayer PCB together during the lamination cycle.

• During lamination, the resin in the prepreg is heated and flows into the openings in the adjacent copper layers, eliminating voids.

• Once the resin has flowed into the openings in the adjacent copper layers, the temperature is raised causing the resin to cure into solid laminate.

• After lamination, the prepreg has the same appearance as the laminate used to create the signal and plane layers.


7

A Typical Prepreg Data Sheet

Notice that the er or DK changes with the percentage resin in the prepreg as well as with frequency. Also, note the variety of glass weave styles listed under the prepreg heading.

Data courtesy of Isola.

Prepreg

Resin Thickness Thickness Dk Dk Dk Dk Dk Dk Dk Dk

Content ( in ) ( mm ) at 100 MHz at 500 MHz at 1 GHz at 2.0 GHz at 5.0 GHz at 10.0 GHz at 15.0 GHz at 20.0 GHz

106 77.0% 0.0022 0.057 3.44 3.44 3.44 3.43 3.43 3.43 3.43 3.43

106 80.0% 0.0026 0.066 3.41 3.40 3.40 3.40 3.40 3.40 3.40 3.40

1035 MS 71.5% 0.0021 0.054 3.51 3.50 3.50 3.50 3.50 3.50 3.50 3.50

1035 MS 75.5% 0.0025 0.063 3.46 3.46 3.45 3.45 3.45 3.45 3.45 3.45

1035 MS 79.0% 0.0030 0.075 3.42 3.41 3.41 3.41 3.41 3.41 3.41 3.41

1067 MS 72.5% 0.0023 0.058 3.49 3.49 3.49 3.49 3.49 3.49 3.49 3.49

1067 MS 75.0% 0.0025 0.064 3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46

1067 MS 77.5% 0.0028 0.072 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43

1080 69.0% 0.0031 0.078 3.54 3.53 3.53 3.53 3.53 3.53 3.53 3.53

1080 74.0% 0.0037 0.095 3.48 3.47 3.47 3.47 3.47 3.47 3.47 3.47

1078 MS 68.5% 0.0030 0.076 3.54 3.54 3.54 3.54 3.54 3.54 3.54 3.54

1078 MS 73.0% 0.0036 0.091 3.49 3.48 3.48 3.48 3.48 3.48 3.48 3.48

1078 MS 76.0% 0.0041 0.103 3.45 3.45 3.45 3.45 3.45 3.45 3.44 3.44

3313 61.0% 0.0040 0.103 3.64 3.64 3.64 3.64 3.64 3.64 3.63 3.63

3313 64.5% 0.0045 0.115 3.59 3.59 3.59 3.59 3.59 3.59 3.59 3.59

3313 68.0% 0.0051 0.129 3.55 3.55 3.55 3.54 3.54 3.54 3.54 3.54

3313 70.0% 0.0055 0.139 3.52 3.52 3.52 3.52 3.52 3.52 3.52 3.52

2116 60.5% 0.0051 0.128 3.65 3.65 3.64 3.64 3.64 3.64 3.64 3.64

2116 66.5% 0.0061 0.156 3.57 3.57 3.56 3.56 3.56 3.56 3.56 3.56


8

Laminates

• Laminates are glass cloth saturated with resin that has a sheet of copper foil bonded to each side. The same resin used in the prepreg layers of a PCB is used in the laminates to insure compatibility.

• Laminates are available in a wide range of thicknesses and can be ordered with several different thicknesses of copper bonded to each side.

• It is possible to order laminate with different thickness copper on each side.

• A caution: thicker copper requires thicker prepreg to provide enough resin to fill the voids in the thick copper, driving overall PCB thickness up.


9

A Typical Laminate Data Sheet

Data courtesy of Isola

Notice that the er or DK changes with the percentage resin in the laminate as well as with frequency.

Also, note the variety of glass weave styles listed under the standard heading.

Notice that there are three very different laminates that are 5 mils (125 microns) thick with very different e r values.

Copper foil thickness on each side is customer specified.

Core Core Standard Resin Dk Dk Dk Dk Dk Dk Dk Dk

Thickness (in.) Thickness (mm) Constructions Content at 100 MHz at 500 MHz at 1 GHz at 2.0 GHz at 5.0 GHz at 10.0 GHz at 15.0 GHz at 20.0 GHz

0.0020 0.051 1035 MS (Not ZBC) 71.5% 3.51 3.50 3.50 3.50 3.50 3.50 3.50 3.50

0.0025 0.064 1- 1067 MS 75.0% 3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46

0.0030 0.076 1- 1078 MS 68.5% 3.54 3.54 3.54 3.54 3.54 3.54 3.54 3.54

0.0033 0.084 1- 1078 MS 71.0% 3.51 3.51 3.51 3.51 3.51 3.51 3.50 3.50

0.0035 0.089 2- 1035 MS 66.5% 3.57 3.57 3.56 3.56 3.56 3.56 3.56 3.56

0.0035 0.089 1- 3313 56.5% 3.70 3.70 3.70 3.70 3.70 3.70 3.70 3.70

0.0040 0.102 2- 1035 MS 71.5% 3.51 3.50 3.50 3.50 3.50 3.50 3.50 3.50

0.0040 0.102 2- 1067 MS 70.0% 3.52 3.52 3.52 3.52 3.52 3.52 3.52 3.52

0.0040 0.102 1- 3313 61.0% 3.64 3.64 3.64 3.64 3.64 3.64 3.63 3.63

0.0045 0.114 2- 1067 MS 72.5% 3.49 3.49 3.49 3.49 3.49 3.49 3.49 3.49

0.0045 0.114 1- 3313 64.5% 3.59 3.59 3.59 3.59 3.59 3.59 3.59 3.59

0.0050 0.127 2- 1067 MS 75.0% 3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46

0.0050 0.127 1- 3313 68.0% 3.55 3.55 3.55 3.54 3.54 3.54 3.54 3.54

0.0055 0.140 2- 1078 MS 66.0% 3.58 3.57 3.57 3.57 3.57 3.57 3.57 3.57

0.0060 0.152 2- 1078 MS 68.5% 3.54 3.54 3.54 3.54 3.54 3.54 3.54 3.54

0.0060 0.152 2- 1080 69.0% 3.54 3.53 3.53 3.53 3.53 3.53 3.53 3.53

0.0066 0.168 2- 1078 MS 71.0% 3.51 3.51 3.51 3.51 3.51 3.51 3.50 3.50

0.0070 0.178 2- 1078 MS 73.0% 3.49 3.48 3.48 3.48 3.48 3.48 3.48 3.48

0.0070 0.178 2- 3313 56.5% 3.70 3.70 3.70 3.70 3.70 3.70 3.70 3.70


10

Fabrication Methods

• There are three basic methods for constructing a multilayer PCB. These are:

1. Foil lamination

2. Cap lamination

3. Build up or HDI lamination

• How each is done and their merits and drawbacks will be explained in the following slides.


11

Foil Lamination

Foil lamination creates inner layers in pairs with the outer layers made of sheets of copper foil. Prepreg separates the pieces of laminate, gluing them together during lamination. It is the most cost effective lamination method.

FOIL

FOIL

LAMINATE

PREPREG/

B STAGE

PREPREG/

B STAGE

PREPREG/

B STAGE

LAMINATE

LAYER 1

LAYER 6

LAYERS 4 & 5

LAYERS 2 & 3

STACK UP FOR 6 LAYER PCB AS IT

ENTERS LAMINATION (FOIL LAMINATION)

LAMINATE IS GLASS/EPOXY

WITH SIGNAL OR POWER

PLANES ETCHED ON BOTH

SIDES

PREPREG IS GLASS/EPOXY

THAT IS PARTIALLY CURED FOIL IS SHEET OF

COPPER FOIL


12

Cap Lamination

Cap lamination creates all layers using pieces of laminate. Prepreg separates the laminates, gluing them together during lamination. It is the second least expensive method for fabricating a multilayer PCB.


13

Build Up or HDI Lamination

Build up lamination or HDI uses either foil lamination or cap lamination to create a core. Prepreg and foil are bonded to each side with a second lamination step followed by laser drilling blind vias. This may be repeated a number of times to create additional layers. It is the most expensive way to fabricate a multilayer PCB.

8 Layer Build Up PCB with 6 Layer Core 6Layer Build Up PCB with 4 Layer Core


14

Fabrication Process Flow

Core

Solder Mask

Prepreg

Prepreg

Prepreg

Prepreg

Core Core

Prepreg Prepreg Prepreg

Core Core Core

Prepreg Prepreg

Core

1.

FRONT END

ENGINEERING

2.

INNER LAYER

PROCESSING

3.

LAMINATION

4.

DRILLING AND

PLATING

5.

OUTER LAYER

PROCESSING

6.

TESTING

TYPICAL MULTILAYER PCB

FABRICATION PROCESS

CHECK DATA FOR ACCURACY

PREPARE ARTWORK

CREATE DRILL FILE

CREATE TEST TOOLING

BUILD TRAVELER

SCHEDULE MATERIALS

CLEAN INNER LAYER COPPER

APPLY ETCH RESIST DEVELOP ETCH RESIST

ETCH INNER LAYER PATTERNS

REMOVE ETCH RESIST

OPTICALLY INSPECT COPPER

PATTERNS

ROUGHEN COPPER SURFACES

PUNCH REGISTRATION HOLES

ARRANGE INNER LAYERS,

PREPREG AND OUTER LAYER

COPPER INTO A STACKUP

PRESS ALL LAYERS

COOL DOWN STACK

XRAY TO LOCATE INNER

LAYER DRILL TARGETS

DRILL ALL THROUGH HOLES

CLEAN DEBRIS FROM HOLES

APPLY PLATING RESIST

PLATE COPPER

PLATE ETCH RESIST

STRIP PLATING RESIST

ETCH AWAY UNWANTED COPPER

STRIP ETCH RESIST

APPLY SOLDER MASK

APPLY LEGEND

APPLY COPPER FINISH

CUT PCB FROM PANEL

PERFORM SHORTS AND

OPENS TEST

PERFORM IMPEDANCE TESTS

CROSS SECTION COUPONS

SPEEDING EDGE 2006


15

Potential SI Problems With Materials and Fabrication

• There are several places that signal integrity of high speed signals can be adversely affected stemming from materials choices and fabrication techniques. Among these are:

1. Increased loss due to copper foil finish.

2. Increased loss due to fabricator’s treatment of foil.

3. Increased loss due to laminate choices

4. Impedance irregularities due to glass style choices


16

Copper Foil Surface Finish Effects

• Choice of copper foil finish can directly affect path loss.

• These are two identical traces in the same test PCB with one layer using VLP copper foil and the other using RTF (reverse treat) copper.

-16.0

-14.0

-12.0

-10.0

-8.0

-6.0

-4.0

-2.0

0.0

0 5 10 15

Lo

ss -

dB

Frequency - GHz

GigaSync dB Loss vs. Freq for 8" Trace

Cu=VLP Cu=RTF


17

Cross Sections of Traces on Previous Slide

HVLP FOIL REVERSE TREAT FOIL


18

Copper Loss Due to Fabricator Treatment

Two PCBs built at two different fabricators using the same materials and the same stackup yield different losses due to differing surface roughness done during processing. Copper roughness has been left to each fabricator. With the advent of 10 Gb/S and higher signal paths, this is no longer allowable. Test structure is 7” Daughterboard made from FR408HR, 13” backplane made from Megtron 6 and 7” daughter board made from FR408HR. Only daughter boards were from different fabricators.

35 db at 8 GHz 40 db at 8 GHz


19

CROSS SECTION OF TWO PCBS ON PREVIOUS SLIDE

Poor Loss Good Loss

Supplier # 2 Oxide Supplier # 1 Oxide

3.5 microns 1.2 microns

Slide 38


20

Increased Loss Due to Laminate Choice

Light Blue – Tachyon

Pink – Terragreen

Green – I-Tera

Blue – Megtron 6

Purple – I-Speed

Red – Megtron 4

4” (10.2 cm) long, 4.5 mil (112 micron) wide, stripline trace.


21

Two Common Glass Weaves Styles

1080 GLASS WEAVE 3313 GLASS WEAVE

(very open weave) (uniformly spread weave)

A 3.5 MIL WIRE IS SPREAD ACROSS THE WEAVE TO PROVIDE SCALE OF A TYPICAL TRACE

[1080 glass has long been used to create 3 mil cores and prepregs. Notice that the wire on the left travels over

a glass bundle (er ≈ 6) for part of its length and then between two glass bundles (er ≈ 3) for part of its length.]


22

Impedance Variation of Two Glass Weaves on Slide 22

Center line is 50 ohms. Upper and lower lines are +- 10%

(Where the impedance is low, the dielectric constant is high meaning the trace is travelling over nearly

pure glass (high er/ slow velocity). Where the impedance is high, the trace is travelling over nearly

pure resin (low er/higher velocity).

1080 GLASS WEAVE 3313 GLASS WEAVE

(very open weave) (uniformly spread weave)


23

Stackup Drawing With Proper Data Call Outs

Layer

#

Material

Name

Material

Type Material Construction

Copper

Type S =

RTF, X =

HVLP

Material

Pressed Er

(at ~2

GHz)

Material

Unpressed

Thickness

(mils)

Material

Pressed

Thickness

(mils) Picture

Copper

Thickness

(mils)

Copper

Thickness

(oz)

Single

Ended

Trace

Width

(mils)

0.7

1 Top 1 2.2 1.5

I-SPEED Prepreg 1 x 3313MS RC = 59% 3.73 4.3 4

2 Ground X 2 0.6 0.5

I-SPEED Core 1 x 3313MS RC = 57% core 3.77 4

3 Sig 1 X 3 0.6 0.5 4.75

I-SPEED Prepreg 2 x 3313MS RC = 59% 3.73 8.6 8.1

4 GND X 4 0.6 0.5


5 Sig 2 X 5 0.6 0.5 4.75


6 GND X 6 0.6 0.5


7 Sig 3 X 7 0.6 0.5 4.75


8 GND X 8 0.6 0.5

I-SPEED Core 3 x 1652 RC = 50% core 18

9 GND X 9 0.6 0.5


10 Sig 4 X 10 0.6 0.5 4.75


11 GND X 11 0.6 0.5


12 Sig 5 X 12 0.6 0.5 4.75


13 GND X 13 0.6 0.5


14 Sig 6 X 14 0.6 0.5 4.75


15 Ground X 15 0.6 0.5

I-SPEED Prepreg 1 x 3313MS RC = 59% 3.73 4.3 4

16 BOTTOM 16 2.2 1.5

0.7

-------- --------

100.0 112.8 12.8

Material

Thickness Total Thickness

Copper

Thickness

Prepreg

Core

Core

Core

Core

CoreCore

Core

Core

Solder Mask

Prepreg

Prepreg

Prepreg

Prepreg

Prepreg

Prepreg

Prepreg

PrepregPrepreg

Prepreg

Prepreg

Prepreg

Prepreg

Prepreg

Prepreg

Core

Core

Core

Core

Core

CoreCore

PrepregPrepreg

Core

CoreCore

PrepregPrepreg

Core

Core

Core

Core

PrepregPrepreg

CoreCoreCoreCore

Core

PrepregPrepregPrepreg

CoreCoreCore

PrepregPrepreg

Core

PrepregPrepregPrepregPrepreg

Solder Mask

CoreCoreCore

Prepreg

Prepreg

CorePrepreg

CorePrepreg

CoreCoreCore

CoreCoreCore

CoreCoreCore

Note: Glass style, resin system and glass to resin ratios are all specified and are not negotiable at fabricator. Also, note that the copper profile has been specified.


24

Conclusions About Effects of Materials and Fabrication Choices on Ultra High Speed Data Paths

1. Choice of laminates, prepregs and copper foils can have a significant effect on the quality of a high speed data path.

2. Current practices in the fabrication of PCBs do not account for many of the variables that are important. As a result, many attempts to correlate simulations to measured results are difficult or inconclusive.

3. The parameters that must be controlled to insure reliable, repeatable results are well understood.

4. Documentation must be prepared that contains enough information for each design and adhered to by fabricators.


25



and Measurements

Part 2- Fundamentals of Matching Measurements with Simulations for PCB Channels Speaker – Heidi Barnes, Keysight Technologies

Chun-Ting “Tim” Wang Lee, Wild River Technology

Achieving Stellar Measurement to Simulation to 40 GHz and 32Gb/s


27

Today’s Objective

w= 11 mils L= .75 in

250 mil

250 mil 342 mil

w= 11 mils L=.75 in

2.92mm 2.92mm


28

Today’s Objective

Measurement

Simulation with Measurement-Based-Model

Simulation from Data Sheet


29

Simulation to Measurement – 40GHz, 32Gb/s- What Does it Take?

It is really not very easy!

Why, and what is Involved?


30

Stellar Match, Down to the Last Ripple!


31

Everything needs to work together –

• DUT definition

• Fixture design

• Measurements

• De-embed approach

• Material identification

The Big Picture


32

SDUT for Simulation to Measurement

Usually, but not always, you want to focus on DUT correspondence, and not the impact of imperfect launches and losses in T-lines

Validate calibration with NIST standards, if you could connect reference 1+2 with a flush through a perfect calibration would have no reflections and no loss.

Port 1 Port 2 ref 1 ref 2 SDUT


33

Terms and Related Concepts

S1x_fixture _left

Port 1 Port 2

SDUT Port 1 Port 2

THRU+Beatty+250mils relief on each side of DUT

S1x_fixture _right

S2x_fixture_thru

Sfixture_DUT_fullpath


34

Assume S T T is T-matrix, versus S-parameter

TDUT=[T1x_fixture_lefthalf]-1 [Tfixture_DUT_fullpath] [T1x_fixture_righthalf]

-1

T2x_fixture_thru=[T1x_fixture_lefthalf] [T1x_fixture_righthalf]

Symmetrical De-Embed Concept


35

The Reality of Measurements 1. Some sort of “Fixture” is required to get from the instrument “coax” to

the non-standard DUT interface such as PCB internal Stripline.

2. The fixture needs to be characterized and de-embedded from the measurement, or verified as “transparent” for the given application.

3. Complicated TRL methods, and the need for adapters to connect with traditional cal-kits can create unexpected errors in the calibration process. Test Structures enable engineers to verify and

understand the accuracy of the fixture removal method and the ability to accurately measure the signal integrity of just the DUT.


36

The Reality of Simulations

1. Simulations are only as accurate as the available material properties and fabrication tolerances.

2. It is not easy to include the measurement fixture in simulations.

3. Accurate placement of reference planes is critical when cascading Fixture S-Parameters with DUT S-Parameters. Test structures enable engineers to verify the

as-fabricated material properties and understand the limitations of the simulation and measurements.


37

Stripline Beatty Standard 25 Ohm w= 11 mils L=250 mils

w= 11 mils L=250 mils

w= 33 mils L=1.0 in

w= 11 mils L=750 mils

w=11 mils L=750 mils

2.92mm 2.92mm

Resonant structures like the Beatty Standard are excellent for calibration

validation in both Simulation and Measurement

Simulate

32 Gb/s PRBS9

Measure TDR SP


38

The Beatty Standard – Loss modeling, Calibration Validation, Benchmarking Simulations

• Tim Wang Lee, Wild River Technology

• Al Neves

Outline • Beatty Standard

– Where did it start? – What is it? – So what?

• Resonator Basics and Background – Wavelength, frequency and velocity of propagation – Velocity of propagation and Dk – Wave interference – Parallel and series resonators

• Loss Modeling Applications – Dk – Etch-back/over-plate width extraction – Dielectric thickness extraction – Loss modeling

• Conductor • Dielectric

• Summary

• Beatty Standard

• Resonator Basics and Background

• Loss Modeling Applications

• Summary

BEATTY STANDARD

Where did it start? What is it? So what?

00 Zw w 03Beatty Zw w

00 Zw w

1 inchL 1

2 inchL 12 inchL

“Additional evaluation of this type of standard is in progress to determine its scope of application.” -R.W. Beatty 1973

Where did it start?

2

0 1

0 2

1

VSWR

S

S

Z

Z

Where did it start? In the original paper, Beatty standard consists of a quarter-guide-wavelength (λg/4) section of waveguide that terminated by a section of waveguide having the same impedance as the measuring system1.

1: R.W. Beatty, “2-Port 1/4L Waveguide Standard of Voltage Standing-Wave Ratio” Electronics Letters 25th January 1973, Vol 9, No. 2.

0Z Z

BeattyZ

4

gL

0Z Z

What is it? To perform accurate material extraction (especially loss), the reference 50 ohm section is extended on each side of the Beatty standard so that impedances and losses of the 2 trace widths are contributing to the measured data. To ensure a measurable amount of loss for a PCB structure, a standard 1 inch Beatty section is used.

00 Zw w 03Beatty Zw w

00 Zw w

1 inchL 1

2 inchL 12 inchL

Broad Band Definition With Losses

Picture credit: Barnes, H.; Schaefer, R.; Moreira, J., "Analysis of test coupon structures for the extraction of high frequency PCB material properties-White paper," 3 August 2014

Beatty Standard-So What?

2: Barnes, H.; Schaefer, R.; Moreira, J., "Analysis of test coupon structures for the extraction of high frequency PCB material properties," Signal and Power Integrity (SPI), 2013 17th IEEE Workshop on , vol., no., pp.1,4, 12-15 May 2013

1. Subtle change in trace width (etch-back or over-plate) can be extracted by analyzing the delta impedance change for the 3x increase in Z0 trace width2.

2. Insertion loss which is affected by dielectric constant and loss tangent can be extracted by examining the overall loss vs frequency as well as the peak-to-peak magnitude of the resonating ripples2.




• Summary

RESONATOR BASICS AND BACKGROUND

Wavelength, frequency and velocity of propagation

Velocity of propagation and Dk

Wave interference

Parallel and series resonators

Wavelength, Frequency and Velocity

1v s

t

;distance

timedista timence;S tv

p

v

wavelengths

periodt p

frequencyf 1

pf

1f

pv

Velocity of Propagation and Dk

0

1

Dk

cv

speed of light in vacuum

Dk dielectric constant

c

Dkp

cv

1 12 inch

nsecDkpv

s

0vt

0v c

4

6 inch

nsecFRv




Wave interference


Wave Interference The Principle of Superposition: For all linear systems, the net response at a given place and time caused by two or more stimuli is the sum of the responses which would have been caused by each stimulus individually.

1 1( ) yF x 2 2( ) yF x

1 2 1 2( ) yF x x y

Constructive Interference Waves are in phase.

1y

2y

1 2y y

Destructive Interference Waves are out of phase.

1 2y y2y

1y




Wave interference


Parallel and Series Resonators Wildriver Techonology (Booth# 751) WRT CMP-28 EDA Kit includes: 1. Series Beatty resonator 2. Parallel Stub resonator 3. AND MORE!

Parallel Stub Resonator

w= 11 mils L= .75 in

250 mil

250 mil 342 mil

w= 11 mils L=.75 in

2.92mm 2.92mm

Parallel Stub Resonator (L=λ/4)

Given: g

p

pv

t

Destructive Interference

4

gL

t4

p

t2

p

1


Quarter-wavelength stub (L=λ/4) 1. Destructive interference 2. Virtual short 3. Cancellation of waves 4. Minimum transmission (S21)


2

gL

t

Constructive Interference

t2

p

tp

1

Given: g

p

pv


Half-wavelength stub (L=λ/2) 1. Constructive interference 2. Virtual open 3. Addition of waves 4. Maximum transmission (S21)

Series Resonator

Series Beatty Resonator (L=λ/4)

4

gL

t

t0 4

p

t

4

p

t0

t


4

p

t

4

p

t

0

2

p

t

2

p

t

4

gL

t

t


4

p

t

4

p

t2

p

t

2

p

t

t

t

3

4

pt

3

4

pt0

4

gL


4

p

t

4

p

t

2

p

t

2

p

t

t

t

3

4

pt

3

4

pt

4

p

t

3

4

pt

Destructive

4

gL


Quarter-wavelength line (L=λ/4) 1. Destructive interference 2. Cancellation of waves 3. Minimum transmission (S21)


t

t0

2

p

t0

t

2

p

t

2

gL


2

p

t

0

pt

pt

t

t

2

p

t

2

gL


2

gL

pt

pt

0

3

2

pt

3

2

pt

t

t 2

p

t

2

p

t


2

gL

pt

pt

3

2

pt

3

2

ptConstructive

t

t 2

p

t

2

p

t 2

p

t

3

2

pt


Half-wavelength line (L=λ/2) 1. Constructive interference 2. Addition of waves 3. Maximum transmission (S21)

Resonator

•Destructive interference

•Minimum transmission Stub/Line is

quarter-wavelength (L=λ/4)

•Constructive interference

•Maximum transmission

Stub/line is half-wavelength

(L=λ/2)




• Summary

Beatty Line Measurement

Now what?

Material Parameter Extraction

∆W H TanD Dk

Dk W

∆W

L

TanD

Sigma H

Ideal Beatty Line

Material Parameter Extraction W=19.5 mils ∆W=0 H=10 mils TanD=0 Dk=4 Sigma=5.7E7

LOSS MODELING APPLICATIONS

Dk

Etch-back/over-plate width extraction

Dielectric thickness extraction

Loss modeling

-Conductor -Dielectric

Dk Dk=variable TanD=0 W=19.5 mils ∆W=0


Dk



Loss modeling


Etch-back/over-plate Width Extraction

Etch-back/over-plate Width Extraction

W=19.5 mils ∆W=variable H=10 mils TanD=0 Dk=4

Dielectric Thickness Extraction

Dielectric Thickness Extraction

W=19.5 mils ∆W=0 H=variable TanD=0 Dk=4


Dk



Loss modeling


-

+

+

-

Loss modeling

Picture credit: Eric Bogatin, "Rule of Thumb #4: Skin depth of copper," 3 January 2014

Conductor Loss

conductorL f

+

-

-

+

Dielectric Loss

dielectricL f

Loss modeling-Dielectric W=19.5 mils ∆W=0 H=10 mils TanD=variable Dk=4

Beatty Line Measurement

Beatty Standard

Adjust

Schematic

• Dk

• ∆W • H • TanD/Sigma

Data Display

• Phase Delay/Z-TDR • Z-TDR (3xW vs. 1xW) • Z-TDR (3xW vs. 1xW) • S21

Observe




• Summary

Beatty Standard

∆W H TanD Dk

Design Verification Workflow 1 Fixture Model

2 Fixture Removal from Measured Data

4 Full-Path Embed Fixture with DUT Model

Simulation Demo CMP-28 ADS Starter Kit

3 DUT Model


96

Fixture Model Reference Plane 1 inch 1 inch

2.92mm 2.92mm

1 inch

Where should I place the reference plane for the DUT?

Fixture Left-Side Fixture Right-Side

0.25 inches

0.25 inches

2.92mm 2.92mm

1 inch 1 inch

What if the 2x Through for the fixture model is too long?

AFR provides a 1inch fixture, but I need a 0.25 inch fixture.


97

MBM

Fixture Left-Side Fixture Right-Side

Fixture Measurement-Based-Model (MBM)

Easy to adjust PCB routing length for flexible fixture length.

AFR vs Measure-Model Compare

Fixture MBM (deconstructed model)

AFR – 2x Through

Fixture left half

Loss vs. Frequency

Inse

rtio

n L

oss

S21

Re

turn

Loss

S11


99

DUT Measure after Fixture De-Embed Schematic for de-embedding the fixture.

Use time domain to verify that the Fixture Model matches the DUT Fixture Connections

Fixture left half

Fixture left half overlaid on DUT+Fixture Measure


100

DUT Model vs. Measure

Transmission Line Model

DUT Measured


101

Embedded Fixture + DUT Simulation vs. Full Path Fixture + DUT Measure

Fixture S-Parameter from AFR-2x Thru and from deconstructed MBM

Model with MBM Fixture Measured Fixture + DUT

Model with AFR Fixture

32 Gb/s, PRBS9

Measure

Simulate


102

Via Example De-constructed T-Line model based on layout.

Required tuning of the via stub lengths to match DUT measure. Stub length is 36mils with via pad.

DUT T-Line MBM DUT Measured

DUT FEM Simulation

Interlayer Via Transition

Top Stub 36 mils

Bottom Stub 36 mils


103

So Why Did I Do This?

Fast “what if” simulations to identify key design parameters before lengthy EM simulations.


104

SIMULATED MEASURED N4951A Pattern Generator

10 Gb/s , PRBS 9

Stripline Stub Resonator Test Structure CILD Line-Type Model with Embedded Fixture

Measurement vs. Simulation in ADS CMP-28 Stripline Resonator

Stub Resonator Example


105

Simulation Conclusion

1. Measurement-Based-Models for DUT topology exploration provide causal, passive S-Parameters and extrapolation beyond measurements.

2. The 2x Fixture Through and the series resonant Beatty Standard for as-fabricated material properties.

Enabling measurement to simulation correlation down to the last ripple!


106

Heidi Barnes [email protected]

Chun-Ting “Tim” Wang Lee, University of Colorado Boulder [email protected]

Thank you Mr. Beatty!


107



and Measurements

Part 3- Using Test Fixtures as Standards for Benchmarking 3D EM Solvers and Measurement to 32 Gb/s Speaker – Alfred Neves, Wild River Technology

Test Fixtures for Benchmarking Simulation to Measurement

13-TU2 Breaking the 32 Gbps Barrier PCB Materials, Simulations, Measurements 109

Stellar Measurement to Simulation – Getting There – tips, things not to do


Everything needs to work together –

• Measurements

• De-embedding Approach

• Fixture Design Architecture

• General Signal Integrity

Test Fixture Gestalt for Simulation-Measurement Correspondence

German word for form or shape. An organized whole that is perceived as more than the sum of its parts


The Reality of Measurements for 32Gbsec

1. The launch from coaxial connector to planar PCB needs good returns loss PAST Fstop!

2. The fixture needs to be characterized and de-embedded from the measurement, or verified as “transparent”.

3. All measurements have noise, de-embedding usually aggravates noise issues.

4. You need an S-parameter work flow. 5. You need standards to validate measurements.

Airlines and Stepped Impedance coaxial standard. 6. Measurement and simulation staff need to meet a

mutual objective.

Measurements must satisfy Simulation-EDA staff’s requirements


• Usable BW less than Fstop

• Poor launch design into platforms, want -5dB min at >Fstop, better than -20dB over Nyquist for base-band NRZ data (ex: 16GHz, for 32Gbpsec)

• Practical fabrication – etch, material, fiber weave and orientation

• S-parameter measurement quality

• Architectural – de-embedding, material extraction, validation structures, often don’t have enough real estate to do what is needed

• Poor Material Identification – may or may not be an issue

Common Test Fixture Use Issues


Designing VLF K+ launch to 50GHz – Comparing an intentional bad launch with tuned launch

Poor launch design

Tuned launch (red), -12dB at 50GHz


Common and Often Overlooked VNA Measurement Issues

• Old noisy VNA technology

• VNA Cables and cable movement, especially during calibration

• VNA is not set up optimally – too many adapters

• Lack of using Standards for both calibration and simulation

• Adapter maintenance – try NOT to clean them with either air or chemicals


Example of old VNA noise issues

Adapter problem

Group Delay Noise –scaled 1st derivative of phase – good metric of phase noise


More S-parameter Tips

• Have S-parameter quality work flow

• >4000 points, harmonic sampling, IF BW <1kHz

• Don’t fix issues (causality especially, minor passivity ok)

• Avoid adapters and cable keepers if possible

• Keep a clean and ordered work space


Important VNA Purchase Criteria • Evaluate Group Delay Noise

• Cal kit selection, standards support

• Evaluate sweep times (we use >4000points typically) – I want FAST measurement time

• S-parameter software required – PLTS, Matlab, ADS, Simbeor, Ansoft Designer, Hyperlynx

• Make vendors prove S-parameter quality claims


• De-embedding is one of the biggest challenges, lots of choices, most of them wrong and the rest are compromises

• All de-embedding schemes leave you with less than you started with (bandwidth, S-parameter quality, etc.,_

What is the Difference between Calibration and De-embedding?

De-embedding is a VERY big challenge


De-Embedding – What you do after making the Measurement

Port 1 Port 2

ref 1 ref 2

VNA NIST traceable calibration, with full-path measurement

What 2 things does VNA calibration accomplish?


Clearly Establish DUT Definition – Full-Path or De-Embedded?

Port 1 Port 2 ref 1 ref 2

Full-Path

De-embedded

VNA NIST traceable calibration + De-embedding to move reference plane to DUT


T-Matrix De-Embed

122

T1-1 T-Device T1-1

For T-matrix de-embedding, S-- T matrix, then inverted and multiplied, all done in VNA, PLTS, ADS

From Full Path Measurement

Left hand side of fixture

Left hand side of fixture

13-TU2 Breaking the 32 Gbps Barrier PCB Materials, Simulations, Measurements

Symmetrical De-Embedding Approach w= 4.75 mils L=250 mil

w= 4.75 mils L=250 mil

w= 15 mils L=1.0 in

w= 4.75 mils L=2 in

w=4.75 mils L=2 in

2.92mm 2.92mm

w= 4.75 mils L=2 in

w=4.75 mils L=2 in

2.92mm 2.92mm

w= 4.75 mils L=2 in

2.92mm 2.92mm

w=4.75 mils L=4 in

2X THRU

1X THRU+DUT+1X

THRU

1X+1X THRU sans DUT

DUT

DUT REMOVED


De-Embed Approaches De-Embed Approach Pros Cons

TRL – really calibration approach with 1X Open reference plane location

Has ring of mystic power. Awesome directivity with coaxial standards

Lots of measurements, on board standards hard, wreaks havoc on causality, needs SOLR compliment which is a tough firmware VNA issue depending on model

AFR – Automatic Fixture Removal, Symmetrical

Calibration Approaches

Simple and straightforward, gets you to the 2 de-embed files fast. Low effort. Either 2X THRU or 1X SHORT/OPEN

Must have good s-parameter quality, lose a bit of insight into problem

Measure-Modeled Very accurate, can move reference plane, can do what-ifs and advanced analysis, inherently causal/passive

Requires significant effort to create 2 S-parameters, requires T-Line models and physical topology


Measure-Based Model 2X THRU De-Constructed

125

2.92mm 2.92mm 2X THRU


Modeling ½ of 2X THRU – Bifurcated S-parameter, Left side

126

w= 4.75 mils L=2 in

w=4.75 mils L=2 in

2.92mm 2.92mm

w= 4.75 mils L=2 in


Symmetrical Calibration, AFR example

w= 4.75 mils L=2 in

w=4.75 mils L=2 in

2.92mm 2.92mm

w= 4.75 mils L=2 in

2.92mm 2.92mm S2X THRU

Measure 2X THRU

AFR generates 2 S-parameters, one for left, the other right hand side

w= 4.75 mils L=4 in

S1X THRU Left S1X THRU Right


TRL Calibration Platform – Early SMA Design, circa

2008

THRU

LINE1

LINE2

LINE3

OPEN MATCHED*

SHORT **

Test Structures –Beatty,

Resonator


2 4 6 8 10 12 14 16 180 20

-60

-40

-20

0

-80

20

freq, GHz

dB

(S(1

,1))

dB

(S(2

,1))

TRL calibrated THRU

TRL De-Embedding Issues for S.I.

• Difficult to design – lengths need to be right, layout is challenging

• Results impacted by launch, weave and material homogeneity issues

• Many measurements required

• THRU path transmissions require Unknown THRU cal in addition to TRL, 2 tier calibration

• Some VNA’s firmware does not support 2 tier calibrations TRL calibration works well for single

line, RF Microwave apps


S11 anomaly – low reflective structures wreak havoc

on S-parameter, results highly non-causal

25dB S11 TRL anomaly occurs from using multiple line standards and only one used for match. TRL algorithm is not optimized for non-homogeneity between standards


Some Test Fixture Voodoo • Functional

– Measurement - Test – Material/loss modeling – Insight into a problem – Validation

• Broaden Solution Space – Small, quick turn platfrom – Design complimentary Calibration Card


March of Channel Modeling Progress- Mini CMP

• Launch design • Material identification • Low Cost & Quick • Systematic • Fab and vendor qual 13-TU2 Breaking the 32 Gbps Barrier PCB Materials, Simulations, Measurements 132

Backplane 10GBase KR Ref plane possibles – A,B,

and C

Port 1

Port 2 A

B

C


The Testing Co-Fixture • Material Identification

• THRU • Beatty • Resonator

• De-embedding • Measure-based • 1X AFR • 2X AFR

• De-embed Validation • One test structure matches

Daughter-Card Fixture • Fixtures same panelization


Recall Measure-Based De-Embed Using Test Co-Test Fixture

2.92mm 2.92mm 2X THRU


136

Matching Model to Measurement- Frequency Domain


137

Time Domain Correspondence


Compare De-embed Model to 1X THRU to Ground - optional

138 13-TU2 Breaking the 32 Gbps Barrier PCB Materials, Simulations, Measurements

Conclusions for 32Gbsec Design • A Lot of Things Can Go Wrong

– Test Fixture Architecture

– Getting to the “DUT” with De-embedding

– Measurement approach and quality

– Using wrong De-embedding scheme

• Test Structures Help with 32Gbspec – Fabrication

– Simulation and EDA Tool Benchmarking

– Measurement Standards

Yikes! 32 Gpsec design is very risky – use test fixtures!


Thank You! – Visit our Booth #751 Advanced Serial Link Testing

Al Neves Chief Technologist Wild River Technology 503 679 2429 [email protected]

XTLK-32, Industry first Crosstalk Channel Modeling Platform, ADS, Simbeor EDA Kit included

ISI-32, Intersymbol Interference From 10-32Gbsec, EDA Kit, S-parameters included


breaking the 32 gb/s barrier: pcb materials, simulations

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