BSIM6: Symmetric Bulk MOSFET ModelY. S. Chauhan, M. A. Karim, S. Venugopalan, S. Khandelwal,P. Thakur, N. Paydavosi, A. B. Sachid, A. Niknejad and C. HuDepartment of Electrical Engineering and Computer Science

University of California, Berkeley, CA-94720, yogesh@eecs.berkeley.edu

ABSTRACT

BSIM6 Model is the next generation Bulk RF MOSFETModel. Model uses charge based core with all physical mod-els adapted from BSIM4 model. Model fulfills all qualitytests e.g. Gummel symmetry and AC symmetry test andshows correct slopes for harmonic balance simulation. Modelhas been tested in DC, small signal, transient and RF simu-lation and shows excellent convergence in circuit simulation.Model is under standardization at Compact Model Council.

Keywords: BSIM6, BSIM4, Symmetry, Analog, RF, MOS-FET, Compact Model

1 INTRODUCTION

BSIM4 was selected as industry standard compact MOS-FET model in 2000 [1] and since then, its been used by majorsemiconductor companies and design houses. The beauty ofBSIM4 lies in the flexibility to fit data from different tech-nologies starting from 350nm to 28nm in production today[2]. The compact model consists of two main components- core model and real device models. The core is the ideallong channel model, which is threshold voltage based in caseof BSIM4 [3]–[5]. The real device models are the modelsused to capture the effects in real devices e.g. short channeleffect, channel length modulation, velocity saturation effect,quantum mechanical effect etc. The real device models ofBSIM4 are physically derived expressions for different ef-fects and have excellently captured the silicon data and pro-vided accuracy in parameter extraction. Although BSIM4 isbeing used for all types of designs, Analog and RF designershave complained on symmetry issue in the model. To ad-dress this issue, BSIM group started BSIM6 development inlate 2010. BSIM6 inherits all real device effects from BSIM4but guarantees symmetry around VDS=0 [6]–[10].

2 BSIM6 Model

BSIM6 has charge based core, which is derived from Pois-son’s solution for long channel MOSFET [11]–[13]. The rea-son for choosing charge based core is due to its physical na-ture as well as accuracy along with computational efficiency.Using Gauss’ law, we have

VG−VFB−ΨS =−Qsi

Cox=−Qi +Qb

Cox(1)

where VG is the is the applied gate voltage, VFB is the flatband voltage, ΨS is the surface potential. BSIM6 is the bodyreferenced model, where gate, drain and source node volt-ages are with respect to applied body voltage. Qi and Qbare the inversion and bulk charge densities respectively. Foruniformly doped MOSFET with gradual channel approxima-tion, we have [11],

Qsi

ΓCox√

Vt=∓

√e−

ΨSVt +

ΨS

Vt−1+ e−

2ΦF+VchVt

(e

ΨSVt − ΨS

Vt−1)

(2)The -ve sign is taken when ΨS is positive and vice-versa. Thebulk charge is given by

Qb

ΓCox√

Vt=∓

√e−

ΨSVt +

ΨS

Vt−1 (3)

and using (1) and (3), we have

VG−VFB−ΨS =−Qi

Cox±Γ

√Vt

(e−

ΨSVt +

ΨS

Vt−1)

(4)

where Vt is the thermal voltage and Γ is the body effectcoefficient. Defining pinch-off potential as ΨS = ΨP, wheninversion charge density is zero, above equation can be writ-ten as,

VG−VFB−ΨP = sign(ΨP)Γ

√Vt

(e−

ΨPVt +ΨP−1

)(5)

Although above equation is an implicit equation for ΨP, theanalytical solution does exist for it (thanks to Francois Krum-menacher) [14]. For ΨS greater than few Vt , from (2) and (3),we have

− Qi

ΓCox√

Vt=

√ΨS

Vt+ e

ΨS−2ΦF−VchVt −

√ΨS

Vt(6)

For charge based models, the inversion charge linearizationis defined as [13],

− Qi

Cox= nq(ΨP−ΨS) (7)

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0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0- 0 . 5

0 . 0

0 . 5

1 . 0

1 . 5

Re

lative

Error

(%) in

q i

v g - v f b

v d = 0 v d = 1 0 v d = 2 0

Figure 1: Relative error in the inversion charge density as a func-tion of gate bias for different drain biases. Accuracy is better than1% for all bias conditions.

where nq is the slope factor. Using (7) in (6), we can get [13]

2qi+ln(qi)+ln[

4nq

γ

(nq

γqi +

√ψp−2qi

)]=ψp−2φ f −vch

(8)where qi =

−Qi2nqCoxVt

is the normalized inversion charge den-

sity and ψp =ΨPVt

is the normalized pinch-off potential.Eq. (8) is the core charge density equation, whose ac-

curacy greatly affects the accuracy in final charge and cur-rent expressions. In earlier approaches [12], [13], both qiterms inside second log term were neglected for evaluationof charge density at source and drain end. We found that us-ing those approaches, the error could be in the order 2-6%.For BSIM6, eq. (8) has been analytically solved without ig-noring first qi term[6]–[9]. Fig. 1 shows the relative errorin qi vs. normalized gate bias using BSIM6 compared to nu-merical solution, where it can be seen that accuracy is betterthan 1% for entire bias range.

The drain to source current is obtained using well knowndrift-diffusion model as follows,

ids =(q2

s +qs)− (q2d +qd)

12

[1+√

1+(λc(qs−qd))2] (9)

where qs and qd are the normalized charge densities atsource and drain end respectively. The denominator termin above equation accounts for velocity saturation for shortchannel transistors; where λc =

2µe f f VtV SAT ·Le f f

[15]. Note, thedrain charge density qd is effective charge density at drain,which is obtained using effective drain voltage accountingfor Vd to Vdsat transition [16]. Fig. 2 show comparison ofnormalized current from BSIM6 model with numerical re-sults [11], where error is in the order of 1%.

0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 005 0 0

1 0 0 01 5 0 02 0 0 02 5 0 03 0 0 0

Norm

alized

curre

nt i ds

v g - v f b

B S I M 6 M o d e l N u m e r i c a l a p p r o a c h

1 E - 81 E - 61 E - 40 . 0 111 0 01 0 0 0 0

(a) Normalized ids vs. vg− v f b using (9)

0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0- 1

0

1

2

3

Relat

ive Er

ror (%

) in i ds

v g - v f b

(b) Relative error in normalized current vs. vg− v f b.

Figure 2: Comparison of BSIM6 Model with numerical surfacepotential approach. It can be seen that model provides excellentaccuracy compared to numerical surface potential approach.

3 Results and Discussion

During BSIM6 development, goal has been to keep inmind the smooth transition of BSIM4 users but providingsymmetry around Vds = 0. Most of the real device effectmodels are similar to BSIM4 model. Even if some of the realdevice models are not same as BSIM4, we have ensured thatthe parameter names are the same for easier extraction basedon BSIM4 experience. The real device effect models wereupdated to ensure symmetry during DC and AC simulations.

Fig. 3, 4 show the famous Gummel symmetry test [17],[18] results for BSIM6 model. The drain current and all ofits derivatives are continuous up to any order depending onthe value of DELTA parameter, whose maximum value hasbeen fixed to 0.5 to ensure that third derivative is always con-

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- 0 . 3 - 0 . 2 - 0 . 1 0 . 0 0 . 1 0 . 2 0 . 3

I DS

V X

dI DS/dV

X

Figure 3: Gummel Symmetry Test: IDS and dIDSdVX

vs. VX = VD,where drain and source biases are swept in opposite direction.

tinuous. The charges associated with drain and source nodesare obtained using Ward-Dutton charge partitioning scheme[19]. Fig. 5, 6 and 7 show the long channel capacitance plots,where it is shown that model behaves physically across biasrange. From fig. 5 and 6, it is evident that transcapacitancesCgs and Cgd overlap each other for Vds = 0 and transcapaci-tances Csg and Cdg also overlap each other for Vds = 0, whichis an important condition for good compact model. Fig. 7show the capacitances’ behavior with drain bias, where it isshown Cgs = Cgd and Csg = Cdg at Vds = 0. The axis valuesare not shown for confidentiality reasons.

Another important quality test for compact MOSFET modelis AC symmetry test proposed by Colin McAndrew [20]. Itis must for a compact model to qualify this test for correctharmonics behavior. In fact, we had to update the junctioncapacitance model taken from BSIM4 to satisfy this test.Fig. 8 - 10 show the capacitance symmetry plots and theirderivatives for BSIM6 model, which clearly demonstrate thatmodel satisfies AC symmetry test. Fig. 11 and 12 show themodel validation on measured characteristics from mediumtechnology node. Model matches well with measured char-acteristics which demonstrate that BSIM6 has similar flexi-bility as BSIM4 for data fitting.

BSIM6 is under standardization at Compact Model Coun-cil [1]. Model has been rigorously tested and satisfies allquality tests for compact MOSFET model [20].

4 ACKNOWLEDGEMENT

We would like thank Compact Model Council and itsmembers companies for continuous feedback and discussionduring BSIM6 development. We would also like to thankChristian Enz, Anuarg Mangla and Maria-Anna Chalkiadakifor feedback on BSIM6 model.

- 0 . 3 - 0 . 2 - 0 . 1 0 . 0 0 . 1 0 . 2 0 . 3

d2 I DS/dV

X2

V X

d3 I DS/dV

X3

Figure 4: Gummel Symmetry Test: d2IDSdV 2

Xand d3IDS

dV 3X

vs. VX = VD,where drain and source biases are swept in opposite direction.

- 3 - 2 - 1 0 1 2 30 . 0

0 . 2

0 . 4

0 . 6

0 . 8

1 . 0

V D S = 0

Norm

alized

Capa

citanc

es

V G

C g s C g d C g g C g b C b g

Figure 5: Normalized capacitances from BSIM6 model. Quantummechanical and poly depletion effects have been added in the model(not shown here).

REFERENCES

[1] Compact Model Council - http://www.geia.org/CMC-Introduction

[2] Chenming Hu and Christian Enz, ”Free StandardSPICE Model Supported by University Partners”, GSAforum Article, March 2012.

[3] BSIM Models: http://www-device.eecs.berkeley.edu/bsim/

[4] Chenming Hu, ”Modern Semiconductor Devices for In-tegrated Circuits”, Prentice Hall, 2009.

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- 3 - 2 - 1 0 1 2 30 . 0

0 . 1

0 . 2

0 . 3

0 . 4

0 . 5

No

rmaliz

ed C gs

and C

gd

V G

C s g C d g

V D S = 0

Figure 6: Transcapacitances Csg and Cdg vs VG for Vds = 0. Bothcapacitances should be same at Vds = 0 for good compact model.

0 . 0 0 . 5 1 . 0 1 . 5 2 . 00 . 00 . 10 . 20 . 30 . 40 . 50 . 60 . 7

Norm

alized

Capa

citanc

es

V d s

C g s C g d C s g C d g

Figure 7: Transcapacitances associated with source and drainnodes with drain bias. Cgs and Cgd should be exactly same at Vds = 0for good compact model. Same is true for Csg and Cdg.

Sachid, A. Niknejad, C. Hu, W. wu, K. Dandu, K.Green, G. Coram, S. Cherepko, J. Wang, S. Sirohi, J.Watts, M.-A. Chalkiadakim A. Mangla, A. Bazigos, F.Krummenacher, W. Grabinski, C. Enz, BSIM6: Sym-metric Bulk MOSFET Model, The Nano-Terra Work-shop on the next generation MOSFET Compact Mod-els, Lausanne, Switzerland, Dec. 2011.

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[8] Y. S. Chauhan, M. A. Karim, S. Venugopalan, A.Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu,BSIM Models: From Multi-Gate to the Symmetric

- 0 . 3 - 0 . 2 - 0 . 1 0 . 0 0 . 1 0 . 2 0 . 3

δ cg

V X ( V )

∂δcg

/∂VX

Figure 8: AC Symmetry Test: δcg =ig−ig+ =

Cgs−CgdCgs+Cgd

and its deriva-tive vs. VX =VD, where drain and source biases are swept in oppo-site direction.

- 0 . 3 - 0 . 2 - 0 . 1 0 . 0 0 . 1 0 . 2 0 . 3

δ cb

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Figure 9: AC Symmetry Test: δcb = ib−ib+ = Cbs−Cbd

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[10] S. Khandelwal, Y. S. Chauhan, M. A. Karim, S. Venu-gopalan, A. Sachid, A. Niknejad and C. Hu, Analy-sis and Modeling of Vertical Non-uniform Doping inBulk MOSFETs for Circuit Simulations, IEEE Interna-

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- 0 . 3 - 0 . 2 - 0 . 1 0 . 0 0 . 1 0 . 2 0 . 3

δ csd

V X ( V )

∂δcsd

/∂VX

Figure 10: AC Symmetry Test: δcsd =(is−+id−)+(is+−id+)(is−−id−)+(is++id+)

=Css−CddCss+Cdd

and its derivative vs. VX = VD, where drain and source bi-ases are swept in opposite direction.

0 . 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4

I DS(A)

V G S ( V )

V D S = 5 0 m V

(a)

0 . 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4

I DS(A)

V G S ( V )

V D S = 5 0 m V

(b)

Figure 11: Model validation on measured transfer characteristics:(a) IDS vs. VGS for VDS = 50mV . (b) gm vs. VGS for VDS = 50mV .

0 . 0 0 . 3 0 . 6 0 . 9 1 . 2

I DS(A)

V D S ( V )

M e a s u r e d B S I M 6 M o d e l

(a)

0 . 0 0 . 3 0 . 6 0 . 9 1 . 2

g ds(A/

V)

V D S ( V )

M e a s u r e d B S I M 6 M o d e l

(b)

Figure 12: Model validation on measured output characteristics:(a) IDS vs. VDS and (b) gds vs. VDS for different gate voltages.

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