bu-65549 mil-std-1553 bc/rt/mt pci interface cardpccorot15.obspm.fr/corot-etc/files/65549.pdf · 24...
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BU-65549
DESCRIPTION
The BU-65549 provides full, intelli-gent interfacing between a PCI busand one or two independent dualredundant MIL-STD-1553B DataBuses. Software controls the oper-ation of each channel as either a1553 Bus Controller (BC), RemoteTerminal (RT), or Bus Monitor (MT).
The board features DDC's Mini-ACE Plus hybrids. As such, eachchannel includes dual transceiversand encoders/decoders, complete1553B protocol, 64K words ofshared RAM and memory manage-ment logic for all three modes.
Background Mode Operation pre-vents inadvertent access to thecard during power-on self-test.
On-board Interrupt Mask andInterrupt Status Registers supportflexible operation for both interruptand polling applications.
The memory management schemefor RT mode provides an option forseparation of broadcast data plus acircular buffer option for individualRT subaddresses to offload the PChost CPU.
Additional features include a wrap-around Built-In-Test, register pro-grammable interrupt level, softwareprogrammable RT address selec-tion and a free “C” software subrou-tine library. Its full compliance withMIL-STD-1553A and B makes it anexcellent choice for real-time simu-lation, test, and system integrationapplications.
MIL-STD-1553 BC/RT/MT PCI INTERFACE CARD
1553BUS
PCI
to
Mini-ACE
Interface
AD[31:0]
C/BE#[3:0]
PARITY
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
CLOCK
RST#
PERR#
SERR#
ErrorReporting
System
InterfaceControl
Address/DataandCommand BU-61688
Mini-ACE Plus1553
BC/RT/MT
BU-61688Mini-ACE Plus
1553
BC/RT/MT
® IBM is a registered trademark of International Business Machines Corporation© 1999, 1998 Data Device Corporation
FIGURE 1. BU-65549 BLOCK DIAGRAM
FEATURES
• PCI Interface Card
• 1553B Notice 2 Dual Redundant BC/RT/MT (STANAG 3838 Compliant)
• Single or Dual Channel
• 64K x 16 Shared RAM per Channel
• Free “C” Runtime Libraries for Win95and WinNT
• Free Win95 Graphical User Interface
• Programmable BC Gap Times
• BC Frame Auto-Repeat
• Flexible RT Data Buffering
• Monitor Command Filtering
• Simultaneous RT/Monitor
• Flexible Interrupt Generation
2
FUNCTIONAL OVERVIEW
GENERAL
The BU-65549 provides a user-friendly interface between theserial MIL-STD-1553B Notice 2 Bus and a PCI bus. The oper-ating modes of the BU-65549 are controlled through the use of24 on-board registers. 1553 message traffic is stored andretrieved using the shared, memory mapped, on-board 64Kwords of RAM. The various registers control and operate theBU-65549. These include the Configuration Registers,Start/Reset Register, Time Tag Register, Interrupt MaskRegister, Interrupt Status Register, Subaddress Control WordRegister, Memory Base Address Register, and Control/RTAddress Register. The Configuration Registers define the oper-ating mode and memory management features. The Start/ResetRegister provides various reset and BC/MT start functions. TheInterrupt Mask Register enables desired interrupts, with theinterrupt priority level being register controlled. The cause ofinterrupts may be determined by a single read operation, bymeans of the Interrupt Status Register. The Control/RT AddressRegister is used to program the RT address and miscellaneousfunctions. The Time Tag Register features programmable reso-lution and is used to time tag messages in BC or RT modes. TheMemory Base Address Register supports a software program-mable base memory address and controls the background modeoperation.
The BU-65549's 64K x 16 of static RAM per channel is sharedby the PC host and the 1553 Bus with memory arbitration han-dled automatically by the BU-65549.
In addition to storing the 1553 message data, the RAM imple-ments the Stacks and Look-Up Tables required for the differentmodes of operation. For RT mode, there is a programmableoption to separate broadcast message data from non-broadcastdata. This provides compliance to MIL-STD-1553B Notice 2. Inaddition, for RT mode, there is the choice of storing either a sin-gle message, a double buffer data structure or a circular bufferdata structure for each transmit or receive subaddress. The sizeof the circular buffer is programmable up to 8192 words, on aTx/Rx/Bcst-subaddress basis. A global double buffering mech-anism is available to prevent partially updated information frombeing transferred to or from the 1553 Bus.
The BU-65549 supports programmable command illegalizationfor RT mode. This allows individual Command Words to be ille-galized as a function of bit, subaddress, and wordcount/mode code. Since the illegalization scheme is RAMbased, it is inherently self-testable.
R/T
TABLE 1 notes:1. Under software control, minimum intermessage gap time may be lengthenedto (65,535 ms minus message time), in increments of 1 µs.2. Software programmable (4 options). Includes RT-to-RT Timeout (Mid-Parity ofTransmit Command to Mid-Sync of Transmitting RT Status).
in(mm)
oz(g)
°C°C
PHYSICAL CHARACTERISTICSSize
Weight
5565
0-20
THERMALOperating TemperatureStorage Temperature
µsecµsec
µsec
µsecµsecµsecµsecµsec
7
19.523.551.5129
2.5
9.5
18.522.550.5128668
4
17.521.549.5127
WWWW
WWWW
V
AAAA
AAAA
5.5
0.50.650.801.10
0.81.101.402.00
5.0
0.300.430.550.80
0.480.730.981.48
4.75
POWER SUPPLY REQUIREMENTSVoltages/Tolerances! + 5 V
Current Drain!BU-65549M1
Idle25% Transmitter Duty Cycle50% Transmitter Duty Cycle100% Transmitter Duty Cycle
!BU-65549M2Idle25% Transmitter Duty Cycle50% Transmitter Duty Cycle100% Transmitter Duty Cycle
VP-P
VP-P
mVP-P,diffmV
nsec
9
27
10
90
300
7
21
6
18
-90
100
TRANSMITTERDifferential Output Voltage! Direct Coupled Across 35 ohms,
Measured on Bus! Transformer Coupled,
Measured on StubOutput Noise, Differential
(Direct Coupled)Output Offset Voltage,
Direct Coupled Across 35 ohmsRise/Fall Time
VP-P
VPEAK
0.860
10
0.2RECEIVER
Threshold Voltage, TransformerCoupled, Measured on Stub
Common-Mode Voltage
V6.0-0.3ABSOLUTE MAXIMUM RATINGS
+5 V Supply Voltage
TABLE 1. BUS-65549 SPECIFICATIONS
UNITSMAXTYPMINPARAMETER
1553 MESSAGE TIMINGRT Response TimeCompletion of CPU Write
(BC Start-to Start of FIRST BC Message)
BC Intermessage Gap (See Note 1)
BC/RT/MT Response Timeout (See Note 2)! 18.5 nominal! 22.5 nominal! 50.5 nominal! 128.0 nominal
Transmitter Watchdog Timeout
2.803.293.784.75
4.405.406.408.40
1.501.802.102.70
2.403.003.604.80
POWER DISSIPATIONBU-65549M1! Idle! 25% Duty Cycle! 50% Transmitter Duty Cycle!100% Transmitter Duty Cycle
BU-65549M2! Idle! 25% Duty Cycle! 50% Transmitter Duty Cycle! 100% Transmitter Duty Cycle
6.80 x 4.50 (172.7 x 114.3)
6.0 (170)
A Descriptor Stack is maintained in BC, RT and MT modes. Thisrecords the status of each message, the time the message wastransmitted or received, and contains either the received 1553command and Data Block Pointer (in RT or MT mode) or theactual address of the 1553 message block (in BC mode). In RTmode, a Lookup Table is provided to define the addresses of thedata blocks to to be used when receiving or transmitting mes-sages for the individual subaddresses.
The BU-65549 RT mode is multiprotocol, supporting MIL-STD-1553A, MIL-STD-1553B Notice 2, STANAG 3838, and the McAirA3818, A5232, and A5690 protocols.
The BU-65549 implements three monitor modes: a word moni-tor, a selective message monitor, and a combined RT/selectivemessage monitor.
MEMORY MANAGEMENT
The BU-65549 incorporates complete memory management andprocessor interface logic. The software interface to the hostprocessor is implemented by means of 24 on board registersand 64K words of RAM. For all three modes, a stack area ofRAM is maintained. In BC mode, the stack allows for the sched-uling of multi-message frames. For all three modes, the stackprovides a real-time chronology of all messages processed. Inaddition to the stack processing, the memory management logicperforms storage, retrieval, and manipulation functions involvingpointer and message data structures for all three modes.
The BU-65549 provides a number of programmable options forRT mode memory management. In compliance with MIL-STD-1553B Notice 2, received data from broadcast messages may beoptionally separated from non-broadcast received data. Foreach transmit, receive or broadcast subaddress, either a single-message data block, a subaddress-specific double-bufferedconfiguration or a variable-sized (128 to 8192 words) circularbuffer may be allocated for data storage. In addition to helpingensure data consistency, the circular buffer feature provides ameans of greatly reducing host processor overhead for bulk datatransfer applications. End-of-message interrupts may beenabled either globally, following error messages, on aTx/Rx/Bcst-subaddress basis, or when any particularTx/Rx/Bcst-subaddress circular buffer reaches its lower bound-ary.
INTERRUPTS
Individual events are enabled by the Interrupt Mask Register.The host processor may easily determine the cause of the inter-rupt by reading the Interrupt Status Register. The Interrupt
Status Register provides the current state of the interrupt condi-tions. The Interrupt Status Register may be updated in twoways. In the standard interrupt handling mode, a particular bit inthe Interrupt Status Register will be updated only if the conditionexists and the corresponding bit in the Interrupt Mask Register isenabled. In the enhanced interrupt handling mode, a particularbit in the Interrupt Status Register will be updated if the conditionexists regardless of the contents of the corresponding InterruptMask Register bit. In any case, the respective Interrupt MaskRegister bit enables an interrupt for a particular condition.
The BU-65549 provides maskable interrupts and 15-bit InterruptStatus Register for end of message, end of BC message list,erroneous messages, Status Set (BC mode), Time Tag RegisterRollover, RT Address Parity Error conditions, BC retry, datastack rollover, command stack rollover, transmitter watchdogtimeout, or RAM parity error. The Interrupt Status Registerallows the host processor to determine the cause of all interruptsby means of a single read operation.
INTERNAL COMMAND ILLEGALIZATION
The BU-65549 offers the option to illegalize commands in RTmode. The illegalization architecture allows for any subset of the4096 possible combinations of broadcast/own address, bit,subaddress, and word count/mode code to be illegalized. TheBU-65549 illegalization scheme is under software control of thehost processor. As a result, it is inherently self-testable.
INTERNAL TIME TAG
The BU-65549 includes an internal read/writable Time TagRegister. This register is a CPU read/writable 16-bit counter witha programmable resolution of either 2, 4, 8, 16, 32, or 64 µs perLSB. For each message processed, the value of the Time Tagregister is loaded into the second location of the respectivedescriptor stack entry (“TIME TAG WORD”) for both BC and RTmodes.
Additional options are provided to clear the Time Tag Registerfollowing a Synchronize (without data) mode command or loadthe Time Tag Register following a Synchronize (with data) modecommand. Another option enables an interrupt request and a bitin the Interrupt Status Register to be set when the Time TagRegister rolls over from FFFF to 0000(hex). Assuming the TimeTag Register is not loaded or reset, this will occur at approxi-mately 4-second time intervals, for 64 µs/LSB resolution, downto 131 ms intervals, for 2 µs/LSB resolution. Another program-mable option for RT mode is for the Service Request StatusWord bit to be automatically cleared following the BU-65549'sresponse to a Transmit Vector Word mode command.
R/T
3
ADDRESSING, INTERNAL REGISTERS, MEMORYMANAGEMENT, AND INTERRUPTS
ADDRESSING THE BU-65549
The BU-65549 makes use of two memory mapped I/O spaces;one for the ACE's registers and the other for the ACE's sharedmemory. The memory base addresses of these I/O spaces arespecified by the base address registers within the BU-65549'sPCI Device Configuration Header. These registers are typicallyprogrammed by the PCI bus enumerator which is a part of theoperating system running on the host computer.
The memory base address of the ACE's registers is specified byBase Address Register 0 in the BU-65549's PCI DeviceConfiguration Header. The single channel BU-65549M1 imple-ments a Base Address 0 register which specifies a memorymapped register space of 128 bytes while the dual channel BU-65549M2 implements a register space of 256 bytes (128 bytesper channel). TABLE 2 illustrates the address map for the BU-65549's memory mapped register space.
MEMORY ADDRESS MAP
The memory base address of the ACEs’ shared RAM is speci-fied by Base Address Register 1 in the BU-65549's PCI DeviceConfiguration Header. The single channel BU-65549M1 imple-ments a shared RAM size of 128K bytes (64K words) while thedual channel BU-65549M2 implements a shared RAM size of256K bytes (64K words per channel). TABLE 3 illustrates theaddress map for the BU-65549's memory mapped shared RAMspace.
Read or writes of the ACE's shared RAM may be either word(16-bit) or double word (32-bit) transfers. Byte (8-bit) write trans-fers are not permitted. Byte (8-bit) read transfers will return thesame data as a word (16-bit) read.
REGISTER MAP
The software interface of the BU-65549 to the host processorconsists of 17 internal operational registers for normal operation,an additional 8 test registers, plus 64Kx16 of shared memory perchannel. Both the registers and the shared memory reside in theISA memory space.
Each ACE register is 16 bits. Registers must be accessed usingword (16-bit) transfers. ACE Registers cannot be accessedusing double-word (32-bit) transfers. Byte (8-bit) write transfersare not permitted. Byte (8-bit) read transfers will return the samedata as word reads.
There is an additional register, at PCI bus address offset 0800,used to designate the card configuration (ACE memory size) andwhich ACE channel(s) have issued interrupt requests.
4
00000000
ACEOFFSET
PCIBUS
Interrupt Mask Register (RD/WR)
DESCRIPTION
00010002 Configuration Register #1 (RD/WR)
00020004 Configuration Register #2 (RD/WR)
00030006 Start/Reset Register (WR)
00030006 BC/RT Command Stack Pointer Register (RD)
000F001E
000E001C
000D001A
000C0018
000B0016
000A0014
00090012
00080010
0007000E
0006000C
0005000A
00040008
RT BIT Word Register (RD)
RT Status Word Register (RD)
BC Frame Time*/RT Last Command/MTTrigger Word* Register (RD/WR)
BC Frame Time Remaining to Next MessageRegister (RD)*
BC Frame Time Remaining Register (RD)*
Data Stack Address Register (RD/WR)
Configuration Register #5 (RD/WR)
Configuration Register #4 (RD/WR)
Configuration Register #3 (RD/WR)
Interrupt Status Register (RD)
Time Tag Register (RD/WR)
BC Control Word/RT Subaddress ControlWord Register (RD/WR)
00000080 Interrupt Mask Register (RD/WR)00010082 Configuration Register #1 (RD/WR)
00020084 Configuration Register #2 (RD/WR)
00030086 Start/Reset Register (WR)
00030086 BC/RT Command Stack Pointer Register (RD)
00040088BC Control Word/RT Subaddress ControlWord Register (RD/WR)
::
::
000E009C RT Status Word Register (RD)
-0800
000F009E RT BIT Word Register (RD)
Configuration / Master Interrupt Register
Notes:1. PCI addresses are specified as the ‘BYTE’ offset within the BU-65549
register Space
TABLE 2. REGISTER ADDRESS MAP
ADDRESS
CH
AN
NE
L 2
CH
AN
NE
L 1
& 2
CH
AN
NE
L 1
ACE memory transfers may be either 32-bit or 16-bit. Writetransfers may be in bursts of up to 32 words.
Definition of the address mapping and accessibility for the BU-65549's 17 nontest ACE registers, and the ACE test registers, isas follows:
Interrupt Mask Register: Used to enable and disable interruptrequests for various conditions.
Configuration Registers #1 and #2: Used to select the BU-65549's mode of operation, and for software control of RT StatusWord bits, Active Memory Area, BC Stop-on-Error, RT MemoryManagement mode selection, and control of the Time Tag oper-ation.
Start/Reset Register: Used for “command” type functions, suchas software reset, BC/MT Start, Interrupt Reset, Time TagReset, and Time Tag Register Test. The Start/Reset Registerincludes provisions for stopping the BC in its auto-repeat mode,either at the end of the current message or at the end of the cur-rent BC frame.
BC/RT Command Stack Pointer Register: Allows the hostCPU to determine the pointer location for the current or mostrecent message when the BU-65549 is in BC or RT modes.
BC Control Word/RT Subaddress Control Word Register: InBC mode, allows host access to the current or most recent BCControl Word. The BC Control Word contains bits that select theactive bus and message format, enable off-line self-test, mask-ing of Status Word bits, enable retries and interrupts, and spec-ify MIL-STD-1553A or -1553B error handling. In RT mode, thisregister allows host access to the current or most recentSubaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enableinterrupts for the current message.
Time Tag Register: Maintains the value of a real-time clock.The resolution of this register is programmable from among 2, 4,8, 16, 32, and 64 µs/LSB. Start-of-Message (SOM) and End-of-Message (EOM) sequences in BC, RT, and Message Monitormodes cause a write of the current value of the Time TagRegister to the stack area of RAM.
Interrupt Status Register: Mirrors the Interrupt Mask Registerand contains a Master Interrupt bit. It allows the host processorto determine the cause of an interrupt request by means of a sin-gle read access.
Configuration Registers #3, #4, and #5: Used to enable manyof the BU-65549's advanced features. These include all of theEnhanced mode features. For all three modes (BC, RT and MT),use of the Enhanced Mode also enables the various read-onlybits in Configuration Register #1.
For BC mode, the Enhanced mode features include the expand-ed BC Control Word and BC Block Status Word, additional Stop-On-Error and Stop-On-Status Set functions, frame auto-repeat,programmable intermessage gap times, automatic retries,expanded Status Word Masking, and the capability to generateinterrupts following the completion of any selected message.
For RT mode, the Enhanced mode features include the expand-ed RT Block Status Word, the combined RT/Selective MessageMonitor mode, internal wrapping of the internal signal tothe RT Status Word bit, the double buffering scheme forindividual receive (broadcast) subaddresses, and the alternate(fully software programmable) RT Status Word. For MT mode,use of Enhanced mode enables use of the Selective MessageMonitor, the combined RT/Selective Monitor mode, and themonitor triggering capability.
MT Data Stack Address Register: Used to point to the currentaddress location in shared RAM used for storing message words(second Command Words, Data Words, RT Status Words) in theSelective Word Monitor mode.
Frame Time Remaining Register: Provides a read only indi-cation of the time remaining in the current BC frame. The reso-lution of this register is 100 µs/LSB.
Message Time Remaining Register: Provides a read only indi-cation of the time remaining before the start of the next messagein a BC frame. The resolution of this register is 1 µs/LSB.
BC Frame Time / RT Last Command / MT Trigger Word Register:In BC mode, this register is used to program the BC frame time,for use in the frame auto-repeat mode. The resolution of thisregister is 100 µs/LSB, with a range of 6.55 seconds; in RT
RTFLAG
RTFAIL
5
PCI ADDRESS DESCRIPTION
00000 ACE Channel #1 RAM Location 0000
00002 ACE Channel #1 RAM Location 0001
00004 ACE Channel #1 RAM Location 0002
::
1FFFE ACE Channel #1 RAM Location FFFF
20000 ACE Channel #2 RAM Location 000020002 ACE Channel #2 RAM Location 0001
20004 ACE Channel #2 RAM Location 0002
::
3FFFE ACE Channel #2 RAM Location FFFF
Notes:1. PCI addresses are specified as the ‘BYTE’ offset within the BU-65549 shared
RAM space.2. ACE addresses are specified as the ‘WORD’ offset within the ACE’s internal
shared RAM.
TABLE 3. SHARED RAM SPACE ADDRESS MAP
ACE SOFTWARE
The BU-65549 is supplied with software Runtime Libraries forand Menu programs for Windows 95/98 and Windows NT. This software is provided with the card at no extra cost.
ACE MENU OVERVIEW
The ACE Menu provides an interface for all ACE BC/RT/MTcards. For detailed information about the ACE Menu, pleaserefer to the ACE Menu User's Guide.
For the 2-channel (BU-65549M2) version of the card, each chan-nel may be independently programmed to function in BusController (BC), Remote Terminal (RT), Monitor Terminal (MT)
6
FIGURE 2. ACE SETUP WINDOW
mode, this register stores the current (or most previous) 1553Command Word processed by the ACE RT; in the Word Monitormode, this register specifies a 16-bit Trigger (Command) Word.The Trigger Word may be used to start or stop the monitor, or togenerate interrupts.
Status Word Register and BIT Word Registers: Providesread-only indications of the BU-65549's RT Status and BITWords.
Test Mode Registers 0-7: These registers may be used to facil-itate self-testing of the BU-65549.
mode. Each channel can only run in one mode at a time. Eachmode has its own run screen.
The ACE Menu provides the necessary functionality for creatingmessages and assembling the messages into a frame for use bythe BC function. The parameters for each message, includingthe command word, data words, and bus selection are modifi-able from the ACE Menu. Setup screens are available for set-ting other operational parameters such as Response Timeout,Retries and Stop-On criteria. Adding these messages to a framestructure creates a BC frame. The ACE Menu allows a frame tobe a composition of many minor frames, where each minorframe will represent the same amount of time, but is not restrict-ed to having the same number of messages. The minor frametime is operator programmable. The number of minor framestimes the minor frame time represents the Major Frame time.Once the frame is complete, the BC Run screen can be used tocontrol the processing of the BC Frame. This screen displaysoperational status and provides controls for setting the minorframe time, the number of frames to send, and the communica-tion stack setup. The Stack setup allows the user to set thename and size of the stack file where the 1553 bus traffic will bestored, and may be viewed at a later time.
Communication information is saved in stack files (*.asf). Therun screens allow configuration of the stack file location and size.All run modes provide the stack view capability. After runningthe card, the generated stack file can be viewed by opening the
7
stack viewer. Within each of the operating mode tool bars andmenus, there is an open stack button that allows quick access tothe stack file open dialog. Once opened, the stack file can besearched for any type of message or error. These stack files arecompatible with the previous version stack files for both theWindows 95 and Windows 3.xx ACE Menu programs.
The Remote Terminal mode operation allows setting the hard-ware to respond to a specified RT address. The setup for a RTis much simpler than that of a BC. The bulk of the setup is usedto specify the data that should be returned based on the sub-address set in the message command word. The data editscreen provides controls to select the sub-address and enter thedata. Once all of the sub-address responses have been deter-mined, the operation of the RT is controlled in the Setup screen.The controls available here are the RT Address, RemoteTerminal to Remote Terminal timeout, and status word bits set.Finally, the RT Run screen will provide options for setting theRemote Terminal Address, and the Stack File.
Monitor operation is also provided. The ACE Menu monitor is afull message monitor that will monitor the 1553 bus traffic,decode the messages (command and data) and save the infor-mation to a Stack File. The monitor is capable of filtering themessage information based on Remote Terminal address, Sub-address, and Transmit/Receive for each message. When all ofthe appropriate filtering has been established, the ResponseTimeout option may be set. The timeout option instructs the
FIGURE 3. BC RUN DIALOG WINDOW FIGURE 4. RT RUN DIALOG WINDOW
Monitor as to how long it must wait before declaring a noresponse message. The Run Monitor screen has controls thatallow setting the Stack File requirements, and to provide accessto the Monitor Trigger capabilities. The monitor is capable of trig-gering its capture based on any combination of the commandword bits, or based on any of the error bits in the RT StatusWord.
Finally, a Stack View capability is provided for each of the modes(BC, RT, and MT). From the Stack Button, a stack file can beselected, and viewed on the screen. Once the stack file is dis-played, there is a capability of 'Finding' any message that wascaptured. The stack file contains information pertaining to theStorage Date, time and number of messages. It also containsthe data portion of the messages, all pertinent status information,and text describing the error type.
The stack file can be searched by message command word, anydata word, or any MIL-STD-1553 error. Each of the search cri-teria may be combined with a mask to allow searching for a fam-ily of command or data words. The search direction is selectablebetween up and down.
For the 2-channel (BU-65549M2) version of the card, each chan-nel may be independently programmed to function in BusController (BC), Remote Terminal (RT), Monitor Terminal (MT)mode. Each channel can only run in one mode at a time. Eachmode has its own run screen.
8
FIGURE 6. MONITOR MODE - STACK VIEW
ACE RUNTIME LIBRARIES
The Runtime Libraries for the BU-65549 come in a 32-bit versionto support 32-bit Windows. Using the Runtime Library, applica-tions may be created that are capable of controlling the card ineither the BC, RT or MT mode. The newest version of thisRuntime Library supports C and Visual Basic programming.Included with the ACE Runtime Library are sample applicationsfor Bus Controller, Remote Terminal, and Monitor mode control.There are also sample programs for self-test and loop back tests.The self-test program tests and reports any errors found with themajor portions of the hardware including registers, RAM, interruptgeneration, and the protocol unit. The loop back tests force theBU-65549 card to communicate with itself. This test verifies theprotocol unit and the transceivers to a greater degree than is per-formed by the Selftst2 program. The source for all of the test andsample programs is provided free of charge. These source pro-grams may be used as a starting point for custom applications.
FIGURE 5. MONITOR MODE WINDOW
The following source code represents the simplicity ofwriting code for the BU-65549 PCI card. This programsends 10 words of data to RT 1 sub-address 5 on chan-nel A, followed by a 32 word transmit to RT 6 sub-address1 on channel 'A'. It then receives 5 words from RT 8 sub-address 4 on channel 'A', followed by a 32 word receivefrom RT 7 sub-address 2 on channel 'A'. Note that thecreation of a 32-word message requires only that the databe defined in a buffer, and then a single function call toBuSendData(…) be made. Similarly, to receive data froma RT, a buffer must be defined, and a call toBuGetData(…) will be made. This encapsulated function-ality relieves the application developer from having toknow the dirty details of the 1553 protocol hardware andregisters.
9
The following code is from the BCDEMO1.C sample program supplied with the BU-65549 hardware.
#include <stdio.h>#include <stdlib.h>#include <stdace.h>
void main ()
BuConf_t Conf; /* ACE library configuration type */BuError_t Err; /* ACE library error status type */
U16BIT data[32]= 0X0000,0x1111,0x2222,0x3333,0x4444,0x5555,0x6666,0x7777,0x8888,0x9999,0xAAAA,0xBBBB,0xCCCC,0xDDDD,0xEEEE,0xFFFF,0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000;
/* display revision info */printf("%s\n\n",BuRev());printf("\nThis BC Demo sets the Ace card in BC mode and sends a few messages.\n\n");
/* setup configuration for device X and open ACE library */printf("Choose the logical device # of your BC:> ");scanf("%d",&Conf.ConfDev);
Err=BuOpen32(&Conf);if(Err)
printf("BuError %d %s\n",Err,BuErrorStr(Err));return;
/* opens bus controller mode */BuBCOpen();
/* send 10 words to rt 5 sa 1 on channel A */Err=BuBCSendData(CW_CHANNELA,5,1,data,10);printf("%s\n",BuErrorStr(Err));
/* send 32 words to rt 6 sa 1 on channel Aadded this [01-SEP-1995] to test 32 word case */
Err=BuBCSendData(CW_CHANNELA,6,1,data,32);printf("%s\n",BuErrorStr(Err));
/* receive 5 words from rt 8 sa 4 on channel A */Err=BuBCGetData(CW_CHANNELA,8,4,data,5);printf("%s\n",BuErrorStr(Err));
/* display data */if(!Err)int x;for(x=0;x<5;x++)printf("%04x ",data[x]);printf("\n");
/* receive 32 words from rt 7 sa 2 on channel Aadded this [01-SEP-1995] to test 32 word case */
Err=BuBCGetData(CW_CHANNELA,7,2,data,32);printf("%s\n",BuErrorStr(Err));
/* display data */if(!Err)int x;for(x=0;x<32;x++)printf("%04x ",data[x]);
/* closes bus controller mode */BuBCClose();
/* must call at end of ACE library use */BuClose();
MESSAGE MONITORENABLED(MMT)
10
RT SUBADDRESS CONTROL WORD EOM4
RT CIRCULAR BUFFER ROLLOVER5
TIME TAG ROLLOVER6
RT ADDRESS PARITY ERROR7
BC RETRY8
RT MODE CODE/MT PATTERN TRIGGER9
MT DATA STACK ROLLOVER10
MT COMMAND STACK ROLLOVER11
BC/RT COMMAND STACK ROLLOVER12
END OF MESSAGE
TRANSMITTER TIMEOUT13
0 (LSB)
LOGIC "0"14
STATUS SET
RESERVED15 (MSB)
1
DESCRIPTIONBIT
FORMAT ERROR
TABLE 4. INTERRUPT MASK REGISTER (READ/WRITE 00H)
2
BC END OF FRAME3
MONITOR ACTIVE(Read Only)
BC MESSAGE IN PROGRESS(Read Only)
0 (LSB)
MONITOR TRIGGERED(Read Only)
S00NOT USEDBC FRAME IN PROGRESS (ReadOnly)
1
MONITORENABLED(Read Only)
S01NOT USEDBC ENABLED2
NOT USEDS02NOT USEDDOUBLED/SINGLE RETRY3
NOT USEDS03NOT USEDRETRY ENABLED4
NOT USEDS04NOT USEDINTERMESSAGE GAP TIMER ENABLED
5
NOT USEDS05NOT USEDINTERNAL TRIGGER ENABLED6
S06RTFLAG (Enhanced ModeOnly)
EXTERNAL TRIGGER ENABLED7
NOT USEDS07SUBSYSTEM FLAGFRAME AUTO-REPEAT8
STOP-ON-TRIGGERS08SERVICE REQUESTSTATUS SET STOP-ON-FRAME9
START-ON-TRIGGERS09BUSY10
TRIGGER ENABLEDWORD
S10DYNAMIC BUS CONTROLACCEPTANCE
FRAME STOP-ON-ERROR11
MESSAGE MONITORENABLED(MMT)
MESSAGE MONITOR ENABLED (MMT)
MESSAGE STOP-ON-ERROR12
CURRENT AREA B/ACURRENT AREA A/BCURRENT AREA B/ACURRENT AREA B/A13
(logic 1)(logic 0)(logic 0)MT/BC-RT (logic 0)14
(logic 0)(logic 1)(logic 1)RT/BC-MT (logic 0)
RT WITH ALTERNATESTATUS (Enhanced Only)
RT WITHOUT ALTERNATESTATUS
BC FUNCTION ( Enhanced Mode Only
Bits 11-0)
BIT
TABLE 5. CONFIGURATION REGISTER #1 (READ/WRITE 01H)
RT MESSAGE IN PROGRESS(Enhanced mode only, Read Only)
MONITOR FUNCTION(Enhanced mode only
bits 12-0)
STATUS SET STOP-ON-MESSAGE
EXTERNAL TRIGGERENABLED
RT MESSAGE IN PROGRESS(Read Only)
15 (MSB)
MINI-ACE REGISTER BIT MAPS
SEPARATE BROADCAST DATA0 (LSB)
ENHANCED RT MEMORY MANAGEMENT1
CLEAR SERVICE REQUEST2
LEVEL/PULSE* INTERRUPT REQUEST3
INTERRUPT STATUS AUTO CLEAR4
LOAD TIME TAG ON SYNCHRONIZE5
CLEAR TIME TAG ON SYNCHRONIZE6
TIME TAG RESOLUTION 0 (TTR0)7
TIME TAG RESOLUTION 1 (TTR1)8
TIME TAG RESOLUTION 2(TTR2)9
256-WORD BOUNDARY DISABLE10
OVERWRITE INVALID DATA11
RX SA DOUBLE BUFFER ENABLE12
BUSY LOOKUP TABLE ENABLE13
LOGIC “0”14
ENHANCED INTERRUPTS15 (MSB)
DESCRIPTIONBIT
TABLE 6. CONFIGURATION REGISTER #2 (READ/WRITE 02H)
RESET0 (LSB)
BC/MT START1
INTERRUPT RESET2
TIME TAG RESET3
TIME TAG TEST CLOCK4
BC STOP-ON-FRAME5
BC/MT STOP-ON-MESSAGE6
RESERVED7
••
••
••
RESERVED
DESCRIPTIONBIT
TABLE 7. START/RESET REGISTER (WRITE 03H)
11
COMMAND STACK POINTER 00 (LSB)
••
••
••
COMMAND STACK POINTER 15
DESCRIPTIONBIT
TABLE 8. BC/RT COMMAND STACK POINTER REG. (READ 03H)
RT-RT FORMAT0 (LSB)
BROADCAST FORMAT1
MODE CODE FORMAT2
SUBSYS FLAG BIT MASK
1553A/B SELECT3
EOM INTERRUPT ENABLE4
MASK BROADCAST BIT5
OFF LINE SELF TEST6
BUS CHANNEL A/B7
RETRY ENABLED8
RESERVED BITS MASK9
TERMINAL FLAG BIT MASK10
SUBSYS BUSY BIT MASK12
SERVICE REQUEST BIT MASK13
M.E. MASK14
RESERVED
DESCRIPTIONBIT
11
TABLE 9. BC CONTROL WORD REGISTER (READ/WRITE 04H)
BCST: MEMORY MANAGEMENT 0 (MM0)0 (LSB)
BCST: MEMORY MANAGEMENT 1 (MM1)1
BCST:MEMORY MANAGEMENT 2 (MM2)2
TX: MEMORY MANAGEMENT 1 (MM1)
BCST: CIRC BUF INT3
BCST: EOM INT4
RX: MEMORY MANAGEMENT 0 (MM0)5
RX: MEMORY MANAGEMENT 1 (MM1)6
RX: MEMORY MANAGEMENT 2 (MM2)7
RX: CIRC BUF INT8
RX: EOM INT9
TX: MEMORY MANAGEMENT 0 (MM0)10
TX: MEMORY MANAGEMENT 2 (MM2)12
TX: CIRC BUF INT13
TX: EOM INT14
RX: DOUBLE BUFFER ENABLE
DESCRIPTIONBIT
11
TABLE 10. RT SUBADDRESS CONTROL WORD REGISTER(READ/WRITE 04H)
TABLE 11. TIME TAG REGISTER (READ/WRITE 05H)
BIT DESCRIPTION
TIME TAG 15
• •
• •
• •
0 (LSB) TIME TAG 0
15 (MSB)
15 (MSB)
15 (MSB)
15 (MSB)
15 (MSB)
12
END OF MESSAGE0 (LSB)
STATUS SET1
FORMAT ERROR2
MT COMMAND STACK ROLLOVER
BC END OF FRAME3
RT SUBADDRESS CONTROL WORD EOM4
RT CIRCULAR BUFFER ROLLOVER5
TIME TAG ROLLOVER6
RT ADDRESS PARITY ERROR7
BC RETRY8
RT MODE/MT PATTERN TRIGGER9
MT DATA STACK ROLLOVER10
BC/RT COMMAND STACK ROLLOVER12
TRANSMITTER TIMEOUT13
RESERVED
MASTER INTERRUPT
DESCRIPTIONBIT
11
TABLE 12. INTERRUPT STATUS REGISTER (READ/WRITE 06H)
ENHANCED MODE CODE HANDLING0 (LSB)
1553A MODE CODES ENABLE1
FAIL-FLAG WRAP ENABLE2
MT COMMAND STACK SIZE 0
BUSY RX TRANSFER DISABLE3
ILLEGAL RX TRANSFER DISABLE4
ALTERNATE STATUS WORD ENABLE5
OVERRIDE MODE T/R ERROR6
ILLEGALIZATION DISABLED7
MT DATA STACK SIZE 08
MT DATA STACK SIZE 19
MT DATA STACK SIZE 210
MT COMMAND STACK SIZE 112
BC/RT COMMAND STACK SIZE 013
BC/RT COMMAND STACK SIZE 114
ENHANCED MODE ENABLE
DESCRIPTIONBIT
11
TABLE 13. CONFIGURATION REGISTER #3 (READ/WRITE 07H)
TEST MODE 00 (LSB)
TEST MODE 11
TEST MODE 22
BROADCAST MASK ENABLE/XOR
LATCH RT ADDRESS WITH CONFIG #53
MT TAG GAP OPTION4
VALID BUSY/NO DATA5
VALID M.E./NO DATA6
2ND RETRY ALT/SAME BUS7
1ST RETRY ALT/SAME BUS8
RETRY IF STATUS SET9
RETRY IF -A AND M.E.10
EXPANDED BC CONTROL WORD ENABLE12
MODE COMMAND OVERRIDE BUSY13
INHIBIT BIT WORD IF BUSY14
EXTERNAL BIT WORD ENABLE
DESCRIPTIONBIT
11
TABLE 14. CONFIGURATION REGISTER #4 (READ/WRITE 08H)
RT ADDRESS PARITY0 (LSB)
RT ADDRESS 01
RT ADDRESS 12
EXPANDED CROSSING ENABLE
RT ADDRESS 23
RT ADDRESS 34
RT ADDRESS 45
LOGIC “1”6
BROADCAST DISABLED7
GAP CHECK ENABLED8
RESPONSE TIMEOUT SELECT 09
RESPONSE TIMEOUT SELECT 110
EXTERNAL TX INHIBIT B, read only12
EXTERNAL TX INHIBIT A, read only13
LOGIC “0”14
12MHZ CLOCK SELECT
DESCRIPTIONBIT
11
TABLE 15. CONFIGURATION REGISTER #5 (READ/WRITE 09H)
15 (MSB)
15 (MSB)
15 (MSB)
15 (MSB)
14
13
MONITOR DATA STACK ADDRESS 00 (LSB)
••
••
••
MONITOR DATA STACK ADDRESS 1515 (MSB)
DESCRIPTIONBIT
TABLE 16. MONITOR DATA STACK ADDRESS REGISTER(READ/WRITE 0AH)
Note: resolution = 100 µµs per LSB
BC FRAME TIME REMAINING 00 (LSB)
••
••
••
BC FRAME TIME REMAINING 15
DESCRIPTIONBIT
TABLE 17. BC FRAME TIME REMAINING REGISTER (READ/WRITE 0BH)
Note: resolution = 1 µµs per LSB
BC MESSAGE TIME REMAINING 00 (LSB)
••
••
••
BC MESSAGE TIME REMAINING 15
DESCRIPTIONBIT
TABLE 18. BC MESSAGE TIME REMAINING REGISTER(READ/WRITE 0CH)
BIT 00 (LSB)
••
••
••
BIT 15
DESCRIPTIONBIT
TABLE 19. BC FRAME TIME/RT LAST COMMAND/MT TRIGGERREGISTER (READ/WRITE 0DH)
TERMINAL FLAG0 (LSB)
DYNAMIC BUS CONTROL ACCEPT1
SUBSYSTEM FLAG2
LOGIC “0”
BUSY3
BROADCAST COMMAND RECEIVED4
RESERVED5
RESERVED6
RESERVED7
SERVICE REQUEST8
INSTRUMENTATION9
MESSAGE ERROR10
LOGIC “0”13
LOGIC “0”14
LOGIC “0”12
LOGIC “0”15 (MSB)
DESCRIPTIONBIT
11
TABLE 20. RT STATUS REGISTER (READ 0EH)
COMMAND WORD CONTENTS ERROR0 (LSB)
RT-RT 2ND COMMAND WORD ERROR1
RT-RT NO RESPONSE ERROR2
TRANSMITTER SHUTDOWN B
RT-RT GAP/SYNCH/ADDRESS ERROR3
PARITY/MANCHESTER ERROR RECEIVED4
INCORRECT SYNC RECEIVED5
LOW WORD COUNT6
HIGH WORD COUNT7
CHANNEL B/A8
TERMINAL FLAG INHIBITED9
TRANSMITTER SHUTDOWN A10
HANDSHAKE FAILURE12
LOOP TEST FAILURE A13
LOOP TEST FAILURE B14
TRANSMITTER TIMEOUT15 (MSB)
DESCRIPTIONBIT
11
TABLE 21. RT BIT WORD REGISTER (READ 0FH)
15 (MSB)
15 (MSB)
15 (MSB)
14
COMMAND WORD CONTENTS ERROR0 (LSB)
RT-RT 2ND COMMAND ERROR1
RT-RT GAP/SYNC/ADDRESS ERROR2
RT-RT FORMAT
INVALID WORD3
INCORRECT SYNC4
WORD COUNT ERROR5
ILLEGAL COMMAND WORD6
DATA STACK ROLLOVER7
LOOP TEST FAIL8
NO RESPONSE TIMEOUT9
FORMAT ERROR 10
ERROR FLAG12
CHANNEL B/A13
SOM14
EOM
DESCRIPTIONBIT
11
TABLE 23. RT MODE BLOCK STATUS WORD
GAP TIME (LSB)
MODE CODE0 (LSB)
CONTIGUOUS DATA/GAP1
CHANNEL B/A2
COMMAND/DATA3
ERROR4
BROADCAST5
THIS RT6
WORD FLAG7
••
••
••
GAP TIME (MSB)
DESCRIPTIONBIT
8
TABLE 24. WORD MONITOR IDENTIFICATION WORD
COMMAND WORD CONTENTS ERROR0 (LSB)
RT-RT 2ND COMMAND ERROR1
RT-RT GAP/SYNC/ADDRESS ERROR2
RT-RT TRANSFER
INVALID WORD3
INCORRECT SYNC4
WORD COUNT ERROR5
RESERVED6
DATA STACK ROLLOVER7
GOOD DATA BLOCK TRANSFER8
NO RESPONSE TIMEOUT9
FORMAT ERROR 10
ERROR FLAG12
CHANNEL B/A13
SOM14
EOM15 (MSB)
DESCRIPTIONBIT
11
TABLE 25. MESSAGE MONITOR MODE BLOCK STATUS WORD
TABLE 22. BC MODE BLOCK STATUS WORD
11
BIT DESCRIPTION
15 (MSB) EOM
14 SOM
13 CHANNEL B/A
12 ERROR FLAG
10 FORMAT ERROR
9 NO RESPONSE TIMEOUT
8 LOOP TEST FAIL
7 MASKED STATUS SET
6 RETRY COUNT 1
5 RETRY COUNT 0
4 GOOD DATA BLOCK TRANSFER
3 WRONG STATUS ADDRESS/NO GAP
STATUS SET
2 WORD COUNT ERROR
1 INCORRECT SYNC TYPE
0 (LSB) INVALID WORD
TABLES 22 TO 25 ARE NOT REGISTERS, BUT THEY ARE WORDS STORED IN RAM:
15 (MSB)
15 (MSB)
BUS CONTROLLER (BC) ARCHITECTURE
The BC protocol of the BU-65549 implements all MIL-STD-1553B message formats. Message format is programmable ona message-by-message basis by means of bits in the BC ControlWord and the bit of the Command Word for the respectivemessage. The BC Control Word allows 1553 message format,1553A/B type RT, bus channel, self-test, and Status Word mask-ing to be specified on an individual message basis. In addition,automatic retries and/or interrupt requests may be enabled ordisabled for individual messages. The BC performs all errorchecking required by MIL-STD-1553B. This includes validationof response time, sync type and sync encoding, Manchester IIencoding, parity, bit count, word count, Status Word RT Addressfield, and various RT-to-RT transfer errors. The BU-65549's BCresponse timeout value is programmable with choices of 18, 22,50, and 130 µs. The longer response timeout values allow foroperation over long buses and/or the use of repeaters.
FIGURE 7 illustrates BC intermessage gap and frame timing.The BU-65549 may be programmed to process BC frames of upto 512 messages with no processor intervention. It is possible toprogram for either single frame or frame auto-repeat operation.In the auto-repeat mode, the frame repetition rate may be con-trolled using a programmable BC frame timer. The internal BCframe time is programmable up to 6.55 seconds in increments of100 ms. In addition to BC frame time, message gap time,defined as the start of the current message to the start of thesubsequent message, is programmable on an individual mes-sage basis. The time between individual successive messagesis programmable up to 65.5 ms, in increments of 1 µs.
BC MEMORY ORGANIZATION
TABLE 26 illustrates a typical memory map for BC mode. It isimportant to note that the only fixed locations for the BU-65549in the Standard (non-frame Auto-Repeat) BC mode are for thetwo Stack Pointers (address locations 0100 (hex) and 0104) andfor the two Message Count locations (0101 and 0105). Enablingthe Frame Auto-Repeat mode will reserve four more memorylocations for use in the Enhanced BC mode; these locations arefor the two Initial Stack Pointers (address locations 102 (hex)
R/T
15
FIGURE 7. BC MESSAGE GAP AND FRAME TIMING
MESSAGE NO. 1 MESSAGE NO. 2 MESSAGE NO. 1
MESSAGEGAP TIME
FOR MESSAGE NO. 1
BC FRAME TIME
INTERMESSAGE GAP TIME
Stack B
Message Block 11
Registers
FF00-FFFF
2CC-2F2
260-27F
Not Used
Message Block 10
Not Used
FEFE-FEFF
2A6-2CB
25E-25F
Message Block 1709
Message Block 9
Message Block 8
FED8-FEFD
280-2A5
238-25D
•
•
•
•
•
•
•
•
Initial Message Count A (see note 1)(Auto-Frame Repeat Mode)
•
•
•
•
Message Block 20154-0179
Message Block 1012E-0153
Message Block 00108-012D
Initial Message Count B (see note 1)(Auto-Frame Repeat Mode)
0107
Initial Stack Pointer B (see note 1)(Auto-Frame Repeat Mode)
0106
Message Count B0105
Stack Pointer B0104
Initial Stack Pointer A (see note 1) (Auto-Frame Repeat Mode)
0102
Message Count A (fixed location)0101
Stack Pointer A (fixed location)0100
Stack A0000-00FF
DESCRIPTIONADDRESS
(note 2)
0103
TABLE 26. TYPICAL BC MEMORY ORGANIZATION(SHOWN FOR 64K RAM)
Notes:1. Used only in the Enhanced BC mode with Frame Auto-Repeat enabled. 2. Address represents the word offset from the memory base address in the
shared RAM address space.
and 106) and for the Initial Message Count locations (103 and107). The user is free to locate the Stack and BC MessageBlocks anywhere else within the 64K shared RAM addressspace.
For simplicity of illustration, assume the allocation of the maxi-mum length of a BC message for each message block in the typ-ical BC memory map of TABLE 26. The maximum size of a BCmessage block is 38 words, for an RT-to-RT transfer of 32 DataWords (Control + 2 Commands + Loopback + 2 Status Words +32 Data Words).
Note, however, that this example assumes the disabling of the 256-word boundaries.
BC MEMORY MANAGEMENT
FIGURE 8 illustrates the BU-65549's BC memory managementscheme. One of the BC memory management features is theglobal double buffering mechanism. This provides for two setsof the various BC mode data structures: the Stack Pointer andMessage Counter locations, Descriptor Stack areas, and BCmessage blocks. Bit 13 of Configuration Register #1 selects thecurrent active area. At any point in time, the BU-65549's internal
1553 memory management logic may access only the variousdata structures within the “active” area; it will not change to thealternate area until a restart occurs. FIGURE 8 delineates the“active” and “inactive” areas by the nonshaded and shadedareas, respectively; however, at any point in time, both the“active” and “nonactive” areas are accessible by the hostprocessor. In many applications, the host processor will accessthe “nonactive” area, while the 1553 bus processes the “active”area messages.
The BC may be programmed to transmit multimessage framesof up to 512 messages. The number of messages to beprocessed is programmable by the Active Area Message Countlocation in the shared RAM, initialized by the host processor. Inaddition, the host processor must initialize another location, theActive Area Stack Pointer. The Stack Pointer references thefour-word message block descriptor in the Stack area of sharedRAM for each message to be processed. The BC Stack size isprogrammable with choices of 256, 512, 1024, and 2048 words.
In the BC Frame Auto-Repeat mode, the Initial Stack Pointer andInitial Message Counter locations must be loaded by the hostprior to the processing of the first frame. The single frame modedoes not use these two locations.
16
FIGURE 8. BC MODE MEMORY MANAGEMENT
15 13 0
CURRENTAREA B/A
CONFIGURATIONREGISTER #1
INITIAL STACKPOINTERS (NOTE)
INITIAL MESSAGECOUNTERS (NOTE)
MESSAGECOUNTERS
STACKPOINTERS
BLOCK STATUS WORD
TIME TAG WORD
INTERMESSAGEGAP TIME WORD
MESSAGEBLOCK ADDR
DESCRIPTORSTACKS
MESSAGEBLOCKS
MESSAGEBLOCK
MESSAGEBLOCK
Note: Initial Stack Pointers and InitialMessage Counters used only in BCFrame Auto-Repeat Mode.
The third and fourth words of the BC block descriptor are theIntermessage Gap Time and the Message Block Address for therespective message. These two memory locations must be writ-ten by the host processor prior to the start of message process-ing. Use of the Intermessage Gap Time is optional. The BlockAddress pointer specifies the starting location for each messageblock. The first word of each BC message block is the BCControl Word.
At the start and end of each message, the Block Status and TimeTag Words write to the message block descriptor in the stack.The Block Status Word includes indications of message inprocess or message completion, bus channel, Status Set,response timeout, retry count, Status address mismatch, looptest (on-line self-test) failure, and other error conditions. TABLE 22 illustrates the bit mapping of the BC Block Statusword. The 16-bit Time Tag Word will reflect the current contentsof the internal Time Tag Register. This read/writable register,which operates for all three modes, has programmable resolu-tion of from 2 to 64 µs/LSB.
BC MESSAGE BLOCK FORMATS AND BC CONTROL WORD
In BC mode, the BU-65549 supports all MIL-STD-1553 messageformats. For each 1553 message format, the BU-65549 man-dates a specific sequence of words within the BC MessageBlock. This includes locations for the Control, Command and(transmitted) Data Words that are to be read from RAM by theBC protocol logic. In addition, subsequent contiguous locationsmust be allocated for storage of received Loopback, RT Statusand Data Words. FIGURE 9 illustrates the organization of the BCmessage blocks for the various MIL-STD-1553 message for-mats.
Note that for all of the message formats, the BCControl Word is located in the first location of themessage block.
For each of the BC Message Block formats, the first word in theblock is the BC Control Word. The BC Control Word is not trans-mitted on the 1553 bus. Instead, it contains bits that select theactive bus and message format, enable off-line self-test, mask-ing of Status Word bits, enable retries and interrupts, and spec-ify MIL-STD-1553A or -1553B error handling. The bit mappingand definitions of the BC Control Word are illustrated in TABLE 9.
The BC Control Word is followed by the Command Word to betransmitted, and subsequently by a second Command Word (foran RT-to-RT transfer), followed by Data Words to be transmitted(for Receive commands). The location after the last word to betransmitted is reserved for the Loopback Word. The LoopbackWord is an on-line self-test feature. The subsequent locations
17
BC-to-RT Transfer
Control Word
Receive Command Word
Data Word #1
Data Word #2
.
.
.
Last Data Word
Last Data Word Looped Back
Status Received Last Data Word
.
.
.
Data Word #2
Data Word #1
Status Received
Transmit Command Looped Back
Transmit Command Word
Control Word
RT-to-BC Transfer
Transmit CommandLooped Back
Rx RT Status Word
Last Data
.
.
.
Data #2
Data #1
Tx RT Status Word
Transmit Command
Receive Command
Control Word
RT-to-RT Transfer
Mode CommandLooped Back
Status Received
Mode Command
Control Word
Mode Code;No Data
Mode CommandLooped Back
Data Word
Status Received
Tx Mode Command
Control Word
Tx Mode Code;With Data
Tx CommandLooped Back
Last Data
.
.
.
Data #2
Data #1
Tx RT Status Word
Tx Command
Rx Broadcast Command
Control Word
RT-to-RTs (Broadcast)Transfer
Last Data StatusWord
Last Data
.
.
.
Data #2
Data #1
Broadcast Command
Control Word
Broadcast
Data Word
Data Word LoopedBack
Status Received
Rx Mode Command
Control Word
Rx Mode Code;With Data
Broadcast Mode CommandLooped Back
Broadcast Mode Command
Control Word
Broadcast Mode Code;No Data
Data Word Looped Back
Data Word
Broadcast Mode Command
Control Word
Broadcast Mode Code;With Data
FIGURE 9. BC MESSAGE BLOCK FORMATS
after the Loopback Word are reserved for received Status Wordsand Data Words (for Transmit commands).
AUTOMATIC RETRIES
The BU-65549 BC can be set to implement automatic messageretries. When enabled, retries will occur, following responsetimeout or format error conditions. As additional options, retriesmay be enabled when the Message Error Status Word bit is setby a 1553A RT or following a “Status Set” condition. For a failedmessage, either one or two message retries will occur, and thebus channel (same or alternate) is independently programmablefor the first and second retry attempts. Retries may be enabledor disabled on an individual message basis.
BC INTERRUPTS
BC interrupts may be enabled by the Interrupt Mask Register forStack Rollover, Retry, End-of-Message (global), End-of-Message (in conjunction with the BC Control Word for individualmessages), response timeout, message error, end of BC frame,and Status Set conditions. The definition of “Status Set” is pro-grammable on an individual message basis by means of the BCControl Word. This allows for masking (“care/don't care”) for theindividual RT Status Word bits received.
REMOTE TERMINAL (RT) ARCHITECTURE
The RT protocol design of the BU-65549 represents DDC's fifthgeneration implementation of a 1553 RT. One of the salient fea-tures of the ACE's RT architecture is its true multiprotocol func-tionality. This includes programmable options for support of MIL-STD-1553A, the various McAir protocols, and MIL-STD-1553BNotice 2. The BU-65549 RT response time is 2 to 5 µs dead time(4 to 7 µs per 1553B), providing compliance to all the 1553 pro-tocols. Additional multiprotocol features of the BU-65549 includeoptions for full software control of RT Status and Built-in-Test(BIT) words. Alternatively, for 1553B applications, these wordsmay be formulated in real time by the BU-65549 protocol logic.
The BU-65549 RT protocol design implements all the MIL-STD-1553B message formats and dual redundant mode codes. Thisdesign is based largely on previous generation products thathave passed SEAFAC testing for MIL-STD-1553B compliance.The ACE RT performs comprehensive error checking, word andformat validation, and checks for various RT-to-RT transfererrors. Other key features of the BU-65549 RT include a set ofinterrupt conditions, internal command illegalization, and pro-grammable busy by subaddress.
RT MEMORY ORGANIZATION
TABLE 27 illustrates a typical memory map for the BUS-65549in RT mode. As in BC mode, the two Stack Pointers reside infixed locations in the shared RAM address space: address 0100
(hex) for the Area A Stack Pointer and address 0104 for the AreaB Stack Pointer. Besides the Stack Pointer, for RT mode thereare several other areas of the ACE address space designated asfixed locations. All RT modes of operation require the Area A(and may use Area B) Lookup Tables. Also allocated, are sev-eral fixed locations for optional features: Command IllegalizationLookup Table, Mode Code Selective Interrupt Table, Mode CodeData Table, and Busy Bit Lookup Table. It should be noted thatany unenabled optional fixed locations may be used for generalpurpose storage (data blocks).
The RT Lookup tables, which provide a mechanism for mappingdata blocks for individual Tx/Rx/Bcst-subaddresses to areas inthe RAM, occupy address range locations are 0140 to 01BF forArea A (and 01C0 to 023F for Area B). The RT lookup tablesinclude Subaddress Control Words and the individual Data BlockPointers. If used, address range 0300-03FF will be dedicated asthe illegalizing section of RAM. The actual Stack RAM area andthe individual data blocks may be located in any of the nonfixedareas in the shared RAM address space.
18
Approximately 1600 more data blocks(or monitor stacks)
Data Block 255
3000-FFFF
2FE0-2FFF
••
••
•·•
Data Block 50420-043F
Data Block 40400-041F
Command Illegalizing Table (fixed area)0300-03FF
RESERVED
Data Block 0-30280-02FF
Registers0260-027F
(not used)0248-025F
Busy Bit Lookup Table (fixed area)0240-0247
Lookup Table B (fixed area)01C0-023F
Lookup Table A (fixed area)0140-01BF
Mode Code Data (fixed area)0110-013F
Mode Code Selective Interrupt Table (fixed area)0108-010F
Stack Pointer B (fixed location)0104
RESERVED0101-0103
Stack Pointer A (fixed location)0100
Stack A0000-00FF
DESCRIPTIONADDRESS
(HEX)
0105-0107
TABLE 27. TYPICAL RT MEMORY MAP (SHOWN FOR 64K RAM)
Notes:1. Address represents the word offset from the memory base address in theshared RAM address space.
RT MEMORY MANAGEMENT
One of the salient features of the ACE series products is the flex-ibility of its RT memory management architecture. The RT archi-tecture allows the memory management scheme for each trans-mit, receive, or broadcast subaddress to be programmable on asubaddress basis. Also, in compliance with MIL-STD-1553BNotice 2, the BU-65549 provides an option to separate datareceived from broadcast messages from non-broadcast receiveddata.
Besides supporting a global double buffering scheme (as in BCmode), the ACE RT provides a pair of 128-word Lookup Tablesfor memory management control, programmable on a subad-dress basis (refer to TABLE 28). The 128-word tables include32-word tables for transmit message pointers and receive mes-sage pointers. There is also a third, optional Lookup Table forbroadcast message pointers, providing Notice 2 compliance, if
necessary. For most applications, the subaddress tables pro-vide more flexible buffering than the global scheme and currentArea B tables are not used.
The fourth section of each of the RT Lookup Tables stores the32 Subaddress Control Words (refer to TABLE 10 and TABLE29). The individual Subaddress Control Words may be used toselect the RT memory management option and interrupt schemefor each transmit, receive, and (optionally) broadcast subad-dress.
For each transmit subaddress, there are two possible memorymanagement schemes: (1) single message; and (2) circularbuffer. The use of a single buffer type is recommended for trans-mitting messages. For each receive (and optionally broadcast)subaddress, there are three possible memory managementschemes: (1) single message; (2) double buffered; and (3) cir-cular buffer. For each transmit, receive and broadcast subad-dress, there are two interrupt conditions programmable by therespective Subaddress Control Word: (1) after every messageto the subaddress; (2) after a circular buffer rollover. An addi-tional table in RAM may be used to enable interrupts followingselected mode code messages.
When using the circular buffer scheme for a given subaddress,the size of the circular buffer is programmable by three bits of theSubaddress Control Word (see TABLE 29). The options for cir-cular buffer size are 128, 256, 512, 1024, 2048, 4096, and 8192Data Words.
SINGLE MESSAGE MODE
FIGURE 10 illustrates the RT Single Message memory manage-ment scheme. When operating the BU-65549 in its default con-figuration, the Single Message scheme is implemented for alltransmit, receive, and broadcast subaddresses. In the SingleMessage mode (also in the Double Buffer and Circular Buffermodes), there is a global double buffering scheme, controlled bybit 13 of Configuration Register #1. This selects from betweenthe two sets of the various data structures shown in the figure:the Stack Pointers (fixed addresses), Descriptor Stacks (userdefined addresses), RT Lookup Tables (fixed addresses), andRT data word blocks (user defined addresses). FIGURES 10,11, and 12 delineate the “active” and “nonactive” areas by thenonshaded and shaded areas, respectively.
As shown, the ACE stores the Command Word from each mes-sage received in the fourth location within the message descrip-tor (in the stack) for the respective message. The bit, sub-address field, and (optionally) broadcast/own address, index intothe active area Lookup Table, to locate the data block pointer forthe current message. The BU-65549 RT memory managementlogic then accesses the data block pointer to locate the startingaddress for the Data Word block for the current message. Themaximum size for an RT Data Word block is 32 words.
R/T
19
Circular Buffer ofSpecified Size
8192-Word111
4096-Word011
1024-Word001
512-Word110
256-Word010
128-Word100
Single Message or Double Buffered000
COMMENTDESCRIPTIONMM0MM1MM2
TABLE 29. SUBADDRESS CONTROL WORDMemory Management Subaddress Buffer Scheme
2048-Word101
Note: Address represents the word offset from the memory base address in thecommon memory address space.
SubaddressControl WordLookup Table
(Optional)
SACW_SA0...
SACW_SA31
0220...
023F
01A0...
01BF
BroadcastLookup Table
(Optional)
Bcst_SA0...
Bcst_SA31
0200...
021F
0180...
019F
TransmitLookup Table
Tx_SA0...
Tx_SA31
01E0...
01FF
0160...
017F
Receive(/Broadcast)
Lookup Table
Rx(/Bcst)_SA0...
Rx(/Bcst)_SA31
01C0...
01DF
0140...
015F
COMMENTDESCRIPTIONAREA BAREA A
TABLE 28. RT LOOK-UP TABLES
20
FIGURE 10. RT MEMORY MANAGEMENT: SINGLE MESSAGE MODE
DATABLOCKS
DATA BLOCK
DATA BLOCK
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMANDWORD
DESCRIPTORSTACKS
LOOK-UPTABLE ADDR
LOOK-UP TABLE(DATA BLOCK ADDR)
15 13 0
CURRENTAREA B/A
CONFIGURATIONREGISTER #1
STACKPOINTERS
CIRCULARBUFFER
ROLLOVER
15 13 0
RECEIVED(TRANSMITTED)
MESSAGEDATA
(NEXT LOCATION)
128,256
8192WORDS
POINTER TOCURRENT
DATA BLOCK
POINTER TO NEXT DATA
BLOCK
LOOK-UP TABLEENTRY
CIRCULARDATA
BUFFERLOOK-UP TABLES
LOOK-UPTABLE
ADDRESS
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMANDWORD
CONFIGURATIONREGISTER #1
STACKPOINTERS
DESCRIPTORSTACK
CURRENTAREA B/A
TX/RS/BCST_SA LOOK-UP TABLE ENTRY IS UPDATEDFOLLOWING VALID RECEIVE (BROADCAST) MESSAGE ORFOLLOWING COMPLETION OF TRANSIT MESSAGE.
*
*
FIGURE 11. RT MEMORY MANAGEMENT: CIRCULAR BUFFER MODE
21
To implement a data wraparound subaddress, as required byNotice 2 of MIL-STD-1553B, the Single Message schemeshould be used to define the transmit and receive pointer for thewraparound subaddress to the same data block. Notice 2 rec-ommends subaddress 30 as the wraparound subaddress.
CIRCULAR BUFFER MODE
FIGURE 11 illustrates the RT circular buffer memory manage-ment scheme. The circular buffer mode facilitates bulk datatransfers. The size of the RT circular buffer, shown on the rightside of the figure, is programmable from 128 to 8192 words (ineven powers of 2) by the respective Subaddress Control Word.As in the single message mode, the host processor initially loadsthe individual Lookup Table entries. At the start of each mes-sage, the ACE stores the Lookup Table entry in the third posi-tion of the respective message block descriptor in the stack areaof RAM, as in the Single Message mode. The ACE transfersReceive or Transmit Data Words to (from) the circular buffer,starting at the location referenced by the Lookup Table pointer.
At the end of a valid (or, optionally, invalid) message, the valueof the Lookup Table entry updates to the next location after thelast address accessed for the current message. As a result,Data Words for the next message directed to the sameTx/Rx(/Bcst) subaddress will be accessed at the next contiguousblock of address locations within the circular buffer. As a rec-ommended option, the Lookup Table pointers may be pro-grammed to not update following an invalid receive (or broad-cast) message. This allows the 1553 bus controller to retry the
failed message, resulting in the valid (retried) data overwritingthe invalid data. This eliminates overhead for the PC hostprocessor. When the pointer reaches the lower boundary of thecircular buffer (located at 128, 256, . . . 8192-word boundaries inthe BU-65549 address space), the pointer moves to the topboundary of the circular buffer, as FIGURE 11 shows.
SUBADDRESS DOUBLE BUFFERING MODE
For receive (and broadcast) subaddresses, the BU-65549 RToffers a third memory management option, Subaddress DoubleBuffering. Subaddress double buffering provides a means ofensuring data consistency. FIGURE 12 illustrates the RTSubaddress Double Buffering scheme. Like the Single Messageand Circular Buffer modes, the Double Buffering mode may beselected on a subaddress basis by means of the SubaddressControl Word. The purpose of the Double Buffering mode is toprovide the host processor with a convenient means of access-ing the most recent, valid data received to a given subaddress.This serves to ensure the highest possible degree of data sam-ple consistency by allocating two 32-bit Data Word blocks foreach individual receive (and/or broadcast) subaddress.
At a given point in time, one of the two blocks will be designatedas the “active” 1553 data block while the other will be designat-ed as the “inactive” block. The Data Words from the next receivemessage to that subaddress will be stored in the “active” block .Upon completion of the message, provided that the messagewas valid and Subaddress Double Buffering is enabled, the BU-65549 will automatically switch the “active” and “inactive” blocks
15 13 0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMANDWORD
CONFIGURATIONREGISTER #1
STACKPOINTERS
DESCRIPTORSTACK
CURRENTAREA B/A
DATA BLOCKS
DATABLOCK 1
DATA BLOCK 0
X..X 0 YYYYY
X..X 1 YYYYY
RECEIVE DOUBLEBUFFER ENABLE
SUBADDRESSCONTROL WORD
MSB
DATA BLOCK POINTER
LOOK-UPTABLES
FIGURE 12. RT MEMORY MANAGEMENT: SUBADDRESS DOUBLE BUFFERING MODE
22
for the respective subaddress. The ACE accomplishes this bytoggling bit 5 of the subaddress's Lookup Table Pointer andrewriting the pointer. As a result, the most recent valid block ofreceived Data Words will always be readily accessible to thehost processor.
As a means of ensuring data sample consistency, the hostprocessor is able to reliably access the most recent valid,received Data Word block by performing the following sequence:
(1) Disable the double buffering for the respectivesubaddress by the Subaddress Control Word. Thatis, temporarily switch the subaddress's memory man-agement scheme to the Single Message mode.
(2) Read the current value of the receive (or broad-cast) subaddress's Lookup Table pointer. This pointsto the current “active” data word block. By invertingbit 5 of this pointer value, it is possible to locate thestart of the “inactive” data word block. This block willcontain the data words received during the mostrecent valid message to the subaddress.
(3) Read out the words from the “inactive” (mostrecent) Data Word Block.
(4) Re-enable the Double Buffering mode for therespective subaddress by the Subaddress ControlWord.
RT INTERRUPTS
As in BC mode, the BU-65549 RT provides a number of mask-able interrupt conditions. RT interrupt conditions include End of(every) Message, Message Error, Selected Subaddress(Subaddress Control Word) Interrupt, Circular Buffer Rollover,Selected Mode Code Interrupt, and Descriptor Stack Rollover.
DESCRIPTOR STACK
At the beginning and end of each message, the BU-65549 RTupdates a 4-word message descriptor in the active area stack.The RT stack size is programmable, with choices of 256, 512,1024, and 2048 words. FIGURES 10, 11, and 12 show the fourwords: Block Status Word, Time Tag Word, Data Block Pointer,and the 1553 received Command Word. The RT Block StatusWord includes indications of message in-progress or messagecomplete, bus channel, RT-to-RT transfer and RT-to-RT transfererrors, message format error, loop test (self-test) failure, circularbuffer rollover, illegal command, and other error conditions.TABLE 23 shows the bit mapping of the RT Block Status Word.
As in BC mode, the Time Tag Word stores the current contentsof the BU-65549's read/writable Time Tag Register. The resolu-
tion of the Time Tag Register is programmable from among 2, 4,8, 16, 32, and 64 µs/LSB. Also, incrementing of the Time Tagcounter may be from an external clock source or via softwarecommand. For the BU-65549M2 card, there are separate, andindependent time tag registers for the two bus channels.
The ACE stores the contents of the accessed lookup table loca-tion for the current message, indicating the starting location ofthe data word block, as the data block pointer. This serves as aconvenience in locating stored message data blocks. The thirdword will contain the data block pointer, or optionally mode codedata. The ACE stores the full 16-bit 1553 Command Word in thefourth location of the RT message descriptor.
RT COMMAND ILLEGALIZATION
The BU-65549 provides an internal mechanism for RT commandillegalization (setting of the Message Error bit in the statusresponse). In addition, there is a means for allowing the settingof the Busy Status Word bit to be only for a programmed subsetof the transmit/receive/broadcast subaddresses.
The illegalization scheme uses a 256-word area in the BU-65549's address space. The BU-65549's illegalization schemeprovides maximum flexibility, allowing any subset of the 4096possible combinations of broadcast/own address, bit, sub-address, and word count/mode code to be illegalized.
PROGRAMMABLE BUSY
The BU-65549 RT provides a software controllable means forsetting the busy status word bit as a function of subaddress. Bymeans of a Busy lookup table in the BU-65549 address space, itis possible to set the Busy bit based on command broadcast/ownaddress, bit, and subaddress. Another programmableoption allows received Data Words to be either stored or notstored for receive messages when the Busy bit is set.
OTHER RT FUNCTIONS
The BU-65549 allows each channel’s programmed RT Addressto be read by the host processor. Also, there are options for theRT FLAG Status Word bit to be set under software control and/orautomatically following a failure of the loopback self-test. Othersoftware controllable RT options include software programmableRT Status and RT BIT words, automatic clearing of the ServiceRequest Status Word bit following a Transmit Vector Word modecommand, capabilities to clear and/or load the Time TagRegister following receipt of Synchronize mode commands,options regarding Data Word transfers for the Busy and/orMessage Error (Illegal) Status Word bits, and for handling of1553A and reserved mode codes.
R/T
R/T
23
MONITOR (MT) ARCHITECTURE
The BU-65549 provides three bus monitor (MT) modes:
(1) A Word Monitor mode.
(2) A Selective Message Monitor mode.
(3) A Simultaneous RT / Selective Message Monitor mode.
The strong recommendation for new applications is the use ofthe Selective Message Monitor, rather than the Word Monitor.Besides providing monitor filtering based on RT Address, bit, and Subaddress, the Message Monitor eliminates the needto determine the start and end of messages by software. Suchsoftware tends to entail a high degree of CPU overhead.
WORD MONITOR
In the Word Monitor mode, the BU-65549 monitors both 1553buses. After initializing the Word Monitor and putting it on-linethe BU-65549 stores all Command, Status, and Data Wordsreceived from both buses. For each word received from eitherbus, the BU-65549 stores a pair of words in RAM. The first wordis the 16 bits of data from the received word. The second wordis the Monitor Identification (ID), or “Tag” word. The ID Wordcontains information relating to bus channel, sync type, wordvalidity, and inter-word time gaps. The BU-65549 stores dataand ID words in a circular buffer in the shared RAM addressspace. TABLE 24 shows the bit mapping for the Monitor IDword. The starting location for storage should be loaded to loca-tion 0100h. Subsequently, this value is overwritten as the mon-itor fills the available RAM and rolls over to 0000h.
MONITOR TRIGGER WORD
There is a Trigger Word Register that provides additional flexi-bility for the Word Monitor mode. The BU-65549 stores thevalue of the 16-bit Trigger Word in the MT Trigger WordRegister. The contents of this register represent the value of theTrigger Command Word. The BU-65549 has programmableoptions to start or stop the Word Monitor, and/or to issue aninterrupt request following receipt of the Trigger command wordfrom the 1553 bus.
SELECTIVE MESSAGE MONITOR MODE
The BU-65549 Selective Message Monitor provides features togreatly reduce the software and processing burden of the hostCPU. The Selective Message Monitor implements monitoring ofmessages from a dual 1553 bus, with the monitor filtering basedon the RT Address, bit, and subaddress fields of received1553 command words. The Selective Message Monitor modegreatly simplifies the host processor software by distinguishing
R/T
R/T
between command and status words. The Selective MessageMonitor maintains two stacks in the BU-65549 RAM: aCommand Stack and a Data Stack.
SIMULTANEOUS RT/MESSAGE MONITOR MODE
The Selective Message Monitor may function as a purely pas-sive monitor or may be programmed to function as a simultane-ous RT/Monitor. The RT/Monitor mode provides completeRemote Terminal (RT) operation for the BU-65549's pro-grammed RT address, and bus monitor capability for the other30 non-broadcast RT addresses. This allows the BU-65549 tosimultaneously operate as a full function RT and “snoop” on allor a subset of the bus activity involving the other RTs on a bus.This type of operation is sometimes needed to implement abackup bus controller. The combined RT/Selective Monitormaintains three stack areas in the BU-65549 address space: anRT Command Stack, a Monitor Command Stack, and a MonitorData Stack. The pointers for the various stacks have fixed loca-tions in the BU-65549 address space.
SELECTIVE MESSAGE MONITOR MEMORY ORGANIZA-TION
TABLE 31 illustrates a typical memory map for the ACE in theSelective Message Monitor mode. This mode of operationdefines several fixed locations in the RAM. These locations allo-cate in a manner that is compatible with the combinedRT/Selective Message Monitor mode. The fixed locations in thememory map consist of two Monitor Command Stack Pointers(location 102H and 106H), two Monitor Data Stack Pointers(locations 103H and 107H), and a Selective Message MonitorLookup Table (0280-02FFH). The Monitor lookup table providesmessage filtering based on RT Address, , and subaddress.TABLE 31 assumes a Monitor Command Stack size of 1Kwords, and a Monitor Data Stack size of 2K words.
FIGURE 13 illustrates the Selective Message Monitor operation.Upon receipt of a valid Command Word, the BU-65549 will ref-erence the Selective Monitor Lookup Table (a fixed block ofaddresses) to check for the selection status (disabled/enabled)of the current command. If disabled, the BU-65549 will ignore(and not store) the current message; if enabled, the BU-65549will create an entry in the Monitor Command Stack at theaddress location referenced by the Monitor Command StackPointer.
Similar to RT mode, the BU-65549 stores a Block Status Word,16-bit Time Tag Word, and Data Block Pointer in the MessageDescriptor, along with the received 1553 Command Word fol-lowing reception of a valid, selected Command Word. The BU-65549 writes the Block Status and Time Tag Words at both thestart and end of the message. The Monitor Block Status Wordcontains indications of message in-progress or message com-plete, bus channel, Monitor Data Stack Rollover, RT-to-RT
R/T
24
transfer and RT-to-RT transfer errors, message format error, andother error conditions. TABLE 25 shows the Message MonitorBlock Status Word. The Data Block Pointer references the firstword stored in the Monitor Data Stack (the first word followingthe command word) for the current message. The BU-65549 willthen proceed to store the subsequent words from the message(possible second command word, data word(s), status word(s))into consecutive locations in the Monitor Data Stack.
Note: If the Monitor lookup table is set to capture only a subsetof subaddresses for an RT, there may be confusing resultswhere an array of command and data words have been rejectedand the following status word has the bit pattern of a valid com-mand word.
The size of the Monitor Command Stack is programmable to256, 1K, 4K, or 16K words. The Monitor Data Stack size is pro-grammable to 512, 1K, 2K, 4K, 8K, 16K, 32K, or 64K words.
Monitor interrupts may be enabled for Monitor Command StackRollover, Monitor Data Stack Rollover, and/or End-of-Messageconditions. In addition, in the Word Monitor mode there may bean interrupt enabled for a Monitor Trigger condition
Monitor Command Stack Pointer B (fixed location)
Monitor Command Stack B0800-0BFF
Monitor Command Stack A0400-07FF
Available for more or larger stacks
Not Used
2000-FFFF
0300-03FF
Monitor Data Stack A
Selective Monitor Lookup Table (fixed area)
1000-1FFF
0280-02FF
Not Used
Registers
0C00-0FFF
0260-027F
Monitor Data Stack Pointer B (fixed location)0107
Not Used0104-0105
Monitor Data Stack Pointer A (fixed location)0103
Monitor Command Stack Pointer A (fixed location)0102
Not Used0000-0101
DESCRIPTIONADDRESS
(HEX)
0106
TABLE 31. TYPICAL SELECTIVE MESSAGE MONITOR MEMORY MAP (SHOWN FOR 64K RAM)
25
15 13 0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMANDWORD
CONFIGURATIONREGISTER #1
MONITOR COMMANDSTACK POINTERS
MONITORCOMMAND STACKS
CURRENTAREA B/A
MONITOR DATASTACKS
MONITOR DATABLOCK #N + 1
MONITOR DATABLOCK #N
CURRENTCOMMAND WORD
MONITOR DATASTACK POINTERS
IF THIS BIT IS "0" (NOT SELECTED)NO WORDS ARE STORED IN EITHERTHE COMMAND STACK OR DATA STACK.IN ADDITION, THE COMMAND AND DATASTACK POINTERS WILL NOT BE UPDATED.
NOTE
SELECTIVE MONITORLOOKUP TABLES
SELECTIVE MONITORENABLE
OFFSET BASED ONRTA4-RTA0, T/R, SA4
16 BITS IN EACH WORD MASKSA0-3 COMBINATIONS
FIGURE 13. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
26
BU-61688MINI-ACE
DATABUS
Z0
55 Ω
55 Ω
TX/RX
TX/RX
1
2
3
4
8
(1:2.5)
B-322611.6 VPP
28 VPP
1 FT MAX
Z0
1
2
3
5
7
(1:1.79)
B-322611.6 VPP 20 VPP
18
34
(1:1.14)
BUS-25679B-2203
M21038/27-02
0.75 Z0
0.75 Z0
LONG STUB(TRANSFORMER
COUPLED)
20 FT MAX
28 VPP
SHORT STUB(DIRECT COUPLED)
OR
BU-65549
NOTE: Z 0 = 70 TO 85 OHMS
FIGURE 14. BU-65549 INTERFACE TO A MIL-STD-1553 BUS (ONE CHANNEL SHOWN)
INTERFACE TO MIL-STD-1553 BUS
FIGURE 14 illustrates the interface from the BU-65549 to a 1553bus for either transformer (long stub) or direct (short stub) cou-pling, plus the peak-to-peak voltage levels that appear at variouspoints (when transmitting).
Jumpers allow for either transformer or direct coupling to beselected.
Both coupling configurations require the use of an isolationtransformer that interfaces directly to the card. For the trans-former (long stub) coupling configuration, a second transformer,referred to as a coupling transformer, is required. In accordancewith MIL-STD-1553B, the turns ratio of the coupling transformer is 1.0 to 1.4.
Alternative suitable termination methods may be used if two ter-minals are directly connected.
27
FIGURE 15. MECHANICAL OUTLINE (WITH JUMPER LOCATIONS)
Drawing not to scale. Dimensions in inches (mm).
1553CHAN
1-A
1553CHAN
1-B
1553CHAN
2-A
1553CHAN
2-B
0.325(8.255)
1.605(40.767)
2.169(55.09)
0.593(15.06)
2.508(63.703)
6.875(172.72)
4.200(106.68)
CHANNEL 1-A COUPLING JUMPERSP4A1
P4B16
P5A1
P5B
16
CHANNEL 1-B COUPLING JUMPERS
CHANNEL 2-B COUPLING JUMPERS
CHANNEL 2-A COUPLING JUMPERS
INSTALLING JUMPERS
Jumper blocks are used to select between transformer and direct coupling configurations as follows:
Direct coupling: install jumpers from pin 9 to 10 and pin 15 to 16.
Transformer coupling: install jumpers from 11 to 12 and pin 13 to 14.
P4A: Channel 1-A Coupling option. Install jumpersfor coupling configuration as described above.
P4B: Channel 1-B Coupling option. Install jumpersin same locations as on P4A.
P5A: Channel 2-A Coupling option. Install jumpersin same locations as on P4A.
P5B: Channel 2-B Coupling option. Install jumpersin same locations as on P4A.
28
CE MARK CERTIFICATION
This product carries the CE MARK signifying conformance to the requirements of COUNCIL DIRECTIVE 89/336 EEC. The supporting test (report) is on file at DDC, New York, USA and is available for on-site review.
29
ORDERING INFORMATION
BU-65549MX-300
Temperature Range:3 = 0 to 55 °C
Number of Channels:1 = One Dual Redundant 1553 Channel2 = Two Dual Redundant 1553 Channels
Included Software:• BUS-69082 32-bit “C” Library (Win 95)• BUS-69083 32-bit “C” Library (Win NT)• BUS-69084 32-bit Menu (Win 95)• BUS-69085 32-bit Menu (Win NT)
30
NOTES
31
NOTES
32
C-05/00-0 PRINTED IN THE U.S.A.
DATA DEVICE CORPORATIONREGISTERED TO ISO 9001
FILE NO. A5976
RE
G ISTERED FIRM
®U
The information in this data sheet is believed to be accurate; however, no responsibility isassumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.Specifications are subject to change without notice.
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