building a virtual computer - city...

Building a Virtual Computer From Gates to Operating System

Student Researcher: Elisa Elshamy

Faculty Mentor: Dr. Victoria Gitman

A modern computer can carry out a plethora of multifaceted computations. Realizing this, one would be led to believe that computer hardware is built to be as complicated as machinery can get. Instead, it turns out that the structure of computer hardware is really a sophisticated concatenation of elementary Boolean gates. In this project, we used the Hardware Description Language (HDL) together with hardware simulator software to virtually build the components of a simple computer’s hardware platform. Using the single fundamental building block NAND gate, we started out by building chips (concatenations of Boolean gates) to carry out the most basic logic functions such as AND, OR and NOT. From these chips, we in turn built the ALU, RAM, CPU and put it all together into a functioning hardware platform. Since the bare bones of computing come down to functions of binary patterns, we implemented the fundamental set of such functions in the ALU. The first advanced function we built was multi/bit binary addition. Next, the Arithmetic Logic Unit (ALU) brought together the elementary Boolean logic gates along with the addition function to become the chip that performs all basic binary functions required for program execution. To implement the storage and processing of data, the computer hardware requires an inbuilt clock. It is realized by an oscillator that alternates between two outputs, 0 and 1 to signal tick and tock. The synchronization and time delay provided by the clock is exploited for data storage and manipulation by the fundamental Data/Flip/Flop (DFF) gate that implements the time/based behavior out(t) = in(t/1), where output is the input from the previous time unit. We used the DFF gate to build a basic unit of data storage that ‘remembers’ a bit of information by constantly cycling its value between input and output until instructed to modify what it stores. These basic chips were glued together to form registers of which the Random Access Memory (RAM) is composed. The master behind computer operation is the Central Processing Unit (CPU). The CPU, which is composed of the ALU, several registers and a program counter chip designed to keep track of program execution, synchronizes computer functionality by decoding, executing, and fetching program instructions. The instructions the CPU receives from the instruction memory or ROM (which is identical to the RAM memory except it is used to store instructions and not data) are decoded to determine what actions the ALU will take to execute each instruction, and where in the RAM memory the ALU’s output will be stored. Upon completion of the CPU, we now have a fully functional computer hardware. We are continuing the project to implement the software end of the computer by writing the assembler, virtual machine, compiler, and operating system programs.

Abstract

von Neumann ArchitectureThe stored program concept

MemoryMemoryMemoryMemory(data + (data + (data + (data +

instructions)instructions)instructions)instructions)

CPUCPUCPUCPUInputInputInputInput

OutputOutputOutputOutput

Arithmetic LogicArithmetic LogicArithmetic LogicArithmetic LogicUnit (ALU)Unit (ALU)Unit (ALU)Unit (ALU)

RegistersRegistersRegistersRegisters

ControlControlControlControl

Depicted left is the von Neumann architecture. The von Neumann machine is a conceptual blueprint for building many computers today and is best known for using the stored program concept. The stored program concept is a key element

MemoryMemoryMemoryMemory – A continuous array of registers where each cell has a unique address�Data Memory – Read and written to by programs, assist with program execution�Instruction Memory – Where high-level and machine language programs that decode high-level instructions are storedCPUCPUCPUCPU – Central Processing Unit, executes instructions of current program�Arithmetic Logic Unit (ALU) – Performs low-level arithmetic and logic operations�Registers – Small amount of local memory for quick calculating�Control Unit – Decodes, executes and fetches instructions Input/OutputInput/OutputInput/OutputInput/Output – Screens, keyboards, mice, printers, scanners, network interface cards, and other peripheral

John von Neumann

12/28/1903 – 2/8/1957

to many computer models, abstract and practical alike. Instead of embedding programs into hardware, programs are stored in the computers memory much like software. This allows for reusability with the hardware and the versatility of loading different programs to instruct the computer to perform different tasks. The von Neumann architecture associated with our platform separates instruction from data memory. Instruction memory holds the program’s code and data memory is manipulated as needed to assist

with program execution.

Building Blocks

Logic diagram for NAND gate011

101

110

100

outBA

out

Boolean logic for NAND gateHardware Simulator

�We used the NAND gate as a building block to build all the other gates (AND, OR, NOT, XOR, etc) �Every gate, can be built from a simple NAND gate �Gates were built virtually, no usage of soldering irons or wires, but a hardware simulator. �The hardware simulator is a software tool that can make a model of any chip as specified by an HDL (Hardware Description Language) program. �In the real world, hardware designers use simulators much like this one to completely plan chip architecture and perform a series of rigorous testing before any production takes place.

Elementary Logic Gates

01

10

outin

111

001

010

000

outBA

Boolean logic for AND gate

ANDANDANDAND outA

B

Logic diagram for AND gate

CHIP And {

IN a, b;

OUT out;

PARTS:

Nand(a=a, b=b, out=nandOut);

Not(in=nandOut, out=out);

}

AND gate HDL program

Boolean logic for NOT gate

NOTNOTNOTNOT outin

Logic diagram for NOT gate

CHIP Not {

IN in;

OUT out;

PARTS:

Nand(a=in, b=in, out=out);

}

NOT gate HDL program

Boolean logic for OR gateLogic diagram for OR gate

CHIP Or {

IN a, b;

OUT out;

PARTS:

Not(in=a, out=aOut);

Not(in=b, out=bOut);

Nand(a=aOut, b=bOut, out=out);

}

OR gate HDL program

111

101

110

000

outBA

OROROROR outA

B

Multiplexor GateThe root of conditional logic

B1

A0

outsel

MUXMUXMUXMUX out

A

B

sel

Logic diagram for MUX gate

Conditional logic for MUX gate

outA00

B10

C01

11 D

sel[0]sel[1]

Conditional logic for 47way MUX gate

4444$$$$waywaywaywayMUXMUXMUXMUX

out

A

B

sel[1]Logic diagram for 47way MUX gate

C

D

sel[0]

CHIP Mux {

IN a, b, sel;

OUT out;

PARTS:

Or(a=a, b=sel, out=out1);

Not(in=b, out=notB);

Nand(a=notB, b=sel, out=out2);

And(a=out1, b=out2, out=out);

}

MUX gate HDL program

The multiplexor gate uses the selector bit to decide which pin to output. We can think of the logic of the multiplexor gate as an conditional if statement. We later built more complicated models such as the 4-way multiplexor shown left. The inputs A, B, C, and D as well as the output are each 16-bit wide.

If sel == 0

out = A;

else

out = B;

Binary Addition2’s complement numbers and adder chips

4 3 2

The binary system is founded on base 2. If we are presented a binary string such as “10011”, we can convert it to its decimal equivalent as follows:10010 = 1*2 + 0*2 + 0*2 + 1*2 + 1*2 = 19

1 0

Binary AdditionBinary AdditionBinary AdditionBinary Addition

001+

1110

110

000

(LSB)(MSB)

3 + (74) = 71

74

3

(carry)We add a pair of binary numbers the same way we would its decimal representation. Starting from the right column (Least Significant Bits) and bringing the carry bit (0 or 1) to the next column until we reach the leftmost column (Most Significant

Bits).

2222’’’’s Complement for signed binary numberss Complement for signed binary numberss Complement for signed binary numberss Complement for signed binary numbers

100 /4

101 /33 011

110 /22 010

111 /11 001

0 000

Negative Numbers

Positive Numbers

2’s complement for a 37bit binary system

≠−

=

otherwise

xifxx

n

0

02

11062223

==−=−

HalfHalfHalfHalfAdderAdderAdderAdder

A

B

sum

carry

HalfHalfHalfHalfAdderAdderAdderAdder

A

BHalfHalfHalfHalfAdderAdderAdderAdder

C

sum

OROROROR carry

Half7Adder (left) & Full7Adder implementation (right)

To represent signed numbers, we split the bit space into two equal subsets. Addition of signed binary numbers is equivalent to its decimal representation.

Arithmetic Logic Unit (ALU)

x | y101010

x & y000000

y - x111000

x + y010000

!y100011

!x101100

f(x,y)=if no then out=

!out

if f then out=x+y else out=

x&y

if ny then y=!y

if zy then y=0

if nx then x=!x

if zx then x=0

out=nofnyzynxzx

These bits preset the x input

These bits preset the y input

Resulting ALU

function

ALUALUALUALUx

y

zr ng

out

zx nx zy ny f no

f(x.y)16bits

16bits

zr //True iff out=0ng //True iff out<0

ALU Logic Diagram ALU truth table showing some of the possible logic functions that can be computed based on the first six bits. The complete 167bit ALU table would show sixty7four functions

Using careful design, a 16-bit ALU can compute functions. Which function the ALU “decides” to output is based on a combination of six bits called control bits. The ALU is the chip that is constructed to carry all the primitive operations desired in the computer architecture and at the heart of its logic.

6426

=

out(t) = in(t-1)

Clocks and Flip-Flops

A computer clock is much like a see7saw, alternating back and forth between signals (0 and 1)

0000

1111

Computers use a master clock to represent the passage of time. This clock is usually implemented from an oscillating device that delivers an infinite alternating train of signals (0 and 1, low and high, tick and tock). A computer clock cycle is defined to start at the beginning of a tick and conclude at the end of the subsequent tock.

Clock CyclesClock CyclesClock CyclesClock Cycles

To build chips which could maintain state, it was essential to have a building block with sequential properties. The data flip-flop, or DFF, takes the current clock’s signal as input to implement time-based behavior. In other words, the DFF takes advantage the clock and uses it to control the output of data. Memory chips built on top of DFFs “remember” values by sending output back to the input pin and outputting it again until told by a control bit to accept a new value.

FlipFlipFlipFlip----FlopsFlopsFlopsFlops

DFFDFFDFFDFFoutin

Logic diagram of data flip7flop. At the end of each clock cycle, the DFF outputs the input value from the previous cycle.

From Registers to RAMmaintaining state with feedback loops

DFFDFFDFFDFFMUXMUXMUXMUX

in

load

out

Logic diagram of 17bit data register

if load(t-1) then out(t) = in(t-1)

else out(t) = out(t-1)

A DFF can only output its previous input, out(t) = in(t-1). A register on the other hand, can also output a previous output, out(t) = out(t-1) and thus maintain state. This is accomplished in sequential chips through the formation of feedback loops. A feedback loop occurs when the output can be fed back to the input pin of the chip. Sequential chips, such as DFFs have an inherent time delay due to the clock input and allow for the construction of memory devices, such as registers. A register stores values according to the control bit (load). If load is 1, the register reads the value from in and stores it. If load is 0, it keeps the current value.

Registers and Feedback LoopsRegisters and Feedback LoopsRegisters and Feedback LoopsRegisters and Feedback Loops

BITBITBITBIT outin

load

outin

load

BITBITBITBIT BITBITBITBIT. . .. . .. . .. . .

(word)

in

(word)

load

address

(0 to n-1)

out

Register 0Register 0Register 0Register 0


Register nRegister nRegister nRegister n$$$$1111

RAMnRAMnRAMnRAMn

direct access direct access direct access direct access logiclogiclogiclogic

From single to multi7bit registers to Random Access Memory (RAM).

Random Access Memory (RAM)

(word)

in

(word)

load

address

(0 to n-1)

out




RAM8RAM8RAM8RAM8

direct access direct access direct access direct access logiclogiclogiclogic

RAM8RAM8RAM8RAM8

RAM8RAM8RAM8RAM8

RAM 64RAM 64RAM 64RAM 64

....

....

Depicted above is the gradual construction of RAM. The underlying architecture of RAM is nothing more than an array of registers.

RAM is an array of n w-bit registers. We describe the RAM’s specs in accordance to the number of registers n and the width of each register w. These components are referred to as the memory’s size and width respectively.

RAM storage and Retrieval of dataRAM storage and Retrieval of dataRAM storage and Retrieval of dataRAM storage and Retrieval of dataRead: To read a value from a given register mwithin the RAM, we must put m in the address input. The value in register m will be outputted to the RAM’s output pin.

Write: To write a value d to a given register m within the RAM, we must put m in the address input, d in the in input, and signal the load input. The RAM’s direct access logic will select the register m and use the load bit to enable it for data storage. In the next clock cycle, the value d will be committed to register m and the RAM’s output pin.

Designated Registersfor machine language instructions

Other than the instruction memory (ROM) and data memory (RAM), there is a set of registers in the processor’s region. This set of registers is handy when the processor is carrying out a list of instructions and must maneuver data and instructions at high speed.

A RegisterA RegisterA RegisterA Register D RegisterD RegisterD RegisterD Register M RegisterM RegisterM RegisterM Register

�Local to the processor�Value is the address of a register in RAM�Value may also represent the location of the next instruction that should be executed�Can also store data values and constants on the fly

�Local to the processor�Stores data values only for quick calculations and comparison testing of conditionals

�Not local to the processor�An actual memory location in RAM�Accessed by the value in the A register, in other words the value of the A register is the address of the M register’s location.

For example if we want

M[516] = 4:

@516 //A=516

M = 4 //M[516] = 4

For example if we want A = 100:

@100 //A=100

The proceeding instruction

decides how to use the A value

For example if we want

D=A=5:

@5 //A=5

D = A //D=A=5

A/C-Instructionsmachine language specification

AAAA----InstructionsInstructionsInstructionsInstructions

0 v v v 0 v v v 0 v v v 0 v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v

CCCC----InstructionsInstructionsInstructionsInstructions

1 1 1 a 1 1 1 a 1 1 1 a 1 1 1 a c1 c2 c3 c4c1 c2 c3 c4c1 c2 c3 c4c1 c2 c3 c4 d3 j1 j2 j3d3 j1 j2 j3d3 j1 j2 j3d3 j1 j2 j3

A machine language program is a series of coded instructions written for the computer to perform basic arithmetic and logic functions. The hardware specification and machine language syntax describe how these coded instructions are read. Since binary strings are cryptic to the human brain, assembly language was developed to make low-level programming feasible. Assembly language replaces codes such

as 1010 to symbols like add which are easier to understand and much more readable. Since program instructions are 16-bits wide

and addresses are specified by 15-bits, our computer platform separates operation code from address instructions. In order to distinguish between the two instructions, A-Instructions (address code) always have a most significant bit of 0 while C-Instructions (Computation Code) always have a most significant bit of 1.

�Sets the A register to a 15-bit value�Must be a non-negative decimal value�Uses of A-Instruction:

�Enter a constant on the fly�Specifies the location of data memory that should be manipulated by the subsequent C-Instruction �Specifies the location for the jump destination of the proceeding instruction

Value (v = 0 or 1)

c5 c6 d1 d2c5 c6 d1 d2c5 c6 d1 d2c5 c6 d1 d2

comp dest jump

�The C-Instruction is broken into three fields:�Comp – Tells the ALU which function to compute as predefined by the language specification�Dest – States which register(s) (A, D, or M) should store the computed value�Jump – Notifies the computer of which instruction to fetch next.

I/O Handlinginteracting with the screen and keyboard

Input/Output HandlingInput/Output HandlingInput/Output HandlingInput/Output HandlingOur computer can interact with two peripheral devices: a screen and a keyboard. The computer platform and these devices “talk” to each other via memory maps. Drawing pixels on the screen and listening to the keyboard is accomplished by writing to and reading from designated memory segments associated with the peripherals.

Simulation of the screen and keyboard used with our computer.

ScreenScreenScreenScreenOur computer uses a black-and-white screen with 256 rows of 512 pixels per row. The screen’s memory map begins at RAM address 16384 and every row is represented by a 32 16-bit word. To read or write to a pixel on the screen, the corresponding bit in the memory map must be read or written to (0=white, 1=black).

KeyboardKeyboardKeyboardKeyboardThe keyboard’s single-word memory map begins at RAM address 24576. Anytime a key is pressed it’s ASCII code appears in RAM[24576]. If no key is pressed, RAM[24576] holds the value 0.

Central Processing Unit (CPU)

Logical diagram of the CPU. It should be noted that this diagram is intended to give a brief overview and is missing detail such as the CPU’s control logic.

Central Processing UnitCentral Processing UnitCentral Processing UnitCentral Processing UnitThe CPU is designed to process instructions and is the core of computational logic. Underlying the CPU is the ALU, a set of registers, and control logic (i.e. Mux gates) all of which are implemented for assisting with fetchingand decoding instructions.

CPUCPUCPUCPU’’’’s Control Logics Control Logics Control Logics Control LogicInstruction Decoding – The 16-bit word in the CPU’s input pin can either represent an address or a compute instruction. The CPU decodes the instruction by breaking it into smaller fields.

Instruction Executing – After the instruction is broken into smaller fields, the CPU routes each part to it’s designated chip. For example, a part of the instruction gets sent to the ALU where it will determine which function to compute.

Next Instruction Fetching – As the CPU executes the current instruction, it must also determine which instruction to process next. This is accomplished as a function of the current instruction, the ALU output and the program counter.

The Computer Platform

Our computer platform as a logic diagram depicted above. Underlying the computer architecture are memory gates and the CPU chip. Below, a simple sketch of our computer interacting with peripheral devices.

Using all the gates and chips mentioned, we built a complete computer platform. This computer platform is a general-purpose machine, meaning that it is versatile and can switch from running one program to another. The significance of hardware design lies in its performance. Issues circumventing performance usually regard memory hierarchies, better access to I/O devices, instruction prefetching, and anything that can allow for faster computation. Our next steps will be to implement the software end of the computer by writing the assembler, virtual machine, compiler, and operating system programs.

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