burn-in & test socket workshop• caf is the acronym for conductive anodic filament. •...

Sponsored By The IEEE Computer SocietyTest Technology Technical Council

Burn-in & TestSocket Workshop

March 2 - 5, 2003Hilton Phoenix East / Mesa Hotel

Mesa, Arizona

tttc™

COPYRIGHT NOTICE• The papers in this publication comprise the proceedings of the 2003BiTS Workshop. They reflect the authors’ opinions and are reproduced aspresented , without change. Their inclusion in this publication does notconstitute an endorsement by the BiTS Workshop, the sponsors, or theInstitute of Electrical and Electronic Engineers, Inc.· There is NO copyright protection claimed by this publication. However,each presentation is the work of the authors and their respectivecompanies: as such, proper acknowledgement should be made to theappropriate source. Any questions regarding the use of any materialspresented should be directed to the author/s or their companies.

Burn-in & Test SocketWorkshop Technical Program

Session 3Tuesday 3/04/03 8:00AM

Socket And Board Development“CAF Effect: Challenges For Fine Pitch Burn-in Board Design”

K. W. Low - Intel CorporationAnthony Yeh Chiing Wong - Intel Corporation

Hon Lee Kon - Intel Corporation

“Automated Burn-in Socket Testing And Evaluation”Holger Hoppe - Infineon Technologies AG

“Thermal Testing Of Burn-In Sockets”James Forster - Texas Instruments

Savithri Subramanyam - Texas Instruments

CAF Effect:Challenges for Fine Pitch BIB Design

Anthony Wong Yeh ChiingKon Hon Lee

Low KWIntel Corporation

Anthony WongHL Kon/Low KW

BiTS 2003 2

Agenda• Overview• Background & Definition• CAF Formation• Factors Contributing to CAF• Fine Pitch BIB Design Rules• Best Known Test Methods & Issues.• Findings on PCB Materials Investigated• Technical Challenges.


BiTS 2003 3

Overview• Most Wireless & Networking products have continuously

shrunk in size due to consumer need for smaller, lighter,powerful, and portable devices.

• Over the years, technology companies have migrated theproduct pin pitch from 1.27mm to 0.5mm and less.

• Due to the tight pitch, fine pitch PCBs are moresusceptible to CAF failure which will cause the board tofail electrically in the field after some time in use.

1.27mm pitch0.5mm pitch


BiTS 2003 4

Background & Definition• CAF is the acronym for Conductive Anodic Filament.• Discovered by Bell Lab in 1976.• Further research has been performed by U of Maryland

(CALCE), Georgia Institute of Technology & SunMicrosystems.

• CAF is the growth of a copper-containing filament subsurfacealong the epoxy-glass interface,from anode to cathode.

Source:School of Materials Science & Engineering,GIT, Atlanta, GA


BiTS 2003 5

CAF Formation• Glass/epoxy bonds degrade – due to mechanical stress,

poor quality coupling agent, etc.• In a humid environment, water absorption occurs and creates

an aqueous medium that provides an electrochemicalpathway that facilitates the transport of corrosion products.

• Water acts as the electrolyte, copper circuitry as anode &cathode and operating voltage as driving potential.

• H+ (pH lower) and OH- (pH higher) creates a pH gradient.• Copper is passivated in region of pH 7 to 11 but becomes

corrosive at pH below 7 and potentials greater than 0.2V.• The anodic copper ions travel along the epoxy/fiber interface

attracted to the cathode.


BiTS 2003 6

Factors Contributing to CAF(1)• Material:• Several experiments have been done by PCB laminate

suppliers.• Most PCB Materials are only CAF Resistive


BiTS 2003 7

• Conductor Configuration:

• Voltage Gradient Effects: 3-8V/mils• Solder Flux/HASL(Hot Air Solder Leveling) Fluid

Composition:• Testing shows that polyglycols diffuse into epoxy during

soldering and increases moisture absorption by thesubstrate.

• Thermal Excursions:• Temperature , amount of polyglycol absorption• Will weaken the bonding between epoxy and glass fibers

due to difference in Coefficient of Thermal Expansion.

Factors Contributing to CAF(2)

Most susceptible Least susceptibleSource:School of Materials Science & Engineering, GIT, Atlanta, GA


BiTS 2003 8

• Cleaning:• Polyglycol residues from soldering process.• PCB Storage & Use: Ambient Humidity Effects.• Humidity threshold depends upon operating voltage and

temperature.• Moisture absorption can occur during any part of the PCB’s

lifetime.• PCB exposure to high humidity conditions during

transportation and storage can be problematic.

Factors Contributing to CAF(3)


BiTS 2003 9

Fine Pitch BIB Design Rules

X

Y

Z-Via or Pin hole size

11.7819.70.50mm

13.7619.70.50mm

15.410.225.60.65mm

15.7515.7531.50.80mm

14.42539.41.00mm

1733501.27mm

9.7615.70.40mm

Y – edge to edgedistance (mils)

Z – Holesize (mils)

X-Pitch(mils)

Product PinPitch

Fine Pitch PCB design distances

Reduction inedge to edgedistance

• Y is a critical dimension; closer it is, more susceptible to CAF• Hole/Via determined by drill bit size and positional accuracy.


BiTS 2003 10

Best Known Test Methods & Issues(1)• Two primary test methods for CAF testing:• Surface Insulation Resistance (SIR) Test method

introduced by Telcordia.– GR-78-CORE (IPC-TM-650, Section 2.6.14.1)– Test for surface electro migration and for characterizing

PCB laminates, soldering fluxes, solder masks &conformal coating.

– Test valid for a 25 year desired minimum product life.


BiTS 2003 11

Best Known Test Methods & Issues(2)• CAF Test method

– Sun Microsystems’ CAF Pattern (IPC in review)– Use to evaluate Alternate materials, design and PCB

manufacturing processes.– Valid for a 20 year desired minimum product life.– Four test patterns available to cover the four critical

PCB designs.• In Line Test Pattern A

10.8 mils29.2 mils34 milsA1

20.0 mils20 mils30 milsA3

25.5 mils14.5 mils27 milsA4

15.0 mils25 mils32 milsA2

Via edge to edgedistance

Drill hole sizePad sizeTestPattern


BiTS 2003 12

Best Known Test Methods & Issues(3)• Staggered Test Pattern B

10.4 mils32 mils37 milsB1

19.9 mils22.5 mils33 milsB3



Via edge to edgedistance


• Via to Plane Test Pattern C

• Trace to Trace Test Pattern D

5.25 mils14.5 mils25 milsC1




Via edge to antipadedge



BiTS 2003 13

Best Known Test Methods & Issues(4)• Sun Microsystems test pattern are used to test:

• Process• Drilled hole roughness• Hole clean process• Drilled hole to inner layer registration

• Material• Reinforcement type• Adhesion treatment used on electrical glass• Resin type• Copper tooth profile

• PCB design• Layer to layer dielectric thickness• Via edge to via edge spacing• Via location (In or out of line with the reinforcement weave direction)• Via edge to antipad clearance• Hole size and board thickness – drill wander

• Environmental• Temperature• Humidity• Voltage Bias


BiTS 2003 14

Best Known Test Methods & Issues(5)

9.7 – 17 mils1-3 years40-85%65-125C

1.3-4.6V

Typical BIRequirements

10V & 100VPower

65%Humility

10.4 – 25.5 milsDesign –via edge to edge20 yearsProduct life

85CTemperature

Sun CAF testProduct Pin Pitch

• SIR test is only valid for surface test.• Sun’s CAF testing setup does not represent today’s fine

pitch Burn-in board environment.• Does not comprehend the current expectation of 1-3 years

usage.• Slightly variation in the PCB via edge to edge design.


BiTS 2003 15

Findings on PCB Materials Investigated• Evaluation done on one material showed that no surfaceelectro migration occurred and it is CAF resistive.• Others investigated include non-woven Aramid enforcedmaterial.

Laminate VoidsLaminate Voids


BiTS 2003 16

• CAF test standardization• An approved industry standard.• Better CAF test data interpretation method.• Must be able to validate CAF free for product lifetime

durations (1-3 years).• New CAF free PCB material• Need to develop a CAF free PCB material for the future.• Should not have any side effect such as high CTE or high

water absorption.• New Manufacturing process• Stability of process and consistent PCB yield.• CAF test data sharing and collaboration.• PCB material - BT Resin, Polyimide, FR4, Thermount etc.• Lack of conclusive data from Laminate suppliers.• Accredited forum for technical consultation.

Technical Challenges

BiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003

Holger HoppePage 1 .

Automated Burn-in SocketAutomated Burn-in Socket

Testing and EvaluationTesting and Evaluation

Holger HoppeHolger Hoppe

Infineon Technologies AGInfineon Technologies AG

[email protected]@infineon.com



A g e n d aA g e n d aRequirements for Burn-in sockets

Release of Burn-in sockets

Burn-in process simulation

Conclusions



IntroductionIntroduction

Burn-in sockets: more complicated than obvious in order to havea stable and reliable burn-in process

Burn-in sockets in memory mass production: very cost intensive

Life time expectation: > 2 years respectively > 600 burn-in cycles

Burn-in cycle:

loading (opening socket, contacting, closing socket) temperature cycling (room temp high temp room temp) unloading (opening, unloading, closing).

Better to know burn-in socket performance before big volumeBetter to know burn-in socket performance before big volumeorders than after 1 year production experience.orders than after 1 year production experience.



Requirements for burn-in socketsRequirements for burn-in sockets

Electrical demandGood (low and stable resistance) and reliable contact of theDUT (device under test) to the test and burn-in equipmentfor proper electrical function and ageing process in the burn-in systems

Mechanical demandStability (springs, contact force) for long term use

Good device guidance during load (drop off) for massproduction



ObjectiveEvaluate electrical and mechanical performance of new burn-insockets in the lab

Approaching real burn-in conditions: to simulate all processesdone with burn-in sockets in real production in short time

Thermal stress with electrical function: Burn-in simulation

Mechanical stress + tests : Loader/Unloader simulation

Also possible: Ageing evaluation of used burn-in sockets aftera few hundreds runs in production (in comparison with anunused socket of same type)

Evaluation and release of burn-in socketsEvaluation and release of burn-in sockets



General featuresFully automated system running LabView software(mechanical control, heating control, measurement control)

Loader / Unloader function with industrial robot

Heating / Cooling ramp freely programmable

Device exchange after each cycle, freely programmable

Simultaneously 4 (different) sockets testable

Engineering field for further investigations andLoader/Unloader simulation

Highly flexible system

Fully Automated Burn-In Socket Tester (FABIST) Fully Automated Burn-In Socket Tester (FABIST) II



General features (cont.)

5 axis robot (Mitsubishi) for automatic cycles (load / unload/ open+close chamber / engineering), accuracy 0.02mm2 x 6 Jedec trays or waffle pack for >= 1200 device (300cycles)Universal presizerMax. socket size 50x50mmTemperature range: RT - 150°C (+/- 1°)Temperature ramp: >=10 K / min (up / down) freelyprogrammable = approx. 7 days for 300 cylcesNI - Industrial controller (PC-based)Keithley 22 bit Multimeter with 4 x 32 channels

Fully Automated Burn-In Socket Tester Fully Automated Burn-In Socket Tester IIII



Fully Automated Burn-In Socket Tester Fully Automated Burn-In Socket Tester IIIIII

Overview I

5-axis-robot



Fully Automated Burn-In Socket Tester Fully Automated Burn-In Socket Tester IVIV

Overview II

Temperature Chamber



Minimum 300 Burn-in cycles (approx. 1 year use)

Load Device

Measure contact resistance [Rc]

Heat up to burn-in temperature

Measure Rc

Cool down

Measure Rc

Unload Device

Restart

Optical inspection of contact tips and solder balls

Burn-in Simulation Burn-in Simulation II



Burn-in Simulation Burn-in Simulation IIII

Contact resistance: supplier “A”

Contact resistance: supplier “B”



Burn-in Simulation Burn-in Simulation IIIIII

Contact resistance: supplier “C”

* Plating: Gold

* Contact shape: Sharp

Contact resistance: supplier “D”

* Plating: Gold




Burn-in Simulation Burn-in Simulation IVIV

Contact resistance: supplier “F”

* Plating: Rhodium

* Contact shape: Standard

Contact resistance: supplier “E”

* Plating: NiB




Mechanical Reliability10.000 cover actuation cycles

without device or with one device or with device exchange

with / without Rc measurement

Socket actuation force by way chartSocket actuation force by way chart

Loader/Unloader simulationdevice shift test: X-/ Y-directiondevice shift test: X-/ Y-direction maximum allowed shift

device rotation test maximum allowed angel

device drop height optimum

Loader/Unloader Simulation Loader/Unloader Simulation II



Loader/Unloader Simulation Loader/Unloader Simulation IIII

Automated device X-/Y-shift test starting in the center of the socket @ (0;0)

short circuit device:

align in the presizer

load device with growing shift

measure RC of all 4 corner pins [Open/Close?]

unload and back to presizer

step-by-step shift to all 4 corners

resolution 0.05 mm; min +/-0.5mm = matrix 21 x 21

repetition with varying angles for device rotation test



Loader/Unloader Simulation Loader/Unloader Simulation IIIIII

Spiral for X-/Y-Shift

Possible Results for X-/Y-Shift



Loader/Unloader Simulation Loader/Unloader Simulation IVIV

Engineering field with

force sensor

Force sensor block above TSOP66



Force by way chart: supplier 1

* stroke 2.1 mm

* actuation force max 13.9 N

Loader/Unloader Simulation Loader/Unloader Simulation VV


* stroke 2.1 mm





* stroke 2.1 mm

* actuation force max 15,5 N@ 2.1mm

Loader/Unloader Simulation Loader/Unloader Simulation VIVI



Loader/Unloader Simulation Loader/Unloader Simulation VIIVII


* stroke 3.5 mm


Force by way chart: supplier 5* stroke 3.5 mm

* actuation force 19.6N / max 26.46N



ConclusionsConclusions

Simulations approach certain burn-in process conditions

Fast way to evaluate and release burn-in sockets

Better results for socket life time estimation

Better purchasing decision and recommendation

Better burn-in socket development together with socket suppliers -

- fast customer feedback

Fast test of new contact types, plating etc.

Direct comparison of different sockets / mechanical principles /

contacts / platings etc.



Investigation of behavior of Green Packages (TSOP and FBGA) in

conventional burn-in sockets

Investigation of new plating types (anti-sticking)

Investigation of vibration stability of contacts

Installation of simple tester - equipment in order to apply real

memory devices

OutlookOutlook

Thank you !Thank you !

Thermal Testing of Burn-In Sockets

James ForsterSavithri Subramanyam

Texas Instruments,Sensors & Controls, Attleboro, MA

2003 Burn-in Test Socket Workshop - March 2-5, 2003Hilton Phoenix East/Mesa Hotel

Mesa, Arizona

Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 2

Outline

• Brief introduction of the problem

• Definition of thermal resistance

• Theoretical and experimentaltechniques to evaluateperformance

• Examples of some experimentalresults


Thermal Difficulties

From paper by Mark Miller titled:Burn-in & Test System for Athlon Microprocessors : Hybrid Burn-in.BiTS Conference Session 5, 2001

Remember this image from 2001?


Computers and PowerNot a New problem

Jan 1946 - ENIAC18,000 electron tubes233 sq. metres140 kW30 Tons

Jan 2000 - Sony8.8 million transistors0.15 sq. metres40W7 lb.


The Problem

• As processor speed increases powerincreases

• Packages dissipate more power today – willdissipate more power tomorrow

• For burn-in socket suppliers - heatgenerated during burn-in of high powerpackages can lead to thermal runawaycausing damage the socket, the board andpotentially the oven or system


Some Types of Packages

Ceramic LGA with heat spreader

Ceramic LGA with heat spreader

Ceramic PGA with heat spreader

Ceramic LGA NO heat spreader


Types of Socket

Socket Type:• Open top• Clamshell

Board Mount:• Through hole• Compression

Mount


Types Of SocketOpen Top

No Integral Heat Sink With Integral Heat Sink


Types Of SocketClamshell With Integral Heat Sink

Clamshell for LGACompression Mount

Clamshell for PGAThru-hole


Thermal Difficulties

• Thermal runawayduring burn-in cancause catastrophicfailure.

• Defective sockets canbe difficult to remove.

• Reduced burn-incapacity.


Burn-in• Historically

Systems were “ovens” used to heat thedevices with appropriate controls and systemsfor generating test patterns

• Today SystemsOven is an environmental chamberHeat generated by device under testSystem controls temperature of individualdevices on a board to reduce temperaturevariability


Burn-inConventional System - Passive Thermal Control

• Indirect heating from air - socket is “Passive”• As air travels through the oven the “ambient”

temperature increases• Device in socket 1 experiences different burn-in

conditions than devices in sockets 2 or 3

90°c80°c 85°c

Socket 1 Socket 2 Socket 3

AIR FLOW


Burn-inNew System - Active Thermal Control

• Direct heating/cooling of each socket.• Each socket/device has individual

temperature monitoring and “Active ThermalControl” to maintain specific temperature.

• Cooling/heating of each socket controlled byindividual fans or heaters for each socket.

• Temperature uniformity +/- 5 deg.C


Burn-inActive Thermal Control - MCC

Cool Air Duct

Burn-in Board

Burn-in Socket

Fan

V(Socket tray)

V(Fan tray)

MCC HPB-3 System


Burn-in Active Thermal Control - Unisys System

Unisys STS 3000

Thermal Button whichinterfaces with the package

From: A Large Capacity and High-Performance Burn-Inand Test System for High-Power Dissipating ComponentsBy Dr. Jerry Tustaniwskyj et al, BiTS Workshop 2002


Heat Transfer MechanismsCeramic Lidded Package

ConductionThrough heat sink

ConductionThrough silicon

Interface material –conduction/convection

ConductionThrough lid CuW, Al,AlSiC or ?

InterfacePackage to heat sinkconduction/convection

ConvectionHeat sink to air


Thermal Issues - Analysis

Analytical/Computational CapabilitiesFEA – Finite Element AnalysisCFD – Computational Fluid Dynamics

ExperimentalWind TunnelThermal Imaging using infra-red Camera


Thermal Issues – Heat Transfer

Conduction –Through silicon to surface of package.Well understoodPhysical constant

Convection –From heat sink surface to air.Less understoodDependent on many variables.

Temperature.Surface finish.Local flow velocity


Thermal Issues – Heat Transfer

Interface ResistanceHeat transfer between mating surfaces.Least understood – most variable. - Chip to thermal interface material - Thermal interface material to heat spreader/lid - Package to heat sink - Heat sink to air


Thermal Resistance - θθθθjaThermal resistance is defined by θθθθja(Theta j-a). Where

θθθθja = Tjunction - Tambient

Power– T(Junction) - Temperature of the device,

measured by an “on-chip” sensor– T(Ambient) - Temperature of the ambient

air.– Power - Power the package is

dissipating.

T(Junction) Temp of Die

T(Ambient) Temp of air


Thermal Testing Standards - EIA /JEDEC

Test methods for determination of θθθθja and otherbasic thermal characteristics:

EIA/JEDEC: (Electronic Industries Association Joint Electron Device Engineering Council)

JESD51: Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device)

JESD51-4: Thermal Test Chip Guidelines (Wire-Bond-Type-Chip)JESD51-6: Integrated Circuit Thermal Test Method Environmental

Conditions – Forced Convention (Moving Air)JESD51-8: Integrated Circuit Thermal test method Environmental

Conditions – Junction-to-BoardSee: http://www.thermengr.com/tea041.html

http://www.jedec.org/


Thermal Testing Standards- SEMI

Test methods for determination of θθθθja and otherbasic thermal characteristics.

SEMI (Semiconductor Equipment and Materials International.):G-30-88: Test Method for Junction-to-Case Thermal Resistance

measurement for Ceramic packagesG32-094: Guideline for Unencapsulated Thermal Test Chip Design

G42-0996: Specification for Thermal Test Board Standardization for Junction-to-ambient thermal resistance of Semi-Conductor

PackageG38-0996: Test Method for Still- and Forced-Air Junction-to-ambient.

See: http://www.thermengr.com/tea041.htmlhttp://www.semi.org/PUBS/SEMIPUBS.NSF/92796f5466497e4

0882565f6000d07af?OpenView


Experimental Tools– Wind Tunnel

Provides a stable, controlled, repeatableenvironment for testing and comparison ofsockets and systems.• Includes flow straightener• Turbulence dampers• Hot wire anemometer• Flow control

0 to 2,000 Linear Feet per Minute (LFM)


Wind Tunnel

Working Section

Inlet

Thermal Imaging Camera

Airflow

Exit


Thermal Test ChipDescription

• A custom semiconductor chip.• Flexible solution which allows the thermal

characterization of semiconductor packages.• Usually a resistor network which acts as a

heater.• Diodes or transistors used as temperature

sensors.• Allows conventional processing of package

through all normal packing processes.


Thermal Test ChipSuppliers

Delphi:http://delphi.com/automotive/microelectronics/testdie/available/

Thermal Engineering Associates:http://www.thermengr.com/tea51.html

Micred Ltd:http://www.micred.com/index3.html


Thermal Test ChipCalibration

• Each temperature sensormust be calibrated.

• Simple procedure –Placed in oven at knowntemperatures - resistancemeasured at minimum of4 different temperatures.

• Relationship betweentemperature andresistance is linear.

• Equation developed foreach sensor.

T = 337.62 R - 248.27T - Temp R - ResistanceCorrelation Coeff R2 = 1

RTD(4) y = 338.05x - 249.09R2 = 1

0

20

40

60

80

100

120

0.75 0.8 0.85 0.9 0.95 1 1.05Resistance (k-ohm)

Tem

pera

ture

(C)


Thermal Test ChipPackaging

Ceramic LGA packageFlip chip bare die

Ceramic LGA packageCu/W lid/heat spreader


Thermal Test Chip

Size 22*22 mmDie composite of 34 individual

die5*5 Array of thermal die3 Die have smaller 4*4 arrayEach die has resistor and RTDIndividual die heater

resistance 130 ohms


Thermal Test Chip

• Initiated thermal testingusing 4 heaters(highlighted in red)

• Heaters wired in parallel• Resistance 33 ohms• Easily powered to 50

watts.Voltage - 40.62Current – 1.23 amps

1,3 3,3

1,1 3,1


Experimental Tools – Thermal Imaging

AdvantagesBest method for determining temperature fieldsNon contact, Non invasiveProvides pictorial representation of thermalinteraction of different parts of the socketFull field visibility – not temperature of adiscrete point

DifficultiesEmissivity of different surfaces and materials.


ExampleTemperature Distribution on Package

Objective: Evaluate temperature distributionin die due to use of 4 modulesCompare results for the lidded andlidless (bare die)

Method: Modify burn-in socket to providewindow to package.Paint socket and package with flatblack paint to eliminate emissivityproblems.


ResultsOriginal Socket for Ceramic LGA


ResultsSocket Modifications – Lidded Package

The central area of the heat sinkwas removed so that the lid of thepackage is visible.Note flat black paint on CuW lid


ResultsThermal Image Lidded Package - No Power

Heat loss by conductioninto socket and naturalconvection.No air flow over socket

No PowerNote uniformity of temperature


ResultsThermal Image - Lidded Package – 2.9 Watts

Image demonstratesuniform temperatureon lid

Temperature on Package Lid39.5 +/- 1°C


ResultsThermal Image - Lidless Package – No Power

Temperature on Lid+/- 0.6°C


ResultsThermal Image Lidless Package – 3.0 Watts

Slot in frame for heater

Holes for shoulder screw

Die Temperature42 +/- 2.0°C


RESULTSComparison of FEA versus Wind Tunnel Testing

FEA Prediction ½ model of heat sink on flip chip bare diePredicted θθθθja – 3.0 °C/watt Actual 3.2°C/watt


ResultsExperimental Thermal Image of Heat Sink

• Comparison of thermal images for:a) lidded and b) bare die package.

• Both images indicate that impinging air keeps “forward”heat sink cooler.

Air Flow

a) b)


ExampleUse of Thermal Imaging to Resolve Problem

Wind tunnel test results on open top socketindicated θθθθja was higher than predicted.

Use of thermal imaging helpedprovide insight to solveproblem (see next slide)

–Poor contact between heatsink and package.–Mechanism not functioningproperly.


ExampleUse of Thermal Imaging to Resolve Problem

After modificationθθθθja – 3.1 °C/watt

Poor contact between heat sink and packageInitial resultθθθθja – 4.4 °C/watt


Conclusions/Summary

• Analytical tools such as FEA and simpleanalyses reduce socket design cycle timeand cost by allowing evaluation of differentconcepts before cutting metal.

• Experimental tools such as the wind tunneland infra-red thermography provide

• confirmation of basic assumptions.

• visual records of the actual testconditions and insight into the thermalpath and heat flow.


AcknowledgementsWork presented here was the result of much

effort by many people.

The authors gratefully acknowledge thework by the following: …….

• Design Teams in USA, Japan and Korea.

• Manufacturing Teams in Japan, andKorea

• Technical Services and Thermal TestLab.

burn-in & test socket workshop• caf is the acronym for conductive anodic filament. •...

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