bus structure

7/28/2019 Bus Structure

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BUS STRUCTURE


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BUSBus is the mechanism by which the CPUcommunicates with memory and I/O

devicesBus is not just a collection of wires

Bus defines the protocol for

communication
http://images.google.co.in/imgres?imgurl=http://www.oxford-chiltern-bus-page.co.uk/upload110704/CAROUSEL%2520C%2520351%2520BUV%2520HIGH%2520WYCOMBE%2520BUS%2520STATION%25206TH%2520JULY%25202004%2520Gavin%2520Francis.jpg&imgrefurl=http://www.oxford-chiltern-bus-page.co.uk/110704.htm&h=480&w=600&sz=69&tbnid=_oC5CWviNMgJ:&tbnh=106&tbnw=133&start=54&prev=/images%3Fq%3DBus%26start%3D40%26hl%3Den%26lr%3D%26sa%3DN


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Bus (2)

Shared communication linksingle set of wires used to connectmultiple subsystems

A Bus is also a fundamental tool forcomposing large, complex systems

Control

Datapath

Memory

ProcessorInput

Output


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Bunch of Wires

Physical / Mechanical Characteristics

the connectors

Electrical Specification

Timing and Signaling Specification

Transaction Protocol

What defines a bus?


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Generic bus structureAddress:

Data:

Control:

m

c

n


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Control lines:

Signal requests and acknowledgments

Indicate what type of information is on thedata lines

Data linescarry information between the sourceand the destination:

Data and Addresses

Address: special form of data

Complex commands

Generic Organization of a Bus


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Time MultiplexingShare a single set of wires for multiple pieces of data

Saves wires at expense of time

data serializing address/data muxing

Master Servantreq

data(8)

data(15:0) data(15:0)

mux demux

Master Servantreq

addr/data

req

addr/data

addr data

mux demux

addr data

req

data 15:8 7:0 addr data

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction,Vahid/Givargis


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Non-multiplexed address and data lines:

Address and data can be transmitted in one bus cycleif separate address and data lines are available

Cost: (a) more bus lines, (b) increased complexity

Data bus width:

By increasing the width of the data bus, transfers of multiplewords require fewer bus cycles

Cost: more bus lines

Block transfers:

Allow the bus to transfer multiple words in back-to-back buscycles

Only one address needs to be sent at the beginning

The bus is not released until the last word is transferred

Cost: (a) increased complexity

(b) decreased response time for request

Increasing the Bus Bandwidth


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Advantages of BusVersatility:

New devices can be added easily

Low Cost:

A single set of wires is shared in multipleways


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Disadvantages of BusIt creates a communication bottleneck

The bandwidth of the bus can limit the maximum

I/O throughputThe maximum bus speed is largely limited by:

The length of the bus

The number of devices on the bus

The need to support a range of devices with:Widely varying latencies

Widely varying data transfer rates


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Parallel communicationMultiple data, control, and possibly power wires

One bit per wire

High data throughput with short distances

Typically used when connecting devices on same ICor same circuit board

Bus must be kept short

long parallel wires result in high capacitancevalues which requires more time to

charge/dischargeData misalignment between wires increases aslength increases

Higher cost, bulky


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Serial communication

Single data wire, possibly also control and power wires

Words transmitted one bit at a time

Higher data throughput with long distances

Less average capacitance, so more bits per unit of timeCheaper, less bulky

More complex interfacing logic and communicationprotocol

Sender needs to decompose word into bitsReceiver needs to recompose bits into word

Control signals often sent on same wire as dataincreasing protocol complexity


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Synchronous BusIncludes a clock in the control lines

A fixed protocol for communication that isrelative to the clock

Advantage: involves very little logic and canrun very fast

Disadvantages:Every device on the bus must run at the same

clock rateTo avoid clock skew, they cannot be long if theyare fast

Most processor-memory buses


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Asynchronous BusAsynchronous Bus:

It is not clocked

It can accommodate a wide range ofdevices

It can be lengthened without worrying

about clock skewIt requires a handshaking protocol


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Basic Protocol ConceptsAbus transaction includes two parts:

Issuing the command (and address) request

Transferring the data action

Master is the one who starts the bus transactionby:issuing the command (and address)

Slave is the one who responds to the address

by:Sending data to the master if the master ask for data

Receiving data from the master if the master wants tosend data


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Bus Arbitration

One of the most important issues in bus design:How is the bus reserved by a device that wishes touse it?

Master-slave arrangement:

Only the bus master can control access to the bus:It initiates and controls all bus requests

A slave responds to read and write requests

The simplest system:

Processor is the only bus masterAll bus requests must be controlled by the processor

Major drawback: the processor is involved in everytransaction


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Basic Transaction Protocols

Strobe protocol Handshake protocol

Master Servantreq

ack

req

data

Master Servant

data

req

data

taccess

req

data

ack

1. Master asserts req to receive data

2. Servant puts data on bus within time taccess

1

2

3

4

3. Master receives data and deasserts req

4. Servant ready for next request

1

2

3

4


2. Servant puts data on bus and asserts ack





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A strobe/handshake combination

Fast-response case

req

data

wait

1 3

4


2. Servant puts data on buswithin time taccess

3. Master receives data and deasserts req4. Servant ready for next request

2

Slow-response case

Master Servantreq

wait

data

req

data

wait

1

3

4


2. Servant can't put data within taccess, asserts waitack

3. Servant puts data on bus and deasserts wait


2

taccess taccess


5

(wait line is unused)



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When to use handshake?When response time cannot beguaranteed in advance:

Data-dependent delay.

Component variations.


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ISA bus protocolmemory accessMicroprocessor Memory I/O Device

ISA bus

ADDRESS

CYCLE

CLOCK

D[7-0]

A[19-0]

ALE

/MEMR

CHRDY

C1 C2 WAIT C3

C4

DATA

ISA: IndustryStandard

Architecture

Features20-bit addressCompromisestrobe/handshakecontrol

4 cycles defaultUnless CHRDYdeassertedresultingin additional waitcycles (up to 6)

memory-read bus cycle

CYCLE

CLOCK

D[7-0]

A[19-0]

ALE

/MEMW

CHRDY

C1 C2 WAIT C3

C4

DATA

ADDRESS

memory-write bus cycle



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Arbitration for Multiple Potential BusMasters

Bus arbitration schemes usually try to balance twofactors:

Bus priority: the highest priority device should be serviced first

Fairness: Even the lowest priority device should never

be completely locked out from the bus

Bus arbitration schemes can be divided into fourbroad classes:

Daisy chain arbitration

Centralized, parallel arbitrationDistributed arbitration by self-selection: each device wanting the busplaces a code indicating its identity on the bus.

Distributed arbitration by collision detection:Each device just goes for it. Problems found after the fact.


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The Daisy Chain

Disadvantages:

Cannot assure fairness:

A low-priority device may be locked outindefinitely

The use of the daisy chain grant signal also limits thebus speed

BusArbiter

Device 1

Highest

Priority

Device N

Lowest

Priority

Device 2

Grant Grant Grant

Release

Request

wired-OR

Advantage: simple


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Used in essentially all processor-memory

busses and in high-speed I/O busses

Bus

Arbiter

Device 1 Device NDevice 2

Grant Req

Centralized Parallel Arbitration


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Arbitration: Priority arbiterTypes of priority

Fixed priority

each peripheral has unique rankhighest rank chosen first with simultaneous requests

preferred when clear difference in rank betweenperipherals

Rotating priority (round-robin)

priority changed based on history of servicing

better distribution of servicing especially amongperipherals with similar priority demands


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Arbitration using a priority

arbiterMicro-

processor

Priority

arbiter

Peripheral1

System bus

Int

3

5

7

IntaPeripheral2

Ireq1

Iack2

Iack1

Ireq2

2 2

6



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arbiter (2) Microprocessor is executing its program. Peripheral1 needs servicing so asserts Ireq1.

Peripheral2 also needs servicing so asserts Ireq2.

Priority arbiter sees at least one Ireqinputasserted, so asserts Int.

Microprocessor stops executing its program andstores its state.

Microprocessor asserts Inta. Priority arbiter asserts Iack1to acknowledge

Peripheral1.


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arbiter(3) Peripheral1 puts its interrupt address vector

on the system bus

Microprocessor jumps to the address of ISRread from data bus, ISR executes andreturns (and completes handshake witharbiter).

Microprocessor resumes executing itsprogram


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Overlapped arbitration

perform arbitration for next transaction during

current transactionBus parking

master holds onto bus and performs multipletransactions as long as no other master makesrequest

Overlapped address / data phases

requires one of the above techniques

Increasing Transaction Rateon Multi-master Bus


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Increasing Bus transaction

rate (2)Split-phase (or packet switched) bus

completely separate address and data

phasesarbitrate separately for each

address phase yield a tag which is matched

with data phaseAll of the above in most modernmemory buses


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Direct memory access

Direct transfer of data by-passing CPU

Using DMA controllerSeparate single-purpose processor

Microprocessor relinquishes control of system busto DMA controller

Microprocessor can meanwhile execute its regularprogram

No inefficient storing and restoring state due to ISR call

Regular program need not wait unless it requires thesystem bus

Harvard architectureprocessor can fetch and executeinstructions as long as they dont access data memoryif they do, processor stalls

P i h l t t f


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Peripheral to memory transferwith DMA

1(a):P is executing its main

program. It has already configured

theDMA ctrlregisters.

1(b): P1 receives input

data in a register with

address 0x8000.

2: P1 asserts req to

request servicing byDMA ctrl.

7(b): P1 de-asserts req.

3: DMA ctrl

assertsDreq to

request control of

system bus.4: After executing an

instruction, P sees Dreqasserted, releases the system

bus, assertsDack, and

resumes execution. P stalls

only if it needs the system bus

to continue executing.

5: (a) DMA ctrl

asserts ack (b)

reads data from

0x8000 and (b)

writes that data to

0x0001.

6:. DMA de-

assertsDreq and

ack completing

handshake with

P1.

7(a):P de-assertsDackand

resumes control of the bus.


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ISA bus DMA cyclesProcessor Memory

I/O Device

ISA-Bus

DMA

R

A

R A

DMA Memory-Write Bus Cycle

ADDRESS

CYCLE

CLOCK

D[7-0]

A[19-0]

ALE

/IOR

/MEMW

CHRDY

C1 C2 C3 C4 C5 C6

C7

DATA

DMA Memory-Read Bus Cycle

ADDRESS

CYCLE

CLOCK

D[7-0]

A[19-0]

ALE

/MEMR

/IOW

CHRDY

C1 C2 C3 C4 C5 C6

C7

DATA



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Multilevel bus architecturesOne bus for allcommunication

Peripherals would need

high-speed, processor-specific bus interface

excess gates, powerconsumption, and cost;less portable

Too many peripheralsslows down bus

Processor-local bus

Micro-

processor

Cache Memory

controller

DMA

controller

BridgePeripheralPeripheralPeripheral

Peripheral bus


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Multi-level BusesProcessor-local bus

High speed, wide, most frequent communication

Connects microprocessor, cache, memorycontrollers, etc.

Peripheral busLower speed, narrower, less frequentcommunication

Typically industry standard bus (ISA, PCI) for

portabilityBridge

Single-purpose processor converts communicationbetween busses


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Parallel protocol: PCI BusPCI Bus (Peripheral Component Interconnect)

High performance bus originated at Intel in theearly 1990s

Standard adopted by industry and administered byPCISIG (PCI Special Interest Group)

Interconnects chips, expansion boards, processormemory subsystems

Data transfer rates of 127.2 to 508.6 Mbits/s and32-bit addressing

Synchronous bus architecture

Multiplexed data/address lines


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PCI Bus Architecture

Ref: IEEE Computer, 1999 Weiss & Finkelstein


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All signals sampled on rising edge

Centralized Parallel Arbitration

overlapped with previous transactionAll transfers are (unlimited) bursts

Address phase starts by asserting

FRAME#Next cycle initiator asserts cmd and

address

PCI Read/Write Transactions


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PCI Read/Write TransactionsData transfers happen on when

IRDY# asserted by master when ready to transferdata

TRDY# asserted by target when ready to transferdata

transfer when both asserted on rising edge

FRAME# de-asserted when master intends tocomplete only one more data transfer


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PC/104Small Size: 3.6 x 3.8

P1 Bus has 64 pins like PC-XT

P2 Bus has 40 pins(note: 64+40=104 as in PC/104)

Provides full AT compatibility

Replaces card edge connector withmore reliable pin-and-socket

Up to 4 modules can be stacked


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Single Board ComputersIntel pioneered the concept of a single boardcomputer (SBC) with the first industry standardmezzanine board called iSBX that providedadditional I/O

PC architecture redefined and vitalized thepopularity of the SBC

SBCs allowed companies to:

Make their design portable from one version to thenext

Shorten product development time

Focus manpower on product instead of the platform


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SBC

SBCs follow the technology developed by thePC Industry

Basic Architecture

ISA/PCI Bus protocolSerial & Parallel Port

The latest SBCs provide all the flexibility andpower of a PC with very small space

requirementsPC/104 and PC/104 plus meet the need ofSBCs


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SummaryWe have studied about Bus connectingCPU to memory and I/O devices

There may be more than one busmasterWe need arbitration

We shall look at the nature of busesused in SOCs

We shall also study serial buses


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BUS STRUCTURE-2SOC BUS

SERIAL BUS


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Recap: SBC

SBCs follow the technology developed by thePC IndustryBasic Architecture

ISA/PCI Bus protocol

Serial & Parallel PortThe latest SBCs provide all the flexibility andpower of a PC with very small spacerequirements

Software CompatibilityPC/104 and PC/104 plus meet the need ofSBCs

Small foot-print to suit the requirement of

embedded appliances


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BridgeA bridge is a slave on the fast bus andmaster of the slow bus

Takes command from the fast bus onwhich it is slave

Issues commands on the slow bus

Returns results from slow bus to fastbus

Also functions as protocol translator


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The System-on-a-Chip

Bridge

DMA CPU DSP

Mem

Ctrl.

MPEG

C

I O O

System Bus

Peripheral

BusControl Wires

Custom

Interfaces

System-on-a-chip

(SoCs) requires

busing systems to

connect variouscomponents,

including one or

more

microprocessors,

memory,

peripherals, and

special logic


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AMBA

Bridge

Timer

On-chipRAM

ARM

InterruptController

Remap/Pause

TIC

Arbiter

Bus InterfaceExternalROM

ExternalRAM

Reset

System Bus Peripheral Bus

AHB or ASB APB

ExternalBus

Interface

Decoder

AMBA: ARMs on chip bus specification


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AMBAAMBA is a multi-level Bus

ASB/AHB: Advanced System Bus: To connectHigh Performance modules

APB: Advanced Peripheral Bus: Simplerinterface for low performance peripherals

Support 32-, 64-, and 128-bit data-busimplementations with a 32-bit address bus

as well as smaller byte and half-word designs.Synchronous, non-multiplexed buses thatsupport bursting and pipelining


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AMBA based SystemSystem bus interconnects a processor in aSOC with memory controllers, on-chipmemory, and DMA controllers

Slower peripherals are connected to theslower, simpler APB peripheral bus.

System and peripheral buses can run atdifferent clock rates.

They link via a bridge that buffers data andoperations between the two buses.


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AHBThe AHB puts the address on the bus,followed by the data.

It supports wait-state insertion and hasa data-valid signal (HREADY).

It has separate read (HRDATA) and

write (HWDATA) buses.


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Bus operationAll bus operations are initiated by busmasters, which also can serve as a slave.

The master-generated address is decoded bya central address decoder that provides aselect signal to the addressed bus slave unit.

The bus master can "lock" the bus, reserving

it with the central arbiter for a series oflocked transfers.


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ArbitrationMaster x requests for the AHB byissuing req[x]

When bus is available the arbiter issuesa hgrant[x] to master x

Upon receiving grant signal master

issues address and control informationto indicate the type of transfer

Simple Arbiter Scheme


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Simple Arbiter Scheme

decoder

address

w

ritedata

readdata

master3

master2

master1

arbiter

slave3

slave2

slave1


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Bus transaction

The slave unit has the option to terminate atransaction

as an error,

signal the master to retry, or

split the transaction for later completion.

Split transactions enable the slave to defer

the operation until it's able to accomplish it,

thereby releasing the bus for other accesses.


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Split Transaction

The slave signals a split transaction and

saves the master number (HMASTER[]).

When ready to complete the transaction, theslave signals the arbiter with the master

number.

When the arbiter grants bus access to the

master, it restarts the transaction.No master can have more then 1 pending split

transaction.


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AHB Signals


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AHB Protection Control Signals

HPROT[1:0] : Protection control signalsprovide additional information about a busaccess

Primarily intended for use by a bus decoder whenacting as a basic protection unit.

The signals indicateif the transfer is an op-code fetch or data access,

if the transfer is a supervisor mode access or user modeaccess.

The signals are driven by the active bus masterand have the same timing as the address bus.


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Some more AHB SignalsHSIZE[1:0]

The transfer size signals indicate the size of thetransfer, which may be byte, half-word word. The

signals are driven by the active bus master andhave the same timing as the address bus.

HTRANS[1:0]Transfer signals indicate the type of the next

transaction, which may be address-only, non-sequential or sequential. These signals are drivenby a bus master when the appropriate GRANTxsignal asserted.


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Timing Diagram


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ARM Core AMBA InterfaceARM core cannot understand AMBAsignaling standards directly.

It needs an interface unit for decoding andtranslation to ASB/AHB signals

Some signals are just renamed


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ARM Core ASB Interface Wrapper


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APBDesigned to support low-speed peripheralssuch as UARTs, keypads, and PIO

All bus devices are slaves to the master, the

bridge to the AHB, or ASB system bus.

Provides a simple address, with latchedaddress and control signals for easyinterfacing.

APB can be implemented with a single tri-stated data bus.


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System Architecture


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ARM SYSTEM Architecture

System Architecture


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Open Core ProtocolOpen core defines a comprehensivebus independent,

high performance,

configurable interface

Connecting IP cores and on-chipcommunication interface

Synthesis/Timing Analysis Friendly

Encompass entire core/system interfaceneeds (data, control, and test flows)


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Master vs. SlaveIP CoreIP CoreIP Core

On-Chip Bus

Slave

Master SlaveSlave

Slave

Master

Master MasterInitiator Target

Open Core

Protocol RequestResponse


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Protocol Phases

Request Phase (begins Transfer)

Master presents request (command, address, etc.)to Slave

Response Phase (ends Transfer)

Slave presents response (success/fail, read data)to Master

Only available for read transfers (postedwritemodel)


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Protocol PhasesDatahandshake Phase (Optional)

Allows pipelining request ahead of write

dataOnly available for write transfers

Phase ordering

Request -> Datahandshake -> Response


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Use of ProtocolA designer selects only those signalsand features from the palette of OCP

configurations needed to fulfill all of anIP cores unique data, control and test

signaling requirements


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Serial Buses


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Serial ProtocolUsed for moving data quickly from onedevice to another

Serial protocols like I2C & SPI aremeant for short distances inside thebox

Low complexityLow cost


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I2CMeant for inter-Integrated CircuitCommunication

Developed by Philips Semiconductor for TV

sets in the 1980sI2C devices include EEPROMs, thermalsensors, and real-time clocks

Used as a control interface to signalprocessing devices that have separate datainterfaces, e.g. RF tuners, video decoders andencoders, and audio processors.


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I2C: Features

Bi-directionalData can flow in both directions

SynchronousData is clocked along with a clock signal

Clock signal controls when data is changed and whenit should be read

Clock rate can vary unlike asynchronous (RS-232style) communication

I2C bus has three speeds:Slow (under 100 Kbps)

Fast (400 Kbps)

High-speed (3.4 Mbps)I2C v.2.0


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Basic ProtocolI2C is a master slave protocol

Master device controls the clock (SCL)

Slave devices may hold the clock low toprevent data transfer

No data is transferred unless a clock signalis present

All slaves are controlled by the masterclock


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SummaryWe have studied bus specifications usedin a SOC

Looked at a serial bus for connectingdevices to a micro-controller

We shall learn more about serial buses

in the next class


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Bus Structure-3Serial Interfaces


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I2C: BasicsTwo wired busSerial data line(SDA)

Serial Clock line (SCL)

Voltage LevelsHigh - 1

Low - 0

Bit transferSCL=1 implies SDA = valid data

Stable data during high clock

Data change during low clocks


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I2C SignalsI2C lines can have two possible states

Float high

Drive lowPull-up resistor on the line and onlydevices pull the line low

If no device is pulling on the line it willfloat high


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Wired-and Connection

Bus is free implying SDA and SCL are highBy pull-up resistors

Device output is AND-ed with signal on bus


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Data transfer

Data bits are transferred after start condition

Transmission is byte oriented8 bits + 1 acknowledge bit

Most significant bit firstAddress of the slave is also data

First byte is address

During first byte transfer

Master is the transmitterAddressed slave is receiver

Next bytes: depend on the last bit in the addressbyte


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Addressing SchemeFirst byte transmitted by master7 bits: address

1 bit: direction(R/W)

0 master writes data1 master receives data

Master may generate repeated start andaddress another device

Each device listens to addressIf address matches device switches stateaccording to R/W bit


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Data TransferSCLMaster sets SCL=0 and generates pulsefor each data bit

8 pulses for data followed by one for ackAfter ack

Master tries to generate next bytes first

pulseSlave can hold SCL low forcing master toswitch to wait state


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Data transferSCL


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Data transfer -SDLData bits are generated by transmitteras SCL pulses

9th pulseTransmitter releases SDA

Receiver must hold SDA low in order to ack

received dataSlave must release SDA after acknowledgebit


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Data transferSDL


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Frame Format


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Bus Arbitration

I2C designed as a multi-master busAny one of several different devices may act asthe master at various times

No global master to generate clock

A master drives both SCL and SDL

When two devices try to drive SDL todifferent values

Listen to the bus to be sure that is not interfering

with another messageIf the device is trying to send a logic 1 but hears logic 0 ,it immediately stops transmission and gives the othersender priority


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I2C in PICIn PIC micro-controller MSSP moduleprovides the support for I2C

MSSP

SSPBUF: a


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I2C in PIC

I2C Engine

implements I2C

protocol in hardware

Controls actions of

the device based

I2C instructions

SSPBUF: a

register that stores

data sent or

received on I2C

bus


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I2C TradeoffsAdvantages:Good for communication with on-board devicesthat are accessed occasionally.

Easy to link multiple devices because ofaddressing scheme

Cost and complexity do not scale up with thenumber of devices

Disadvantages:The complexity of supporting softwarecomponents can be higher than that of competingschemes ( for example, SPI ).


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SPIShorthand for Serial Peripheral InterfaceDefined by Motorola on the MC68HCxx line ofmicrocontrollers

Generally faster than I2C, capable of several Mbps

Applications:Like I2C, used in EEPROM, Flash, and real timeclocks

Better suited for data streams, i.e. ADCconverters

Full duplex capability, i.e. communication betweena codec and digital signal processor


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SPI Bus Configuration

Master Slave

SCLKMOSI

MISO

/SS

l


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Bus Signals

Synchronous serial data link operating at fullduplex

Master/slave relationship

2 data signals:MOSImaster data output, slave data input

Also called SDO : serial data output

MISOmaster data input, slave data outputAlso called SDI: serial data input

2 control signals:SCLKclock

/SSslave select (no addressing)


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SPI vs. I2

CFor point-to-point, SPI is simple andefficient

Less overhead than I2

C due to lack ofaddressing, plus SPI is full duplex.

For multiple slaves, each slave needsseparate slave select signal

More effort and more hardware than I2C


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SPI Protocol


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2 Parameters, Clock Polarity (CPOL) and Clock Phase(CPHA), determine the active edge and idle state ofthe clock

Master and slave must agree on parameter pair

values in order to communicate

CPOL CPHA Activeedge

0 0 Rising

0 1 Falling

1 0 Falling

1 1 Rising

SPI P t l (2)


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SPI Protocol (2)

SPI interface defines onlythe communication linesand the clock edge

There is no specified flow

controlNo acknowledgementmechanism to confirmreceipt of data

Hardware realization can

be done with a simple shiftregister


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Communicating withEmbedded System


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USBUSB is a serial protocol and physical linktransmits all data differentially on a single

pair of wires.Another pair provides power todownstream peripherals

PC centric protocol

Every USB device is an embeddedsystem.


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Bit serial bus

USB uses bit-serial, differential drive

technology


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USB signalingSpeeds:High-speed is 480 Mb/s.

Full-speed is 12 Mb/s.Low-speed is 1.5 Mb/s.

Signals:

Vbus, Gnd.D+, D-.


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USB powerUSB devices can pull a limited amountof power from the bus.

May also supply their own power.System may provide a power-management protocol.

Independent of USB.


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USB architectureUSB Peripherals are slaves respondingto commands from the host.

When a peripheral is attached to theUSB network, the host communicateswith the device

To learn its identity andTo discover which device driver is required(a process called enumeration ).


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USB devicesThe specification recognizes two kindsof peripherals:

Stand-alone (single function units, like amouse)

Compound devices (those that have morethan one peripheral sharing a USB port).

An example of a compound device is a videocamera with separate audio processor.


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USB bus protocolPolled bus, all transfers initiated by host.Basic transaction:

Host sends token packet:

Type and direction.

USB device number.

Endpoint number (subdevice).

Data transfer packet.

Acknowledge packet.


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SummaryWe have studied serial interfaces forconnecting peripherals

We have also looked at serial busprotocol for connecting embeddedsystems to hosts


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Recap: USB bus protocolPolled bus, all transfers initiated by host.Basic transaction:

Host sends token packet:

Type and direction.

USB device number.

Endpoint number (subdevice).

Data transfer packet.

Acknowledge packet.

B P t l


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Bus Protocol

Host controller initiates data transfer by generating

token packet

Data transferred

Handshake packet for completion

handshake

data transfer

token

Type of transaction

Direction of trans.USBdevice address


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Attach and Remove of USB Devices

Host

Hub

port

port

port

upstream port

device

Enable port

allocate

USB addressindicato

rdisable

Remove

indicato

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USB HubsHubs are bridgesIncrease the logical and physical fan-out of thenetwork.

A hub has a single upstream connectionMany downstream connections.

Hubs are themselves USB devices

Hubs detect topology changes dueinsertion/deletion of devices.

They also source power to the USB network


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USB CommunicationCommunications between the host andendpointslocated in the peripherals.

An endpoint is a uniquely addressableportion of the peripheral that is the sourceor receiver of data.

Four bits define the device's endpointaddress;

Codes also indicate transfer direction andthe transaction


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PIPEPipe: all transfers occur through virtual pipesthat connect the peripheral's endpoints withthe host.

When establishing communications with theperipheral, each endpoint returns a descriptor

Descriptor is a data structure that tells the hostabout the endpoint's configuration and

expectations.Include transfer type, max size of data packets, perhapsthe interval for data transfers, and in some cases, thebandwidth needed.


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Types of data transferFour data transfer types:control,

Isochronous

Bulk

interrupt.

Control transfers exchange configuration,

setup, and command information betweenthe device and the host.


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Bulk data transferBulk transfers move large amounts ofdata when timely delivery isn't critical.

Typical applications include printers andscanners.

Bulk transfers are fillers, claiming unusedUSB bandwidth when nothing more

important is going on.


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Interrupt transferInterrupt transfers, though notinterrupts in the CPU-diverting sense,

poll devices to see if they need service.Peripherals exchanging small amounts ofdata that need immediate attention (suchas mice and keyboards) use interrupt

transfers.Error checking validates the data.


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Isochronous transferIsochronous data transferensures that dataflows at a pre-set rate so that an applicationcan handle it in a timed way.

Isochronous transfers handle streaming datalike that from an audio or video device.

It is time sensitive information so, withinlimitations, it has guaranteed access to the

USB bus.No error checking occurs so the system musttolerate occasional scrambled bytes.


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IEEE 1394

IEEE 1394 (Firewire)


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IEEE 1394 (Firewire)

400 Mbps and more( 3200Mbps for 1394b )

Plug & play

Provides power

Comparison to USB

USB is host-based(must be connected to

computer)

IEEE 1394 is peer to peer(two devices can beconnected directly)

Firewire:features


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Firewire:features

Packet-based layered design structure

Applications using FireWire include:disk drives, printers, scanners, cameras

Capable of supporting a LAN similar toEthernet64-bit address:

10 bits for network ids, 1023 subnetworks

6 bits for node ids, each subnetwork can have 63 nodes

48 bits for memory address, each node can have 281terabytes of distinct locations


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IEEE 1394 Applications

Source: Texas Instruments

Connecting Devices


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Connecting Devices

In work area #1 a videocamera, PC, and videorecorder, allinterconnected

PC is also connected to aphysically distant printervia a 1394 repeater

Repeater extends the inter-device distance by redrivingthe 1394 signals.

A 1394 splitter is used toprovide another port toattach a 1394 bus bridge.

Source: http://www.pctechguide.com/26interfaces_IEEE_1394.htm

Connecting Devices


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Connecting Devices

The 1394 bus bridgeisolates data traffic withineach work area.

Bus bridges allow selected

data to be passed from onebus segment to another.PC #2 can request imagedata from the video recorderin work area #1.

Since the 1394 cable ispowered, the signallinginterface is always powered

Video data is transportedeven if PC #1 is powered off.

Source: http://www.pctechguide.com/26interfaces_IEEE_1394.htm

Protocol Stack


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Protocol Stack

Soure: Xilinx

Ph i l L


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Physical LayerPhysical layer provides the initialization andarbitration services

It assures that only one node at a time is sendingdata

IncludesElectrical signaling

Mechanical connectors and cabling

Arbitration mechanism

Serial coding and decoding of data beingtransferred or received

Transfer speed detection

Link Layer


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Link Layer

Extracts and put data packets on and off thewire

Does error detection and correction

Does retransmissionHandles provision for cycle control forisochronous channel

Link layer supplies an acknowledged

datagram to the transaction layerA datagram is a one-way data transfer withrequest confirmation


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Transaction Layer

Implements Request-response protocol

Minimizes amount of circuitry required

to interconnect with standard busessuch as the PCI bus


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Host Controller

Soure: Xilinx


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Wireless Protocol

IRDA

Wireless communication


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Wireless communication

Infrared (IR)Electronic wave frequencies just belowvisible light spectrum

Diode emits infrared light to generatesignal

Infrared transistor detects signal, conductswhen exposed to infrared light

Cheap to buildNeedline of sight, limited range


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IrDAIrDA is a standard defined by the IrDAconsortium (Infrared Data Association).

Specifies a way to wirelessly transfer data via

infrared radiation.Specifications include standards for both thephysical devices and the protocols they use tocommunicate with each other.

Can connect various mobile/embedded systemsPrimary use has been to link notebooks or variouspersonal communicators


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FeaturesMost IrDA work over distances up to 1.0mwith BER 10-9 and maximum level ofsurrounding illumination 10klux (daylight).

Bit Error Ratio - number of incorrectly transferredbits over number of correctly transferred bits

Pulse modulation with 3/16 of the length ofthe original duration of a bit is used.

Data format is the same as for a serial port -asynchronously transmitted word, with a startbit at the beginning.


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Pulse widthTransmitter can use either 3/16 mark-to-space ratio for one bit, or a fixed length 1.63us of each optical pulse, which would

correspond to 115kbps (ver1.0).

IR Frame

Why pulse modulation?


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Why pulse modulation?

The receiver needs to distinguish betweenthe surrounding illumination, noise, andreceived signal.

Useful to use the highest possible output

power:higher power -> higher current in the receiver ->better signal-to-noise ratio.

IR-LED's can not transmit at full power

continuously over 100% of time. So, a pulsewidth of only 3/16 of the total time for onebit is used.

Advantages of Pulse modulation


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Advantages of Pulse modulation

Power can be up to 4 or 5 times the possiblemaximum power for LED's shiningcontinuously.

The transmission path does not carry the dccomponent

Receiver continuously adapts itself to thesurrounding illumination, and detects changesonly.

Integrated IrDA transceivers do have filtersthat eliminate noise other than the IrDAfrequency range 2400-115200 bps


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Packet StructureA packet consists of two start words followedby target address

IrDA devices are assigned numbers by the means

of IrDA protocol, so they are able tounambiguously identify themselves

Followed by data, CRC-16 and a stop word.

The whole packet (frame) including CRC-16 is

generated by IrDA compatible chipset.Start and stop words last 1.5times the bitduration (6 times longer flash than usual).


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ProtocolsIrDA Infrared Link Access Protocol(IrLAP)

Encapsulates the frames

Provides arbitrationOnly one primary device, others are secondary

The communication is always half-duplex

Describes how the devices establishconnection, close it, and how are theygoing to be internally numbered.


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ProtocolsIrDA Transport Protocols (Tiny TP)

This layer manages virtual channels betweendevices, performs error corrections (lost packets,etc.), divides data into packets, and reassemblesoriginal data from packets.

IrDA Object Exchange Protocol (IrOBEX)Defines PUT and GET commands, thus allowingbinary data transfer between devices.

The standard defines what a packet must containin order for the devices to recognize each otherand communicate.


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Application ProtocolsExtensions to IrOBEX for Ir MobileCommunications

Extension for mobile devices - handhelds, PDA,

cellular phones - defines how to transferinformations pertaining to GSM networkaddress books, SMS, calendar, dialing control, digitalvoice transfer over IR, etc.

IrTran-P (Infrared Transfer Picture)

SpecificationSpecifies how to transfer pictures over the infraredinterface.


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Application of IrDA


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Wireless Communication

Radio frequency (RF)

Electromagnetic wave frequencies in radio

spectrumAnalog circuitry and antenna needed onboth sides of transmission

Line of sight not needed, transmitter powerdetermines range


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Generic Issues

d d


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Error detection and correctionOften part of bus protocol

Error detection: ability of receiver to detecterrors during transmission

Error correction: ability of receiver andtransmitter to cooperate to correct problem

Typically done byacknowledgement/retransmission protocol

Bit error: single bit is invertedAlways detects single bit errors, but not all burstbit errors

Error detection and Correction


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Burst of bit error: consecutive bits receivedincorrectly

Parity: extra bit sent with word used for errordetection

Odd parity: data word plus parity bit contains oddnumber of 1s

Even parity: data word plus parity bit containseven number of 1s

Checksum: extra word sent with data packet ofmultiple wordse.g., extra word contains XOR sum of all data words inpacket

Trends in Bus structure


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Switched Serial Inter-ConnectPacket switching

Serial high speed buses for connectingprocessor to memory and peripherals

Use of packet switching for improvingtransfer efficiency

Split transactionExample: PCI-express

S


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Summary

We have studied about bus structuresused for connecting CPU andperipherals

We have also looked at the interfacespecifications for connecting two ormore systems

bus structure

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