by the end of this topic, student should be · by the end of this topic, student should be...

By the end of this topic, student should be

able to:

1. Define Programmable Logic Device

methodology for integrated circuit.

2. Discuss the advantages of PLD

compared to standard IC and custom IC.

3. State general characteristic of PLD.

4. Discuss example of ROM IC using PLD.

5. List the company names of this IC

manufacturer.

• PLD is a general-purpose chip for implementing

logic circuitry. Transistors and wires are already

prefabricated on the PLD. Unlike a logic gate,

which has a fixed function, a PLD has an

. Before the PLD can be

used in a circuit it must be programmed.

• An integrated circuit that can be programmed in

a laboratory to perform complex functions. Most

“standard” PLDs consist of an AND array

followed by an OR array, either (or both) of

which is programmable.

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• Circuits are permanent.• They perform one function or set of functions.• Once manufactured, they cannot be changed.• Constrained to parts.• Need to stock many different parts.• Most resources (power, board area,

manufacturing cost) are consumed by the “package” but not by the “silicon”, which performs the actual computation.

• Automation is impossible.Example

Fixed Logic Devices (e.g. SSI/MSI)Small-Scale Integration (SSI) uses circuits containing transistors numbering in the tens, while Medium-Scale Integration" (MSI) contains hundreds of transistors on each chip.

Disadvantages

02/02/2009 7

• Devices can be changed at any time to perform any number of functions.

• Use a single chip (or a small number of chips).• Program it for the circuit you want.• Testing using simulation.• Then, a design can be quickly programmed into a device, and

immediately tested in a live circuit.

Programmable Logic Devices

Lecture Notes – Lab 2

VHDL is the standard language used by designers to describe the circuit or system to be implemented.

02/02/2009 8

Basic VHDL building blocks

Lecture Notes – Lab 2

Example 1: Consider the following circuit:

EntityENTITY fewgates IS

PORT (

A : IN STD_LOGIC;

B : IN STD_LOGIC;

C : IN STD_LOGIC;

Y : OUT STD_LOGIC

);

END fewgates;

ARCHITECTURE c1_behavior OF fewgates IS

SIGNAL sig1: STD_LOGIC;

BEGIN

sig1 <= (NOT A) AND (NOT B);

Y <= C OR sig1;

END c1_behavior;

Architecture sig1

ADVANTAGES OF PLD

1. Ease of designThe design support tools consist of design software

and a programmer. The design software is used in

generating the design; the programmer is used to

configure the device.

Many PLD users do not find it necessary to purchase a

programmer; it is often quite cost effective and

convenient to have either the manufacturer or an

outside distributor do the programming for them.

For design and prototyping, though, it is very helpful to

have a programmer; this allows one to implement

designs immediately.

ADVANTAGES OF PLD

2. PerformanceThe PLD devices can provide equal or better

performance than the fastest discrete logic available in

terms of speed and power consumption.

3. ReliabilityAs systems get larger and more complex, the increase

in the amount of circuitry tends to reduce the reliability

of the system; there are “more things to go wrong.”

such as crosstalk and noise. Thus, a solution which

inherently reduces the number of chips in the system

will contribute to higher reliability. A programmable logic

approach can provide a more reliable solution due to

the smaller number of devices required.

ADVANTAGES OF PLD

4. Cost savingsThe greatest savings over discrete design are derived

from the fact that a single PLD can replace several

discrete chips. Board space requirements can drop

25% or more when PLDs are used.

Programming a PLD doesn‟t involving masking

process. Thus, cost saving than full custom and semi

custom.

GENERAL

CHARACTERISTICS OF PLD

1. No customized cells or masks, just a

single large block of programmable

interconnect.

2. Can be configured / programmed to

create a specialized device.

3. Fast turn-around time.

By the end of this topic, student should be able to:

1. Draw a floor plan for PLD.

2. Label the different parts of PLD.

3. Explain the content of PLD.

4. Draw the architectural diagram of PROM, PAL

and PLA.

5. State the differences between these 3 types IC

along with examples of the operational logic

function.

FLOOR PLAN OF PLD

Programmable

logic circuit

Complex Programmable Logic Devices (CPLD)

Other example:

programmable

OR array

programmable

AND array

programmable

OR array

fixed AND arrayprogrammable

AND array

fixed OR array

Operational

logic

function

COMPARISON BETWEEN

PROM, PAL, PLA

PROM

• Consists of fixed AND gates array and programmable OR gates array.

• Medium speed.

• Cheap (high‐volume component)

• Not flexible.

PAL

• Consists of programmable AND gates array and fixed OR gates array.

• High speed (only one programmable gates array).

• Intermediate cost (less than PLA).

• Not flexible.

PLA

• Consists of programmable AND gates array and programmable OR gates array.

• Slow (two programmable gates arrays).

• Most expensive (most complex in design, need more sophisticated tools)

• offering maximum programming flexibility.


1. Draw the block diagram of hardware used

when programming the PLD.

2. Describe the methods of downloading a

program using schematic editor, Boolean

expression and truth table.

3. State examples of low-level design language

and the software that uses them.

4. State examples of high-level design language.

Programming the PLD

Block Diagram of

the ISP

Programmer

(ATMEL

AT89SXX ISP)

Circuit diagram

of the ISP

Programmer

(ATMEL

AT89SXX ISP)

http://www.8052.com/users/AT89S52InSystemProg/

ATMEL AT89SXX ISP Flash Programmer v1.4

Programming the PLD

• Method

1. Schematic Editor

2. Boolean expression & Truth table

3. Language

i. Low-level design language

ii. High-level design language

Schematic1. The schematic can be developed by hand using

Design Architect software.

http://www.people.vcu.edu/~rhklenke/tutorials/plds2/tutorial.html

Schematic2. Check and simulate the schematic in Quicksim

software.


Schematic3. Export the schematic to PLDS II and BP1400

Universal Device Programmer.


Schematic4. Setting parameter.


Schematic5. Select template.


Schematic6. Device mapping.


Schematic7. View.


Boolean Expression

• ORCAD/PLD

Boolean Expression

• ORCAD/PLD

Boolean Expression : W = A + B + CD

W = A # B # (C&D)

Boolean Expression• ORCAD/PLD – Example program:

Truth table• ORCAD/PLD

Input Output

A B f

0 0 1

0 1 1

1 0 0

1 1 0

Input Output

A B x y

0 0 1 0

0 1 1 1

1 0 0 1

1 1 0 0

Language for LPD

• Low-Level Design Languages

– ABEL - PLD programming language from

Data I/O

– CUPL - PLD programming language from

Logical Devices

– PALASM - PLD programming language from

AMD/MMI

ABELhttp://wwwdsa.uqac.ca/~daudet/Cours/Vlsi/DOCUMENTS/repertoire435/Cours-MJS-Smith/CH09/CH09.10.htm#pgfId=3197

CUPLhttp://wwwdsa.uqac.ca/~daudet/Cours/Vlsi/DOCUMENTS/repertoire435/Cours-MJS-Smith/CH09/CH09.11.htm#pgfId=3209

PALASMhttp://wwwdsa.uqac.ca/~daudet/Cours/Vlsi/DOCUMENTS/repertoire435/Cours-MJS-Smith/CH09/CH09.12.htm#pgfId=3294

Language for LPD

• High-Level Design Languages

–Verilog HDL (Verilog Hardware

Description Language)

–VHDL (Very high speed integrated

circuit Hardware Description

Language)

Language for Veriloghttp://en.wikipedia.org/wiki/Verilog

Language for VHDLhttp://en.wikipedia.org/wiki/VHDL


1. Draw the physical structure of Floating gate

Avalanche MOS transistor (FAMOS).

2. Describe how FAMOS can be on ON or OFF

state.

3. Give examples of operational of logic function

of this transistor in matrix interconnect.

FAMOS• Floating gate Avalanche Injection MOS transistor used in

EPROM (Erasable Programmable Read Only Memory).

• Operation (ON):

– When not programmed (logic 1), the floating gate has no extra

charge on it and the transistor is controlled by the non-floating

gate (control/access gate). Positive charge in the control/assess

gate creates a channel in the p-substrate that carries a current

from source to drain.

FAMOS• Floating gate Avalanche Injection MOS transistor used in

EPROM (Erasable Programmable Read Only Memory).

• Operation (OFF):– To fuse-out a transistor (logic 0), a high voltage is applied to the access

gate of the transistor which causes accumulation of negative charge in

the floating-gate area.

– This negative charge then shields the control gate and prevents the

formation of a channel between source and drain. The transistor,

therefore, will act as an unconnected transistor for as long as the

negative charge remains on its floating-gate.

Example in matrix interconnecthttp://www.cse.scu.edu/~tschwarz/coen180/LN/flash.html


1. Describe the programming method of PLD

using fuse.

2. Draw the programming method using anti-fuse,

metal anti-fuse and polydiffused anti-fuse.

3. State the response of all types of anti-fuse

while the PLD is being programmed.

http://mouloudrahmani.com/ELECTRICAL/DIGITAL/FPGAFUNDAMENTALS.HTML


1. Draw the block diagram for FPGA and CPLD.

2. State differences between FPGA, CPLD and

PLD

Comparison of Design Styles

Full-Custom Standard Cell Gate Array FPGA

Area compactcompact to

moderatemoderate large

Performance highhigh

to moderatemoderate low

Design cost high medium medium low

Time-to-market long medium medium short

Comparison of Design Styles

Full-CustomStandard

CellGate Array FPGA

Cell size variable fixed height fixed fixed

Cell type variable variable fixedprogramma

ble

Cell placement variable in row fixed fixed

Interconnections variable variable variableprogramma

ble

Fabrication

layersall layers

all

layers

routing layers only no layers

1. FPGA contains up to 100,000 of tiny logic blocks while CPLD contains

only a few blocks of logic that reaches up to a few thousands.

2. In terms of architecture, FPGAs are considered as „fine-grain‟ devices

while CPLDs are „coarse-grain‟.

3. FPGAs are great for more complex applications while CPLDs are better

for simpler ones.

4. FPGAs are made up of tiny logic blocks while CPLDs are made of larger

blocks.

5. FPGA is a RAM-based digital logic chip while CPLD is EEPROM-based.

6. Normally, FPGAs are more expensive while CPLDs are much cheaper.

7. Delays are much more predictable in CPLDs than in FPGAs.

by the end of this topic, student should be · by the end of this topic, student should be...

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