c2000 digital power control seminar -...

C2000Digital Power Control

Seminar

Version 1.0

January 2015

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void TypeII_Calc(void){

e[0]= Vref - AdcVal;u[0] = b0*e[0] + b1*e[1] + b2*e[2] - a1*u[1] - a2*u[2];PWMDUTY* = u[0] * k; // write new duty cycleu[2] = u[1];u[1] = u[0];e[2] = e[1];

C2000 Digital Power Control

version 1.0

½-day Technical Seminar

Scope & ObjectivesThis seminar will help you to...

• Appreciate the major considerations in digital power

• Understand how digital power control loops are designed

• Implement a digitally controlled power supply

The seminar does not cover...

• Power supply design

• Control theory

• C programming

2

DIGITAL POWER CONTROL SEMINAR 1

Agenda1. Digital Power Overview

Analogue vs. Digital ControlDigital Power Control RequirementsC2000 Platform Architecture

2. Power Topology SupportPWM GenerationPower Topologies Peak Current Mode Control

3. Closed Loop ControlDesign ExampleSoftware Frequency Response AnalyzerLimit Cycle Issues

4. Control Law ImplementationPre-ComputationNumerical ConsiderationsThe Control Law Accelerator

5. Design ResourcesReference DesignsFurther CoursesRecommended Reading

3

TI Embedded Processors

32-bit ARMMCUs

16-bit Ultra-Low Power

MCUsApplicationProcessors

32-bit ARMfor High

Performance Applications

Tiva-CTMS570

RM4 CortexMSP430

SitaraCortex-A8/A9 + ARM9

KeystoneCortex-A15 + DSP

OMAPCortex-A8, A9

& A15

Digital Signal ProcessorsMicrocontrollers ARM® Based Processors

Software & Dev. Tools

Up to 220 MHz

300 MHz to 5 GHz

Up to 25 MHz Up to 1.7 GHz

32-bit Real-Time

ControlMCUs

C2000

40 MHz to 300 MHz

Multi-Core DSP

KeystoneMulti-Core + ARM

C6000Multi-Core

Up to 15 GHz

Single CoreDSP

C6000Power Optimised

C5000 Ultra Low Power

Up to 1.5 GHz

Flash1 KB to 256 KB

Measurement,Sensing, General

Purpose

$0.25 to $9.00

Analog I/O, ADCLCD, USB, RF

PWM, ADC, CAN, SPI, I2C

Motor Control, Digital Power,

Renewable Energy

$1.50 to $20.00

Flash, RAM16 KB to 512 KB

USB, ENET MAC+PHY CAN, ADC, PWM, SPI

Connectivity, Security,Motion Control, HMI,Industrial Automation

$1.00 to $8.00

Flash64 KB to 3 MB

USB 3.0+PHY, CAN,Gigabit Ethernet MAC,

PCIe+PHY, SATA+PHY

Industrial computing, POS & portable

data terminals

$5.00 to $20.00

Cache: 32 KB I/D256 KB L2

LPDDR 1/2/3USB 2/3, eMMC,

SD/MMC, I2s,HDMI, SATA

Floating/Fixed PointVideo, Audio, Voice,

Security, Conferencing

$5.00 to $200.00

Cache: 32 KB I/D2 MB L2

RAM, ROM

USB 2.0+PHY, CAN, PRU, ADC, SPI,

McBSP, LCD

Telecom , test & meas., media gateways,

base stations

$40 to $200.00

Cache: L2 mDDR, 320 KB RAM 256 KB ROM

RapidIO, PCIe, 10GigE, USB 3.0, Hyperlink,

DDR3, NetCP

Audio, VoiceMedical, Biometrics

$3.00 to $10.00

Up to 4 MB SL2, 32 KB L1, 1MB L2

4

2 C2000 TECHNICAL TRAINING

1. Digital Power Overview

5

1. Digital Power OverviewAnalogue vs. Digital ControlDigital Power Control RequirementsC2000 Platform Architecture





Analogue Power Control System

6

• In an analogue power control system both power stage and compensator are typically described in the form of transfer functions.

• These are based on a set of differential equations derived from the under-lying physical laws.

• Techniques for modelling power stages and designing analogue compensators are mature and well understood.


Digital Power Control System

7

• When we apply digital control to a power system the power stage description is still an analogue model, while the compensator is a discrete time control law or z transform.

• The A/D converter introduces finite resolution, quantization error, and frequency artefacts not present in the analogue system.

• The digital PWM generator imposes a limit on the resolution of the pulse edges. This translates into a resolution limit on the control output.

22

11

22

110

1)(

zazazbzbbzF

Analogue vs. Digital Control

8

Wide bandwidth Bandwidth limited by sampling

Infinite resolution Resolution fixed by data converters

Theory well understood Requires new theory

Perceived as lower cost Processor can perform multiple tasks

No software Requires programming skills

Component drift & aging Immune from drift

Sensitive to temperature change Insensitive to thermal effects

Hardwired / not flexible Functionality detetmined by software

Limited control techniques possible Can implement advanced control strategies

Large parts count for complex systems Multiple control functions can be run in parallel

Loop response must be measured off-line Can run in-circuit frequency measurement

Testing must be performed manually Periodic self-test and diagnostics in software

No record of operation Data logging and communications

Analogue Control Digital Control


Time Sampled Systems

9

In general, the digital part of the control loop consists of three major blocks, each of which restricts the perfomance of the control system differently.

ADC throughput limits the complexity of the control law and the number of channels which can be simultaneously controlled

CPU speed determines computation time of the control law which limits upper control loop frequency & affects phase margin

PWM resolution limits the maximum switching frequency

Digital Power Control Requirements

10

To control power electronics using an MCU, four features are essential:

1. A high speed ADC which can be synchronised with the switching patterns

2. A high performance CPU for low latency computation of the control law

3. A flexible PWM pattern generator capable of supporting multiple high frequency power topologies

4. A high speed comparator sub-system to trip PWM outputs on current events


F2807x Control Architecture

11

Feedback• 3 x 12/16-bit ADCs• 3 x 12-bit buffered DACs• 4 x comparator sub-systems

Computation• 120MHz floating-point CPU• 120MHz CLA• 512KB flash• 100KB RAM

Actuation• 24 x PWM modules• High resolution edge control• Integrated dead-band• Trip zone control

(F28075 shown)

A0A1A2A3A4A5

TripZonelogic

Int-Osc-1PWR

GND

POR / BOR

Int-Osc-2

Ext-Osc-2

Timer-0

Timers(32bit)

Timer-1Timer-2

GPIO cntl

X1X2 PLL

WD

TRIPIN

System

DAC-B

PWM1 AB

PWM2 AB

PWM3 AB

PWM12

PWM-1APWM-1BPWM-2APWM-2BPWM-3APWM-3B

15

DCAN x 2

SCI x 3

SPI x 3

CAP x 6 CAP

QEP x 3 QEP

Vreg-DCDC

ADC12-bit3.19 MSPS(1 S/H)

DAC-A

DAC-12

B0B1B2B3B4B5

Flash 512 KB

CLA32bit-FltPt/120 MHz

RAM 100 KB

TMU

12

C28 CPU-(FPU)32 bit–120 MHz

DFH1

x8

I2C x 2

DAC-12

DAC-12Ch.xP

Ch.xN

Comparator Sub-System

DAC-12

System Management

SCI

SPI

CAN

I2C

TRIPOUTAnalogue

AB

PWM-12APWM-12B

DAC-C DAC-12

54


12

54

C0C1C2C3C4C5


12

5C6 6

Application Example

12

Topology shown:Isolated Phase Shifted Full Bridge (PSFB) DC-DC converter with 2-phase Interleaved boost Power Factor Correction (PFC) and secondary side Synchronous Rectification (SR).

Digital control implemented using a single primary side micro-controller.

48V

IPFC

FILTER

VRECT VOUT

IphA IphB

95~275VAC

C2000VRECTVBUSIPFCIphAIphB

1A

DC bus

1A 1B

2A

2B

3A

3B

4A

4B

Aux.DC/DC

3V3DC bus

1B

IOS

VOUT

Ipri

PWM1

ADC12 bit

5 MSPS

I2CSPI

UARTCAN

Comms

CPU32 bit

DSP core60 MHz

3V3

PWM2I/Os

CLA

PWM3

PWM4

PWM5

2A2B3A3B

4A4B

Host

Ipri

IOS

5A5B


1. Summary

13

• Analogue vs. Digital Control

• Digital Power Control Requirements

• C2000 Platform Architecture

2. Power Topology Support

14







Modular PWM Architecture

15

Key features• Flexible pattern generation• Synchronized PWM• Tight coupling with

ADC,interrupts• Configurable trip functionality

PIE

PWM1Module

PWM2Module

PWMnModule

SYNCO

SYNCI

SYNCI

SYNCO

SYNCI

SYNCO

GPIOMux

xSYNCI

PWMnA

PWMnB

PWM2A

PWM2B

PWM1A

PWM1B

PWM1INT

PWM1SOCA/B

EPWM2INT

ADC

PWM2SOCA/B

TRIP4 to 12

EPWMnINT

PWM2SOCA/B

XTRIPX-BAR

TRIP4 to 12

TRIP4 to 12

xSYNCO

Each PWM module:• 2 PWM outputs• 1 SYNC in• 1 SYNC out• 2 ADC SOCs• 1 INTs• 8 TRIPINs

PWM Sub-ModulesTime-Base Module (TB)• Generates counter timebase• Controls period (frequency) • Controls phase shift

Dead-Band (DB)• Inserts dead-band delays• Programmable rising/falling

edge delays

Trip Zone (TZ)• Trips PWM outputs• Edge blanking• Current mode control

Counter Compare Module (CC)• Four independent comparators• Controls PWM duty cycle

Action Qualifier (AQ)• Constructs PWM patterns• Generates ADC SOC events• Generates PIE interrupts


Phase Control

17

• Phase is controlled between PWM modules by synchronising time-base counters.• In this example, PWM1 generates a SyncOut pulse on a CNT = Zero event. PWM2

receives the pulse at its SyncIn terminal and loads a phase offset of 200 into its TBCTR.• Adjustment of phase offsets can be done at any time without corrupting the waveforms.

Compare Unit

18

TBCTR

Period

CMPD

CMPA

Zero

PRD

CBu

CCd

CAu CAd

ZROtime

CMPCCBd

CMPB

CDd

CCu

CDu

ZRO

• The compare unit allows up to four separate thresholds to be placed on the TB count.

• Events can be specified on any time-base counter threshold crossing.

• Compares C & D can be used to generate SOC events and interrupts.

• Compares A & B can also be used to switch PWM waveform edges.

The Compare Unit allows events to be positioned at specific instants in the timing pattern. These events can subsequently be associated with specific actions such as PWM edges or ADC sample triggers.


Action Qualifier

19

Zero(ZRO)

Z

CMPA(CAu)

CMPB(CBu)

CA

CB

Period(PRD)

CMPA(CAd)

CMPB(CBd)

CA

CB

P

TBCTR(Up)

equals:

TBCTR(Down)equals:

S/W force SW

Z

CA

CB

P

CA

CB

SW

Z

CA

CB

P

SW

CA

CB

ZT

CBT

PT

CAT

SW

T

CBT

CAT

Nothing Clear Lo Set Hi ToggleEvents Actions Triggers

ADC-SOCInterrupt

ZA

CAA

CBA

PA

ZI

CAI

CBI

PI

CAI

CBI

CAA

CBA

CMPC(CCu)

CMPD(CDu)

CCA

CDA

CCI

CDI

CMPC(CCd)

CMPD(CDd)

CCA

CDA

CCI

CDI

T2 T2 T2 T2

T

T1 T1 T1 T1

T

SW

ASW

I

T1(T1u)

T1A

T1I

T2(T2u)

T2A

T2I

T2 T2 T2 T2

T

T1 T1 T1 T1

TT1

(T1d)T1A

T1I

T2(T2d)

T2A

T2I

Each event can be assigned a markerfrom this table to identify which actionsshould be taken.

Trip inputs T1 & T2 come fromcomparator threshold crossings.These are asynchronous events usedin current mode control.

Software can force any action at anytime.

PWM patterns can be constructed byplacing the desired event markers on atiming diagram. These in turn are bitsettings in the Action Qualifier controlregisters.

Basic PWM Example

20

In this example, an asymmetrical up-count timebase is used to generate two PWM waveforms at the same frequency but with different duty cycles.

CMPA and CMPB are adjusted to control the trailing edges of each PWM waveform.


PWM ExampleIn this example, a symmetrical up-down count timebase is used to generate complementary pair PWM waveforms with dead-band and independent control of leading and trailing edges.

CMPC is used to position a SOC trigger for the ADC shortly after each rising edge.

An interrupt is triggered at each counter zero match to modulate the edges. 21

Dead-Band Sub-Module

22

The Dead-Band sub-module inserts delays on rising and falling PWM edges to prevent "shoot-through" in power toplogies which use complementary PWMs.

Two 14-bit timers are double edge clocked to independently adjust rising and falling edge delays with high precision.


Dead-Band Waveforms

23

Dead-Band may be applied in several different forms, depending on the polarity required by the external gate drivers. "Active High Complementary" (shown here with symmetric mode PWM) is the most common.

PWM1A

PWM1B FED

RED

FED

RED

CA CACACA

TBCTR

AP

AP

TBPRD

CMPA

ZI

ZI

Three Phase Inverter

24

• Single & multi-phase inverters used in motor control & grid tied applications

• Fixed switching frequency (10 - 20kHz typ.)

• Duty cycle of each leg modulated to produce sinusoidal output current

• PWM waveforms synchronized with zero phase shift


PWM Waveforms - Inverter

25

En SyncIn

SyncOut

CNT=ZeroCNT=CMPB

X

Phase Reg

Master

En SyncIn

SyncOut

CNT=ZeroCNT=CMPB

X

Phase Reg

Slave

En SyncIn

SyncOut

CNT=ZeroCNT=CMPB

X

Phase Reg

Slave

1

Ext Sync In(optional)

2

3

EPWM1A

EPWM1B

EPWM2A

EPWM2B

EPWM3A

EPWM3B

EPWM1A

CA CACBA

CA CACBA

CA CACBA

EPWM1B

EPWM2A

EPWM2B

EPWM3A

EPWM3B

CA CACBA

CA CACBA

CA CACBA

ZI

ZI

FED

RED

FED

RED

FED

RED

FED

RED

Multi-Phase Interleaved Converter

26

• Used in high current DC/DC supplies (e.g. server)

• Each of n phases is phase shifted by 360/n deg.

• Each phase is duty cycle modulated complementary pair PWM with dead-band

• Interleaving reduces ripple amplitude and increases ripple frequency


PWM Waveforms - MPI

27

P CA P PCA

EPWM1A

CA P CAP

CACA P

CBA

CBA

CBA

EPWM2A

EPWM3A

P

120 deg.

240 deg.

PI

PI

PI

Pulse Center

En SyncIn

SyncOut

CNT=Zero

CNT=CMPB

X

0 deg.

TBPHS

En SyncIn

SyncOut

CNT=Zero

CNT=CMPB

X

120 deg.

TBPHS

En SyncIn

SyncOut

CNT=Zero

CNT=CMPB

X

240 deg.

TBPHS

1

2

3

EPWM1A

EPWM1B

EPWM2A

EPWM2B

EPWM3A

EPWM3B

2-Phase Boost PFC

28

EPWM1A EPWM1B

VDC_busVrect

• Inter-leaved boost converter common in Power Factor Correction applications• Reference sinewave generated from ACin. Duty cycle adjusted to make Iin

follow reference.• Inter-leaving reduces ripple amplitude and increases ripple frequency• Two parallel boost converters typically preceded by (full bridge) rectifier• Current typically shared equally between phases


PWM Waveforms - Boost PFC

29

• 2-phase implementation needs only one PWM module

• Symmetrical mode time-base• Interrupt on zero match• CMPA & B control duty cycles

Half H Bridge

30

• Common in off-line converters & telecom rectifier applications below 1kW

• One PWM pair with variable duty cycle

• One end of primary held at VDC_bus/2 if capacitor leakages equal

• Switches other end between 0V and VDC_bus

• Switch-on times of each transistor must be equal to prevent "stair-casing"


PWM Waveforms - HHB

31

• Symmetrical mode time-base• Interrupt on zero match• CMPA & B control duty cycle• Dead-band on switch• CMPC & D control ADC sample points

Phase Shifted Full Bridge

32

• Used in telecom rectifier applications over about 1kW• Two complementary pair PWMs with fixed 50% duty cycle• Phase shift • Each of n phases is phase shifted by 360/n deg.• Each phase is duty cycle modulated complementary pair PWM with dead-band• Interleaving reduces ripple amplitude and increases ripple frequency


PWM Waveforms - PSFB

33

CA

PowerPhase

PowerPhase

CBA

Z Z CACBA

Z

RED

FED

CAZ Z CA Z

EPWM1A

EPWM1B

EPWM2A

EPWM2B

RED

FED

variable

ZI

ZI

ZI

ZVStransition

ZVStransition

CBA

CBA

En SyncIn

SyncOut

CNT=ZeroCNT=CMPB

X

Phase Reg

Master

En SyncIn

SyncOut

CNT=ZeroCNT=CMPB

X

VarPhase Reg

Slave

1

2

EPWM1A

EPWM1B

EPWM2A

EPWM2B

Resonant LLC

34

• Common switched power topology: telecom, solar, ballast, etc.• Primary side: complementary pair PWM with fixed 50% duty cycle• Frequency modulated topology: up to 1MHz common• Secondary side synchronous recitification• Control interrupt runs a lower rate (10kHz typ.)


PWM Waveforms - LLC

35

P CA P PCA

EPWM1A

CA

CBA

EPWM2A

EPWM3A

Pulse Center

En SyncIn

SyncOut

CNT=Zero

CNT=CMPB

X

0 deg.

TBPHS

En SyncIn

SyncOut

CNT=Zero

CNT=CMPB

X

0 deg.

TBPHS

En SyncIn

SyncOut

CNT=Zero

CNT=CMPB

X

0 deg.

TBPHS

1

2

3

EPWM1A

EPWM1B

EPWM2A

EPWM3A

CBA

EPWM1B

CA CACB CB

CB CA CB

FED

RED

Multi-Phase Applications

36

In multi-phase frequency modulated topologies, period, duty and phase must all be updated at a single point. Update delay between channels can be disastrous. Multiple registers in different PWM modules can now be configured to update on the same trigger.

Global & One Shot Reload

In multi-phase applications which use a fixed phase, frequency updates must be synchronised across PWM modules. A single register write can now be applied simultaneously across multiple modules.

Global Register Writes

INT INT

New PRD1 and PRD2 calculated

New PRD calculated here. TBPRD1 is updated! However, TBPRD2 could not

be updated before TBCNT2 = 0!!!

New PRD takes effect

ePWM1 time base

ePWM2 time base

Control loop trigger

Disastrous!!!


Power Control Schemes

37

+_Vref PWM

ADC

2P2Z PowerStage

IL

VoutDAC

ADC

+_Vref

+

_2P2Z PWM

ADC

2P2ZPowerStage

IL

Vout

ADC

Vref+

_2P2Z PWM

PowerStage Vout

Voltage Mode Control• Vout sense, 1 voltage loop controller,• Different power topologies• Controller regulates: PWM duty, phase shift (PSFB), or

frequency (LLC) in order to regulate Vout.

Average Current Mode Control,• Diverse power topologies• Vout sense, 1 voltage controller• Average current sense, 1 current loop controller

Output inductor current (forward, buck), Input inductor current (IL PFC),TFMR primary/secondary current (FB, HB)Switch current (BL PFC)

• Voltage controller sets average current command to regulate Vout.

• Current controller adjusts PWM duty/phase/frequency to track the average current command from voltage controller.

Peak Current Mode Control,• Mostly used in isolated power topologies• Vout sense, 1 voltage controller• Voltage controller output with slope compensation sets peak

current threshold• Peak current sense (output inductor, input inductor, TFMR)• Internal comparator controls PWM duty cycle

PCMC Block Diagram

38

• Current mode control achieves wider bandwidth compared with voltage mode control

• Desired control is average current, but need to filter ripple reduces bandwidth

• Peak Current Mode Control offers best combination of bandwidth and performance


Comparator Sub-System

39

Multiple comparator sub-systems enable several peak current control loops to be implemented in parallel.

The digital ramp generator supports slope compensation.

Programmable output filters prevent spurious glitches from tripping PWMs in electrically noisy environments.

PWM outputs can be optionally tripped on comparator edges.

PWM Trip: One-Shot Mode

40

IinIsetSD

PWM1A

PWM1A

PWM1B

PWM2A

PWM2B

PWM3A

PWM3B

Motor(3 ph)

Iin

HiZ

HiZ

Action onFault

time

PWM action on trip programmable

for each module via protected

registers

PWM must be reset by software

Over-current condition trips PWM


PWM Trip: Cycle-by-Cycle Mode

41

Over-current condition causes PWM shut-downCycle-by-cycle mode

enable peak current control

PWM action restored automatically on zero

match

Delayed Trip

42

Ideal peak current mode control uses cycle-by-cycle mode to trip PWM when load current crosses comparator threshold.


Delayed Trip - PSFB

43

PWM timings for peak current mode control of a Phase Shifted Full Bridge converter. Delayed trip needed on bothtransitions of pair Q2, Q3.

Switching Transients

44

PWM switching edges often produce "glitches" on the measured current signal which in turn can cause spurious PWM tripping. In this scenario the converter cannot start up.

P P P

EPWM1B

Trip

EPWM1A

IthIL

TBCTR


Trip Blanking (1)

45

Rising edge blanking on comparator output prevents spurious glitches from tripping PWM. Blanking window size (TB) and offset can be configured for each PWM module.

RED

Delayed trip on channel B

P P P

EPWM1B

Trip

EPWM1A

IthIL

TBCTR

Blanking

FED

T1 T1

TB

Trip Blanking (2)

46

RED

Delayed trip on channel B

P P P

EPWM1B

Trip

EPWM1A

IthIL

TBCTR

Blanking

FED

T1 T1

TB

Toffset

Alternatively, we can invert and offset the blanking window to restrict the interval in which trip events take effect.


Open Loop Instability

47

In peak current mode control we cannot operate at duty cycles of over about 50% without causing an open loop instability.

Current rise and fall slopes are approximately equal in the nominal and perturbed cases, but the constant period means the error will theoretically increase when D > 0.5. The current error at end of each PWM period is:

1

201 m

mII

P P

EPWM1B

EPWM1A RED

Ipk

I0

FED

T1 P P

RED

FED

T1

Current perturbation

I1I0 I1

D < 0.5 D > 0.5

m1

m2

m1

m2

Sub-Harmonic Oscillation

48

Without Slope Compensation With Slope Compensation

This type of open loop instability may manifest itself as sub-harmonic oscillations in the current waveforms.

The solution is to increase the rate at which the measured current approaches the comparator threshold. On C2000, we achieve this by super-imposing a decreasing slope on the comparator reference; a technique known as slope compensation.


Slope Compensation

49

EPWM1B

EPWM1A

P P

RED

FED

T1

Current perturbation

I0 I1m1

m2

Ith m

The instability can be prevented by adding slope to the trip threshold of the comparator, called slope compensation.

To guarantee current loop stability, the slope of the compensation ramp (m) must be greater than half the down-slope of the current waveform.

mmmmII

1

201

Slope Compensation on C28x

50


2. Summary

51

• PWM Generation– PWM sub-modules– Basic PWM patterns

• Power Topologies– 3 phase inverter– Multi-phase interleaved & boost PFC– Resonant LLC– Full & half-bridge topologies– Multi-phase applications

• Peak Current Mode Control– Delayed Trip– Blanking– Slope compensation

3. Closed Loop Control

52







Digital Transformations

53

Analogue control systems are generally well understood. Plant and feedback subsystems are modelled using Laplace transforms and a compensator designed to meet frequency or transient requirements.

Digital control systems comprise "samplers" and "holds", which form the boundaries between the continuous time and discrete time domains. The compensator operates in discrete time and is therefore represented by a z (rather than Laplace) transform.

We will consider an "emulation" design approach in which a continuous time compensator is first designed and then transformed into an equivalent discrete time form.

Transfer Functions

54

)(...))(()(...))(()(

21

21

cncc

cmccs pspsps

zszszsksF

An equivalent sampled data system can be found using a discrete transformation, which yields a transfer function in the complex variable z.

A linear continuous time system may be represented in transfer function form as

)(...))(()(...))(()(

21

21

dndd

dmddd pzpzpz

zzzzzzkzF

• Poles & zeros are in different positions in the complex plane

• The relative degree may not be the same

• Dynamic performance is different

Comparing the continuous time and discrete time representations of the same system:


The Tustin Transform

55

The Tustin transform allows us to approximate the z-transform directly from the Laplace transform by making the substitution

112

zz

Ts

The exact relationship between continuous and discrete transfer functions is

• The Tustin transform is easy to apply and performs well.

• Phase effects from computation & sampling delays must be accounted for separately.

sTez

Once we have an equivalent transfer function in terms of z, the time shifting property of the z transforms provides the difference equation.

)()( zfzknf kZ

Frequency Response

56

The frequency response of a discrete time system may be represented in Bode plot form, however the maximum unique frequency is limited by the sampling theorem. Typically only those frequencies below the Nyquist limit ( N) are shown.

Continuous time

Discrete time-20

0

20

40

60

80

Mag

nitu

de (d

B)

102

103

104

105

106

107

108

-225

-180

-135

-90

-45

0

45

Phas

e (d

eg)

Frequency (rad/s)N

Notice that the response of the discrete time system typically exhibits greater phase lag. This is due to sample-to-output delay inherent in any digital control system.


Design Example - 1

57

Step 1: Determine the plant transfer function

In Continuous Conduction Mode (CCM) the buck output stage has transfer function

3132321322

332)(RRLRCRRRCRsRRLCs

RRsCRsG

Inserting the passive component values for the workshop board, we obtain

L = 0.9 HC = 471 FR1 = 2.2 mR2 = 0.6 mR3 = 1

002.110219.210252.4110826.2)( 6210

7

ssssG

Design Example - 1a

58

Frequency (rad/s)10

310

410

510

610

710

8-180

-135

-90

-45

0

Phas

e (d

eg)

-150

-100

-50

0

50

Mag

nitu

de (d

B)

Double pole from LC filter

Zero from ESR

The plant frequency response exhibits a well-defined peak in the magnitude curve from the LC filter, and a high frequency zero from ESR of the output capacitor.


Design Example - 2

59

Step 2: Design the analogue compensator

33212

21

33122

131

31

1

11

)(

CRs

CCRCCss

CRRs

CRs

CRRRRsF

The transfer function of the classical type III compensator is

21

21)(pp

zzs sss

ssAsF

Pole & zero frequencies are selected using any of the established design techniques.

Design Example - 2a

60Frequency response plot of open loop with analogue compensator.

103 104 105 106 107 108-180

-135

-90

-45

0

Frequency (rad/s)

Phas

e (d

eg)

-80

-60

-40

-20

0

20

40

60

Mag

nitu

de (d

B)

Complex zero pair

HF poles

Integrator

PM = 70.1 deg. @ 87.2 kHz

Slope at cross-over = -1


Design Example - 3Step 3: Transform the compensator into discrete time

The digital transfer function can be formed using a Tustin transformation:112

zz

Ts

21

21

112

112

112

112

112

)(pp

zz

s

zz

Tzz

Tzz

T

zz

Tzz

TAzF

After some algebra we arrive at the third order digital transfer function

21

21)(pp

zzs sss

ssAsF

The 0Hz gains of the transfer functions must be matched: 10 )()( zs zFsF

33

22

11

33

22

110

1)(

zazazazbzbzbbzF

61

Design Example - 3a

After a lot of algebra, the coefficients turn out to be:

32

32322

1 22212

pp

pppp

TTTT

a

32

32322

2 22212

pp

pppp

TTTT

a

32

323 22

22

pp

pp

TTTT

a

3221

113210 222

22

ppzz

zzppp

TTTTT

b

3221

21212

3211 222

234

ppzz

zzzzppp

TTTTT

b

3221

21212

3212 222

234

ppzz

zzzzppp

TTTTT

b

3221

213213 222

22

ppzz

zzppp

TTTTT

b

33

22

11

33

22

110

1)(

zazazazbzbzbbzF

11

11)(

32

211

pp

zzp

ss

ss

ssF

Using the Tustin method, we have transformed a transfer function in s to one in z.

62


Design Example - 3b

63Frequency response comparison of analogue (blue) and digital (green) compensators. fs = 1MHz.

Mag

nitu

de (d

B)

Phas

e (d

eg)

Design Example - 4

64

Step 4: Determine the difference equation for the compensator

33

22

11

33

22

110

1)()()(

zazazazbzbzbb

zezuzF

Normalising to the highest power of z in the denominator

u(z) = b0 e(z) + b1 z -1 e(z) + b2 z-2 e(z) + b3 z-3 e(z) - a1 z-1 u(z) - a2 z-2 u(z) - a3 z-3 u(z)

To find the difference equation we simply apply the shifting property of the z transform

u(k) = b0 e(k) + b1 e(k – 1) + b2 e(k – 2) + b3 e(k –3) - a1 u(k – 1) - a2 u(k – 2) - a3 u(k – 3)

)()( zfznkf nZ

It only remains to code and test the controller algorithm.


Frequency Response Analyzer

65

The Software Frequency Response Analyzer (SFRA) can measure the frequency response of the control loop without disrupting normal operation.

The presence of the injected frequency is detected at various points in the loop and its magnitude and phase measured as the frequency is swept between specified limits. Plots of gain and phase vs. frequency can then be constructed from the collected data.

Plant TF:

Open loop TF:

uyG

ry

FGFG

1

eyFG

Closed loop TF:

SFRA Principle of OperationAt each frequency, a low amplitude sinusoidal disturbance is injected into the loop. The magnitude and phase of the extracted signal is measured using a single point DFT.

1

0

1

0

2sin)(2cos)()(N

n

N

nk

Nnnxjk

NnnxX

The data is stored and the measurement repeated with a different excitation frequency. Once we have swept through all the desired frequency points the Bode plots can be constructed.

1

0

2exp)()(N

nk

NnjnxX

66


C2000 DP Library

67

The C2000 Digital Power (DP) library is a collection of hand optimised assembly macros which are typically executed in a single assembly Interrupt Service Routine.

Integrating SFRA with DP Library

68

When used with the assembly based C2000 Digital Power library, the SFRA and library modules must be called from the same C interrupt routine.

The assembly ISR must be declared and called from within the main C file.


Plant Measurement

69

Open Loop Measurement

70


SFRA Summary

71

• Extracts closed loop and open loop transfer functions by injecting asinusoidal excitation and measuring the response.

• Can be used to periodically measure gain and phase margins which candetermine the health of the power stage. This allows early detection ofpossible fault conditions and reduces costly "down-time".

• Frequency response data can then be used to design the compensatorand evaluate stability of the system.

• Entirely software driven - no external equipment required.

• Available at: www.ti.com/tool/sfra

PWM Resolution in Bits

72

PWM resolution is typically expressed as a percentage, however in digital control systems it is often more convenient to work in binary "bits". PWM resolution in bits (N1) is related to PWM and CPU frequencies as follows.

PWM Freq Resolution(kHz) (bits) (%)

100 10.0 0.1150 9.4 0.2250 8.6 0.3500 7.6 0.5750 7.1 0.81000 6.6 1.01500 6.1 1.5

2000 5.6 2.0

For a CPU clock frequency of 100 MHz the table below lists the PWM resolution in bits and percent.

PWM

CPU

ffN 21 log

Recall, change of logarithmic base can be computed from the formula:

axx

b

ba log

loglog


Data Converter Gain

73

22maxN

bb12

maxN

uu

bK ADC

1 uKPWM

• Converter gains are related to quantization limits by:

• End-to-end controller gain is KADC | F(z) | KPWM

• Quantization takes place at each continuous/discrete boundary. Resolution limits can be referred to the continuous domain by:

Resolution Based Limit Cycles

74

Out

put

Out

put

• Steady-state limit cycles may appear if the feedback resolution ( y) is worse than the control resolution ( u)

• Limit cycle prevention requires increased control resolution.


Limit Cycle Condition

75

21 22maxmaxNN

uku

22maxN

bb

12maxN

uu

To prevent a limit cycle condition we must have: u < b

In steady state, control and sense quantities are related by

Control resolution is:

Sense resolution is:

This gives the inequality

kNN 221 log

maxmaxmax |)0()0(| ukuHGb

21 212 NN

k• To avoid a steady-state limit cycle, control effort resolution must satisfy the inequality

Duty Cycle Utilisation

76

PWM resolution issues are compounded when less than 100% of the duty cycle is available for control. For example, the input-output voltage range of the buck converter defines the maximum duty cycle possible.

Vout0.8 1 1.2 1.8 2.5 3.3 5

Vin14 4.1 3.8 3.5 3.0 2.5 2.1 1.512 3.9 3.6 3.3 2.7 2.3 1.9 1.310 3.6 3.3 3.1 2.5 2.0 1.6 1.09 3.5 3.2 2.9 2.3 1.8 1.4 0.88 3.3 3.0 2.7 2.2 1.7 1.3 0.77 3.1 2.8 2.5 2.0 1.5 1.1 0.56 2.9 2.6 2.3 1.7 1.3 0.9 0.3

Resolution Loss in bits


PWM Edge Resolution

PWM edge resolution is fixed by the period of the time-base clock.

At high switching frequencies (greater than about 200kHz) loss of edge resolution can lead to limit cycles.

SYSCLK

PWM

TTN 21 log

PWMx

CMPA

CMPA = n + 1

CMPA = n

PWMx

Z CA

TBPRD

TBCTR

Z

Desired Duty Cycle

TPWM

TSYSCLK

77

High Resolution PWM

78

In high resolution mode edges can be positioned with an accuracy of approximately 150ps (Tmstep).

High resolution mode can be applied to duty cycle, period, or phase shift modulation.


Limit Cycle Example

79

Conventional PWM: 10ns edge resolution High resolution PWM: 150ps edge resolution

3. Summary

80

• Design Example– Discrete transformation– Basic buck controller design

• Software Frequency Response Analyzer– Online frequency response measurement

• Limit Cycle Issues– Limit cycle condition– PWM resolution


4. Control Law Implementation

81






PID Control

82

dttdekdektektu d

t

ip)()()()(

PID (Proportional + Integral + Derivative) controllers allow intuitive tuning of the transient response.

The parallel PID form is:

• The proportional term kp directly affects loop gain

• Integral action increases low frequency gain and reduces/eliminates steady state errors, however this can have a de-stabilizing effect due to increased phase lag

• Derivative action introduces a predictive type of control which tends to damp oscillation & overshoot but can lead to large control effort


PID Controller Emulation

83

The 2P2Z structure can be applied to emulate the behaviour of a PID controller. The transfer function of the "ideal" PID controller is:

di

p ksskksF )(

212

0

212

0)(zzzzzF

The 2P2Z coefficients are related to the PID gains and sample period (T) as follows:

The Tustin transformation allows us to find an equivalent z transform of this controller.

dd

ii

pp

kT

k

kTk

kk

1

2d

dip

dip

k

kkk

kkk

2

1

0

2

0

1

1

2

1

0

Common Controller Types

84

skkk di

p s

)s)(s(s)s)(s(

21

21

ppzzk p

)s)(s(s)s)(s)(s(

21

321

ppzzzk p

)s(s)s)(s(

1

21

pzzk p

)s(s)s(

1

1

pzk p

)2()1()()1()( 210 kebkebkebkuku

)2()1()()2()1()( 21021 kkbkebkebkuakuaku

)3()2()1()(

)3()2()1()(

3210

321

kebkebkebkeb

kuakuakuaku

)2()1()()2()1()( 21021 kkbkebkebkuakuaku

)3()2()1()(

)3()2()1()(

3210

321

kebkebkebkeb

kuakuakuaku

PID

Type II

Type III

2-Pole 2-Zero

3-Pole 3-Zero

Controller Transfer Function Control Law

The digital control law is a difference equation involving input & output data weighted by a set of coefficients derived from those of the transfer function.

Notice the similarities between the first three and the last two control laws: the structure is the same -only the coefficients are different.


3P3Z Control Law

85

322

13

0

322

13

0

)()(

zzzzzz

zezu

33

22

11

33

22

110

1)()(

zazazazbzbzbb

zezu

Normalizing for the term involving the highest denominator power ( 0) gives

Applying the shifting property of the z-transform term-by-term yields the difference equation

The second order discrete time transfer function is written

Re-arranging to find an expression for u(z)

u(z) = e(z) { b0 + b1 z -1 + b2 z-2 + b3 z-3 }- u(z) { a1 z-1 + a2 z-2 + a3 z-3 }

u(z) { 1 + a1 z-1 + a2 z-2 + a3 z-3 } = e(z) { b0 + b1 z -1 + b2 z-2 + b3 z-3 }

u(z) = b0 e(z) + b1 z -1 e(z) + b2 z-2 e(z) + b3 z-3 e(z) - a1 z-1 u(z) - a2 z-2 u(z) - a3 z-3 u(z)

u(k) = b0 e(k) + b1 e(k – 1) + b2 e(k – 2) + b3 e(k – 3) - a1 u(k – 1) - a2 u(k – 2) - a3 u(k – 3)

Control Law Computation

The discrete time control law can be represented graphically using blocks to represent the operations of addition, multiplication, and time delay.

Computing the 3P3Z control law involves performing seven multiplications and six additions.

u[0] = b0*e[0] + b1*e[1] + b2*e[2] + b3*e[3] - a1*u[1] - a2*u[2] - a3*u[3];

z-1 z-1

+

z-1 z-1

+ +

-a1-a2

b1 b2 b3

e(k-3)e(k-2)

u(k-2) u(k-1)

u(k)

z-1

+

z-1

-a3

b0

e(k)

u(k-3)

e(k-1)


86


C Example - 3P3Z Controller

// control law coefficients#define a1 xxxx#define a2 xxxx#define a3 xxxx#define b0 xxxx#define b1 xxxx#define b2 xxxx#define b3 xxxx#define K 0x5678 // PWM scaling factor#define PWMDUTY (volatile unsigned int *) 0x1234 // PWM duty register address

// variablesfloat Vref; // reference inputfloat AdcVal; // feedbackfloat e[3], u[3]; // e(k) = controller input, u(k) = controller output

// 3P3Z control lawvoid TypeIII_Calc(void){

e[0]= Vref - AdcVal; // servo erroru[0] = b0*e[0] + b1*e[1] + b2*e[2] + b3*e[3] - a1*u[1] - a2*u[2] - a3*u[3]; // control lawu[3] = u[2]; // delay line updatesu[2] = u[1];u[1] = u[0];e[3] = e[2];e[2] = e[1];e[1] = e[0];PWMDUTY* = u[0] * K; // new duty cycle

}

The following C code shows an example of how a type III controller might be implemented in software.

87

Control Loop Delay

88

CONTROLLERADCCS CRSUPERVISORY ACKDAC

CONTEXTSAVE

READADC

COMPUTENEW

CONTROLUPDATE

CONTROLLER

COMMS, WATCHDOG, ETC

ACKNOWLEDGEINTERRUPT

CONTEXTRESTORE

Need to determine the cycle count of this!

9 3 27 5 23 1 9+ + + + + + = 77 cycles?Example:

Control loop delay

time

Sam

ple

poin

t

ISR

beg

ins

ISR

end

s

Sam

ple

poin

t

Con

trolle

r u/d

A B C

ISR code

Other code

A + CCPU Bandwidth = A + B + C x 100%

Inte

rrupt

Di

Fixed by hardware

User configurable

Software dependent


Pre-Computation

Unknownat t = k-1

Can be pre-computed at t = k-1

u(k) = b0 e(k) + v(k – 1)

u[0] = b0*e[0] + v;

In C code:

e(k)

u(k)

b0

v(k-1) +


z-1

z-1

+ +

-a1-a2

b2 b3

e(k-2)

u(k-1)u(k)

v(k)

z-1

-a3

u(k-2)

+

b1

z-1e(k)e(k-1)

v(k) = b1 e(k) + b2 e(k – 1) + b3 e(k – 2) - a1 u(k) - a2 u(k – 1) - a3 u(k – 2)

89

C Example - Pre-Computation

// variablesfloat Vref; // reference inputfloat AdcVal; // feedbackfloat e[3], u[3]; // e(k) = controller input, u(k) = controller output

// compute 3P3Z control lawvoid TypeIII_Calc(void){

static float v;

e[0]= Vref - AdcVal; // servo erroru[0] = b0*e[0] + v; // note: sample-to-output delay reduced!PWMDUTY* = u[0] * K; // write new duty cycle

// pre-compute next partial resulttemp = b1*e[1] + b2*e[2] + b3*e[3] - a1*u[1] - a2*u[2] - a3*u[3]; // control law u[3] = u[2]; // delay line updatesu[2] = u[1];u[1] = u[0];e[3] = e[2];e[2] = e[1];e[1] = e[0];

}

Pre-computing the partial product using the known data allows the sample-to-output delay in the next sample period to be reduced.

90


Scaling

91

The controller operates on a "per unit" basis, so reference, feedback, and output variables must all be scaled to have a range of ±1.

Voltage Sense Scaling

92

2N

0

Vmax

0V

Vomax

0V

Vfbk VADC xb

Kd KADC

b

The quantity b is the smallest resolvable change in voltage at the ADC input:22

maxN

Vb

For a 3V input to a 12-bit converter, mVVb 732.023

12


PWM Gain

93

umax

0V

TBPRD

0

Voxu

KPWM

Quantization

94

Quantization is an effect which takes place when an analogue input is converter into digital form using an ADC with finite resolution.

Each sample potentially carries a quantization error of up to ±0.5 LSB of the converter.

A 12-bit converter is capable of representing 212 = 4096 discrete levels. If the input range is 3V, the quantization error is

40963V = 0.732mV

(Note: "round-to-nearest" conversion shown)


Floating Point Format

95

Example: 0x41200000 = 0 100 0001 0 010 0000 0000 ... 0000 bs e = 130 f = 2-2 = 0.25

Case 3 v = (-10)*2(130-127)*1.25 = 10.0

s eeeeeeee fffffffffffffffffffffff031 30 23 22

23 bit mantissa (fraction)8 bit exponent1 bit sign

Case 1: if e = 255 and f 0, then v = NaNCase 2: if e = 255 and f = 0, then v = [(-1)s]*infinityCase 3: if 0 < e < 255, then v = [(-1)s]*[2(e-127)]*(1.f)Case 4: if e = 0 and f 0, then v = [(-1)s]*[2(-126)]*(0.f)Case 5: if e = 0 and f = 0, then v = [(-1)s]*0

Normalizedvalues

The IEE754 single precision floating point format is a 32-bit binary sequence:

Floating Point Limitations

96

You cannot represent 10.000000238 with single-precision floating point

0x412000000 = 10.00000000010.000000238 – can’t represent!

0x412000001 = 10.000000950

The result is z gets rounded down to 10.000000000.

x = 10.0 (0x41200000)+ y = 0.000000238 (0x347F8CF1)

z = 10.000000238

Here is an example of a problem caused by limited floating point resolution:

Moral: Don't assume you can forget about numerical issues just because you're using a floating point processor.


Numerical Precision

97

Floating point number line:

0+ -0+ -

Note the non-uniform distribution along the number line

• Numeric precision is greatest near zero

• Less precision the larger the number gets

Advantage Exponent gives large dynamic range

Disadvantage Precision of a number depends on its exponent

Reading the ADC

98

#define AdcFsVoltage float(3.3) // ADC full scale voltage

float Result; // ADC result

void main(void)

{

// Convert unsigned 16-bit result to 32-bit float. Gives value of 0 to 4095.

// Scale result by 1/4096. Gives value of 0 to ~1.

// Scale result by AdcFsVoltage. Gives value of 0 to ~3.3.

Result = (AdcFsVoltage/4096.0)*(float)AdcResult.ADCRESULT0;

}

AdcResult.ADCRESULTx

x x x xx x x xx x x x0 0 0 0

32-bit float15 031

f f f ff f f ff f f ff f f fs e e e e f f fe e e e f f f f

ASM:I16TOF32

C:(float)

Compiler will pre-compute at build-time.No runtime division!


Typical Control Software Structuremain(){

// device init

1

1. Initialisation code runs once, on start-up, to setup device hardware and software variables.

}

while(1){

}

// sequencing

// communications

// monitoring

22. Infinite software loop performs non-time critical background tasks: comms, health monitoring, supply rail sequencing, ...

interrupt adc_isr(void){

}

// read ADC result

// control law

// modify PWM pattern

4

3. Hardware event such as ADC end-of-conversion (EOC) triggers interrupt synchronously with hardware.

4. Interrupt Service Routine executes time critical functions then returns program control to background loop.

3

99

Modular Software Architecure

100

The modular software concept enables control structures to be dynamically re-configured, simplifying development and enabling sophisticated control structures.

// module pointer declarationsextern volatile long Ref;extern volatile long Fdbk;...

// net declarationsvolatile long Vref = 0;volatile long Duty = 0;...

// assign connectionsRef = &Vref; Out = &Duty;In = &Duty;Fdbk = &Vout;Rlt = &Vout;

Step 1: declare terminals and net variables Step 2: connect net variables


Controlling Multiple Power Stages

Vref1

200 kHz200 kHz

Vout1

Voltage Controller

CNTL2P2Z

UoutRefFB

ADC

HWrslt0

Ch0

ADCDRV

DutyCmd1

EPWM

HWDuty

BUCKDRV

EPWM1A

Vin Vout1

BuckDRV

Synchronous Buck Power Stage #1

S-start / SEQ

Start / Stop trigger

S-start / SEQ

Vref2

Vout2

Voltage Controller

CNTL2P2Z

UoutRefFB

ADC

HWrslt0

Ch1

ADCDRV

DutyCmd2

EPWM

HWDuty

BUCKDRV

EPWM2A

Vin Vout2

BuckDRV

200 kHz

200 kHz

200 kHz

200 kHz

BG ISR

Synchronous Buck Power Stage #2

A typical digital power supply consists of multiple power stages, each controlled by an independent software module, and possibly all running at different rates.

101

System Management

102

Coeff - B2

Coeff - B1

Coeff - B0

Coeff - A2

Coeff - A1

Coeff set 3

Coeff - B2

Coeff - B1

Coeff - B0

Coeff - A2

Coeff - A1

Coeff set 2

UoutRefFB

Control“2P2Z”

Vset

Duty

VoltageFeedback

SSartSEQ

Delay

OutSlope

Target

Duty Clamp

Dead Band

Fault Trip

Coeff - B2

Coeff - B1

Coeff - B0

Coeff - A2

Coeff - A1

Coeff set 1

CoeficientTuning

TripZone

Vout MonitorDuty Monitor

Supervisory - BG Control Engine(s)

ADC

HWRslt

“ADC”DRV

EPWM

HWIn

“PWM”DRV

In addition to controlling the power switches, the software must also manage the configuration of the power system. Typically this is done in the backgound loop.


Multi-Mode Control

103

A-55.0

-50.0

-45.0

-40.0

I limit

Uo (V)

Iout(A)

Pmax= Rated PSU Output power

Curve for current versus voltage

-43.0V

-54.5V

I nom

-39.0V

Key Points• 3 compensators running in parallel• Cycle-by-cycle decision by H/O Mgr• Mixing Decision making with CLA

allows greater flexibility to solve problems

• Example:Seamless transition V-Pwr-I

seamlesstransition

• Constant Voltage

• Constant Current

• Constant Power

Control Law Accelerator (CLA)

• An independent CPU which operates in parallel with the main CPU

• Computes the control law with low latency

• Interacts directly with ADC and PWM modules

• Is a C programmable 32-bit floating-point CPU

104


Benefits of the CLA

105

CONTROL LAW

time

Sam

ple

Sam

ple

H/w

trig

ger

CPU

CLA

Con

trolle

r u/d

time

Sam

ple

Sam

ple

H/w

trig

ger

Con

trolle

r u/d

CPU

A/D Conversion

A/D Conversion

F2804x

MCU

Reduced control loop delay

2

3 CPU bandwidth increased

CONTROLLER ISR

1Reduced interrupt

latency / jitter

1

The Control Law Accelerator

106

• The Control Law Accelerator (CLA) is an independent 32-bit floating-point core

• CLA has an independent data and program buses

• CLA has access to control peripherals, including:

PWM, ADC results, GPIO, QEP, HRCAP, DAC, CMPSS

• Communication between CPU and CLA is through dedicated message RAM


Digital Power CLA Example

107

#include “CLA_Shared.h”

#pragma DATA_SECTION (VRef,“CpuToCla1MsgRAM");volatile float VRef;

#pragma DATA_SECTION(Duty,”Cla1ToCpuMsgRAM”);volatile float Duty;

#pragma DATA_SECTION(VFbk,”Cla1ToCpuMsgRAM”);volatile float VFbk;

CNTL2P2Z_CLA_C 2p2z;

interrupt void Cla1Task1 ( void ){

// Read the adc values and scale it to PUVFbk= ADCDRV_1ch_CLA_C(AdcResultRegs.ADCRESULT0);

// Read the reference set point & feedback2p2z.Ref = Vref;2p2z.Fbk = VFbk;

// compute the control outputCNTL_2P2Z_CLA_C(2p2z);Duty=2p2z.Out;

// write the new PWM duty cyclePWMDRV_1ch_CLA_C(EPwm1Regs,Duty,EPwm1Regs.TBPRD);

}…interrupt void Cla1Task8 ( void ){

Duty=0; VFbk=0;CNTL2P2Z_CLA_Init(2p2z);

}

#include “PWMDRV_CLA_C.h“#include “ADCDRV_CLA_C.h”#include “CNTL2P2Z_CLA_C.h”…..extern float Vref;

CLA-Tasks_C.cla

CLA-Shared.h

#include “CLA-Shared.h”…main(){…//CLA initialization here…}

C28x Code_main.c

4. Summary

108

• Pre-Computation– PID control– 2P2Z control example– Control loop delay

• Numerical Considerations– Scaling– Quantization– Floating point format

• The Control Law Accelerator– Software structure– System management


5. Design Resources

109






2-Phase Interleaved Boost PFC

110

Description• 750W Pout, 400V DC Bus• 90~264Vrms, 47~63Hz• 2 phase interleaved Boost PFC• Isolated JTAG

PWM-1

Piccolo-A

I2CSPI

UART

CPU32 bit

A

B

PWM-2 A

B

PWM-3 A

B

PWM-4 A

B

ADC12 bit

Vref

1

2

3

13

1

2

3

4

5

6

7

8

• High Efficiency (LL, HL – 94%, 96%)• PF 0.99, HL Light Load - 0.92(Min)• 200kHz Switching Frequency• Fast Vin Feed Forward• Adaptive current loop, Non-linear voltage loop• OVP, Soft-start, Inrush current limit• Input RMS current, voltage, power &

frequency measurement


Half Bridge Resonant LLC

111

Description• 375~405V DC in / 12V DC out / 300W• Half Bridge + Synchronous Rectification• Operating Frequency (100~130KHz)• Resonant Frequency, f0 (~130KHz)• 93.7% peak efficiency, 91.3% full load

PWM-1

Piccolo-A

I2CSPI

UART

CPU32 bit

A

B

PWM-2 A

B

PWM-3 A

B

PWM-4 A

B

ADC12 bit

Vref

1

2

3

13

1

2

3

4

5

6

7

8

Phase Shifted Full Bridge

112

Description• 300~400V DC input / 12V output• ZVS Phase Shifted Full Bridge• Synchronous Rectifiers on output• 600W • Isolated JTAG

Control Methods- Peak Current Mode- Optimized Sync. Rectification Control- Voltage Mode- Adaptive ZVS- Switching and Sampling Frequency: 150KHz


Solar Micro-Inverter

113

• MPPT DC-DCHigh Gain Active Clamp Flyback with Secondary Voltage MultiplierPanel Input Voltage 28-35V typical, 44V maxOutput Voltage 250-400VMax input power 300W 100kHz PWM switching frequency with HR

• DC-AC Inverter220V, 50Hz and 110V, 60Hz AC connection50kHz PWM Switching Frequency Max output power 280W/220V, 140W/110V>95% efficiency and <4% THD at 50% load

Bi-Directional DC-DC Converter

114

Markets / EEs• Automotive (HEV, EV)• General digital power e.g. Industrial,

battery back-up systems.

Description• 400V 12V bi-directional pwr flow• Isolated design / 400W• Phase shifted FB (400V 12V) with SR

operated with VMC/PCMC• Push-Pull (12V 400V) with active

clamping operated with ACMC/VMC• PWM frequency – 100 KHz• Isolated CAN bus


Digital Power Training

115

• Biricha Digital Power Design Workshops3-day hands-on workshops on design of digitally controlled power systemshttp://www.biricha.com/

• C2000 Product Training1-day and 3-day hands-on training on C2000 MCUshttp://focus.ti.com/general/docs/traininghome.tsp

• Digital Power Supply workshop1-day hands-on workshops on digital power supplieshttp://processors.wiki.ti.com/index.php/C2000_DPSWorkshop

• Control Theory Seminars1-day and 2-day technical seminars in control theoryhttps://sites.google.com/site/controltheoryseminars/

Recommended Reading

116

R.Poley, Control Theory Fundamentals,CreateSpace, 2014

CONTROL THEORYFUNDAMENTALS

Richard Poley

Second Edition

J.J.DiStefano, A.R.Stubberud & I.J.Williams, Feedback & Control Systems, Schaum, 2011

G.F.Franklin, J.D.Powell & M.L.Workman, Digital Control of Dynamic Systems,

Addison-Wesley, 1998

J.Schwarzenbach & K.F.Gill, System Modelling & Control,

Edward Arnold, 1992


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