cache design for an alpha microprocessor

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1 University of Texas at Dallas Department of Electrical Engineering EEDG 6304 – Computer Architecture Project #1 “CACHE DESIGN” Team Members Bharat Biyani (2021152193) Shree Viswa Shamanthan L D (2021180127)

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DESCRIPTION

Fine tuned the cache hierarchy of an Alpha microprocessor for three individual benchmarks namely GCC,ANAGRAM and GO by modifying various cache design parameters like cache levels, cache types ( in case of more than one level of cache), sizes, associativity, block sizes and block replacement policy. compared the performance of individual benchmarks for different configurations based on CPI and COST function.

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Page 1: Cache Design for an Alpha Microprocessor

1

University of Texas at Dallas

Department of Electrical Engineering

EEDG 6304 – Computer Architecture

Project #1

“CACHE DESIGN”

Team Members

Bharat Biyani (2021152193)

Shree Viswa Shamanthan L D (2021180127)

Page 2: Cache Design for an Alpha Microprocessor

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TABLE OF CONTENTS

Sr. No. Description Page No.

1 INTRODUCTION 3

2 SIMULATION APPROACH 4

3 CPI FORMULAE 4

4 PART 2: FIND CPI 5

5 PART 3: OPTIMIZE CPI FOR EACH BENCHMARK 7

6 PART 4: DEFINE COST FUNCTION 10

7 PART 5: OPTIMIZE CACHE FOR PERFORMANCE/ COST

11

8 CONCLUSION 14

9 APPENDIX 15

Page 3: Cache Design for an Alpha Microprocessor

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1. INTRODUCTION

Caches are used by the central processing unit (CPU) of a computer to reduce the

average time to access memory. The cache is a smaller, faster memory which stores copies of

the data from frequently used main memory locations. Hence Caches form the integral part of a

microprocessor design. Any cache design is proven to the industry/customers through their

benchmarks. The main aim of this project is to analyze the cache performance of an Alpha

microprocessor for 3 individual benchmarks (GCC, Anagram Alpha and Go) with following

design constraints.

The cache design parameters that can be tuned in our example are

Cache Levels: One or two levels, for data and instruction caches

Unified caches: Selection of separate vs. unified instruction/data caches

Size: Cache size is the most important factor to avoid capacity misses.

Block size: Block size of the cache, usually 64 or 32 bytes.

Block replacement policy: Selection between FIFO, LRU and Random.

Associativity: Selection of cache associativity (e.g. direct mapped (1-way set associative), 2-way set associative, etc.)

While larger caches generally mean better performance, they also come at a greater cost.

Thus, sensible design choices and trade-offs are required. So we are going to use the cost

function to identify the optimal configuration.

Page 4: Cache Design for an Alpha Microprocessor

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2. SIMULATION APPROACH

Three benchmarks (GCC, Anagram and Go) were selected and run on the Simplesim3.0 simulation tool. Multiple techniques are applied to achieve the optimal configuration. The following steps were carried out in order to determine the optimal configuration:

1. Select a particular benchmark. 2. Select one cache structure combination from these 3 cases for each benchmark

L1 Separate - L2 Separate

L1 Separate - L2 Unified

L1 Unified - L2 Unified

Where L1 and L2 are Levels of Cache. 3. For each cache structural combination; vary the page replacement policy iteratively

(LRU, FIFO and Random) 4. For each cache structural combination and page replacement policy; vary the block size

values iteratively (32Kb, 64Kb) 5. For each cache structural combination, page replacement policy and block size; vary

associativity iteratively (1, 2, 4, 8) 6. Calculate the CPI for each setting (shown below) 7. Repeat steps 1 to 6 for all possible combination of configurations. 8. Calculate the cost for each cache configuration using the cost function (shown on page

no. 10). 9. Compare the results and annotate graphically Optimal cache configuration for each

benchmark, as well as all benchmarks combined is selected with the help of the defined

cost function.

3. CPI FORMULAE

3.1. L1 separate and L2 separate CPI = CPI ideal + 6 * ( L1InsMissRate * %L1Ins + L1DataMissRate * %L1Data) + 50 * ( L2InsMissRate * %L2Ins + L2DataMissRate * %L2Data ) 3.2. L1 separate and L2 unified CPI = CPI ideal + 6 * ( L1InsMissRate * %L1Ins + L1DataMissRate * %L1Data) + 50 * ( L2MissRate * %L2Data ) ) 3.3. L1 unified and L2 unified CPI = CPI ideal + 6 * ( L1MissRate * ( %L1Data) ) + 50 * ( L2InsMissRate * ( %L2Data ) ) ) Where, %LxIns = Instruction Accesses for Lx /Total Memory Accesses %LxData = Data Accesses for Lx /Total Memory Accesses

Page 5: Cache Design for an Alpha Microprocessor

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4. PART 2: FIND CPI

In this part, the CPI for the 3 individual benchmarks was calculated. Our baseline configuration will be the Alpha 21264 EV6 configuration:

Cache Levels: Two Levels.

Unified caches: Separate L1 data and Instruction cache, unified L2 cache.

Size: 64KB Separate L1 data and instruction caches, 1MB unified L2 cache.

Block size: 64 bytes

Block replacement policy: FIFO

Associativity: 2- way set associative L1 cache, Direct-mapped L2 cache.

------------------------------------------------------------------------------------------------------------------------------- 4.1. GCC Benchmark Total Memory Accesses = 337327101 Number of L1 Instruction cache accesses = 337327101 Number of L1Data cache access = 124102799 Number of L2 access = 3330118 L1 Ins miss rate = 0.0047, L1 Data miss rate = 0.0106, L2 miss rate = 0.1311 CPI = CPI ideal + 6 * ( L1InsMissRate * %L1Ins + L1DataMissRate * %L1Data) + 50 * ( L2MissRate * %L2Data ) ) CPI = 1 + 6 * (0.0047 * (337327101/337327101) + 0.0106 * (124102799/337327101)) + 50 * (0.1311 * (3330118/337327101))) CPI = 1.11631 ---------------------------------------------------------------------------------------------------------------------------- 4.2. Anagram Benchmark Total Memory Accesses = 25724898 Number of L1 Instruction cache accesses = 25724898 Number of L1Data cache access = 11182060 Number of L2 access = 92401 L1 Ins miss rate = 0, L1 Data miss rate = 0.0048, L2 miss rate = 0.3191

Page 6: Cache Design for an Alpha Microprocessor

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CPI = 1 + 6 * (0 * (25724898/25724898) + 0.0048 * (11182060/25724898)) + 50 * (0.3191 * (92401/25724898))) CPI = CPI ideal + 6 * (L1InsMissRate * %Ins + L1DataMissRate * %Data) + 50 * (L2MissRate * %Data)) CPI = 1.06983 ---------------------------------------------------------------------------------------------------------------------------- 4.3. GO Benchmark Total Memory Accesses = 545823664 Number of L1 Instruction cache accesses = 545823664 Number of L1Data cache access = 213791111 Number of L2 access = 1021478 L1 Ins miss rate = 0.0013, L1 Data miss rate = 0.0010, L2 miss rate = 0.0907

CPI = CPI ideal + 6 * (L1InsMissRate * %Ins + L1DataMissRate * %Data) + 50 * (L2MissRate * %Data)) CPI = 1 + 6 * (0.0013 * (545823664/545823664) + 0.0010 * (213791111/545823664)) + 50 * (0.0907 * (1021478/545823664))) CPI = 1.01864

CONCLUSION FOR PART 2:

Sr. No. Benchmark CPI

1 GCC 1.11631

2 Anagram 1.06983

3 GO 1.01864

Page 7: Cache Design for an Alpha Microprocessor

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5. PART 3: OPTIMIZE CPI FOR EACH BENCHMARK Given a two-level cache hierarchy, 128KB available for L1 cache and 1MB available for L2 cache, in order to find the optimal configuration (in terms of achieved CPI) for each benchmark, Decision must be made between unified/separate caches, associativity, replacement policy etc. 5.1. Assumptions

1. Both L1 and L2 use the same block size (e.g. if L1 cache uses 32KB, L2 cache also uses 32KB). We have considered only 32KB and 64KB block sizes for both L1 and L2 in order to find the optimal configuration. Having higher block size would decrease the number of lines in the cache and increases the miss penalty.

2. L1 block size cannot be larger than L2 block size. 3. Associativity values range from 1, 2, 4 and 8. Design does not consider associativity

more than 8 because they have much higher cost for a very little performance improvement in reality. Directly mapped design (1-way associative) is also taken into consideration even though it gives poor performance, but it will help in analyzing the design better.

4. While optimizing, only three replacement policies are considered Random, FIFO (First IN First OUT) and LRU (Least Recently Used).

The below graphs show the CPI plotted against various configuration for L1 Separate-L2

separate, L1 Separate L2 unified, and L1 & L2 unified for all three benchmarks

5.2. GCC Benchmark

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Page 8: Cache Design for an Alpha Microprocessor

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5.3. Anagram Benchmark

5.4. GO Benchmark

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Page 9: Cache Design for an Alpha Microprocessor

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CONCLUSION FOR PART 3:

The graphs plotted above helps us to decide the design choices. Optimum CPI in each case is as

follows:

Sr. No. Benchmark Configuration Block Size (In Bytes)

Replacement Policy Associativity

Optimal CPI

L1 L2 L1 L2 L1 L2

1 GCC L1L2unified 64 64 LRU LRU 8 8 1.05296841

L1sepL2unified 64 64 LRU LRU 8 8 1.059915236

L1sepL2sep 64 64 LRU LRU 8 1 1.061853108

2 Anagram L1L2unified 64 64 LRU FIFO 4 1 1.07084492

L1sepL2unified 64 64 LRU FIFO 4 1 1.069724523

L1sepL2sep 64 64 FIFO FIFO 4 1 1.093832533

3 Go L1L2unified 64 64 Random LRU 8 4 1.011049037

L1sepL2unified 64 64 Random FIFO 8 2 1.012941826

L1sepL2sep 64 64 LRU Random 4 8 1.013631953

Row highlighted in green is the optimal CPI configuration for the corresponding Benchmark. Hence, the Best Configuration for each benchmark from the above table is shown below: ------------------------------------------------------------------------------------------------------------------------------- GO Benchmark L1 unified 64 bytes block size, 8 way set associative and Random replacement Policy L2 unified 64 bytes block size, 4 way set associative and LRU replacement Policy CPI Optimum = 1.01105 ------------------------------------------------------------------------------------------------------------------------------- ANAGRAM Benchmark L1 separate 64 bytes block size, 4-way set associative and LRU replacement policy L2 unified 64 bytes block size, 1-way set associative and FIFO replacement policy CPI Optimum = 1.06972 ------------------------------------------------------------------------------------------------------------------------------- GCC Benchmark: L1 unified 64 bytes block size, 8-way set associative and LRU replacement Policy L2 unified 64 bytes block size, 8-way set associative and LRU replacement Policy. CPI Optimum = 1.05297 -------------------------------------------------------------------------------------------------------------------------------

Page 10: Cache Design for an Alpha Microprocessor

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6. PART 4: DEFINE COST FUNCTION Cost function plays a major role in determining parameters that give least CPI. So we need to define a cost function, which assists architect to design a cost efficient, and performance effective Cache. It refrains us from choosing whatever design giving the least CPI. The cost function can be defined as below. Cost Function = 0.35*(L1 cache size) + 0.25* (L2 Cache size)+ 0.075* (L1 associativity) + 0.075* (L2 associativity)+ 0.15 *(Unified/Separate)+ 0.05*(L1 policy)+0.05*(L2 policy)+ 0*(block size) Explanation of the cost function can be found in the below table.

We normalized the cost function in such a way that the total cost will not exceed 100 units. For a given cost of a configuration say 85%, if the L1Cache Size doubles, the new cost function will become 120%. So assumed cost function is reasonable.

Cost Function Weight Overall Weight Comment

L1 Cache Size 0.35 64KB: 50 units 128KB: 100 units

If cache size doubles, cost also doubles

L2 Cache Size 0.25 512KB: 100 units 1MB: 200 units

If cache size doubles, cost also doubles

L1 Associativity 0.075

1: 2 units 2: 4 units 4: 8 units 8: 16 units

Increasing associativity increases number of comparators on hardware, which in turn increases cost.

L2 Associativity 0.075

1: 2 units 2: 4 units 4: 8 units 8: 16 units

Increasing associativity increases number of comparators on hardware, which in turn increases cost.

Unified/Separate 0.15

L1 Separate-L2 Separate: 1.5 units L1 Separate - L2 Unified: 0.5 units L1 Unified - L2 Unified: 0 units

Separate data and instruction cache will involve some additional hardware cost compared to unified

L1 Policy 0.05

LRU: 0.1 units FIFO: 0.05 units Random: 0 units

For Random, no extra hardware required. For FIFO to LRU, cost should increase by 5%.

L2 Policy 0.05

LRU: 0.1 units FIFO: 0.05 units Random: 0 units

For Random, no extra hardware required. For FIFO to LRU, cost should increase by 5%.

Block Size 0 32 Bytes: 0 units 64 Bytes: 0 units

With respect to hardware there will not be any additional cost for change in block size.

Page 11: Cache Design for an Alpha Microprocessor

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7. PART 5: OPTIMIZE CACHE FOR PERFORMANCE/ COST To find the optimal configuration, the cache configuration such as associativity, Replacement policy and cache type is considered along with the cost. A plot of Cache configuration for each benchmark is plotted against the product of the CPI and cost. The configuration, which gives the lowest value among all in the graph, is considered as the optimal configuration. 7.1. GCC Benchmark

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L1L2unified

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Page 12: Cache Design for an Alpha Microprocessor

12

7.2. Anagram Benchmark

7.3. GO Benchmark

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L1L2unified

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Page 13: Cache Design for an Alpha Microprocessor

13

Hence, from the graph above the optimum configuration would be as follows for all the 3 benchmarks-

Row highlighted in green is the optimal CPI configuration for the corresponding benchmark. Hence, the optimum configuration considering all three benchmark together with different specification constraints, Cost and CPI would be – ----------------------------------------------------------------------------------------------------------------------------------- Benchmark: GO

Cache Levels: L1 and L2

Configuration: L1 separate and L2 unified

Block size: 64 Bytes for L1 and 64 Bytes for L2

Block replacement policy: LRU for L1 and FIFO for L2

Associativity: 2-way associative for L1 and 2-way associative for L2 ------------------------------------------------------------------------------------------------------------------------------------

Sr. No.

Benchmark Configuration Block Size (in Bytes)

Replacement Policy Associativity

Optimal Configuration

L1 L2 L1 L2 L1 L2 (CPI*Cost)

1 GCC L1L2unified 64 64 LRU LRU 4 2 91.53571716

L1sepL2unified 64 64 LRU LRU 4 2 92.14588838

L1sepL2sep 64 64 LRU LRU 4 4 92.65215522

2 Anagram L1L2unified 64 64 LRU Random 2 1 91.51083284

L1sepL2unified 64 64 LRU Random 2 1 91.49413323

L1sepL2sep 64 64 LRU Random 4 2 93.74364974

3 Go L1L2unified 64 64 LRU FIFO 4 2 86.86445493

L1sepL2unified 64 64 LRU FIFO 2 2 86.83958025

L1sepL2sep 64 64 LRU Random 2 2 86.98242473

Page 14: Cache Design for an Alpha Microprocessor

14

8. CONCLUSION

Thus, the best possible configuration and its cost function have been computed by modifying various parameters such as cache type, associativity and replacement policies. 8.1 Optimal CPI

CPI is minimum mostly for LRU and High Associativity and Block size. It’s due to the following real reasons.

High Associativity: This will help to reduce the conflict misses High Block Size: It takes the advantage for spatial locality. LRU: It's the best page replacement policy, as it keeps track for the least frequent use of

any block need to be replaced. 8.2 Optimal CPI v/s Cost.

Here we have observed that high cost cache architectures have optimal values of CPI but the % change of CPI to the % change in cost function is not good.

Usually defining the cost function plays a very crucial role such that it should not be very large that CPI wont affect the optimization, at the same time it should not be so small that it doesn’t affect the optimization. Usually a configuration involves with FIFO as replacement policy, 2-way associativity or 4 – way associativity and L1 separate and L2 unified should give us the optimum performance design because cost and CPI with such configuration doesn’t have very high as well as very small value. So their product (CPI * Cost) will be minimum.

Page 15: Cache Design for an Alpha Microprocessor

15

9. APPENDIX

Below table shows all the combination values (Replacement policy [l – LRU, f- FIFO, r -random], Associativity [1, 2, 4, 8], Block Size [32 bytes, 64 bytes], Cost, CPI, Optimal Value (CPI*Cost), Configuration [L1 unified L2 unified, L1 separate L2 unified, L1 separate L2 separate]) for all the 3 benchmarks (GCC, Anagram, GO) from which we plotted all our above corresponding graphs.

Sr No. L1 L2 Benchmark Configuration CPI Cost CPI*Cost

1 1024:32:4:f 16384:32:2:f GCC L1L2unified 1.112259099 85.905 95.54861792

2 1024:32:4:f 16384:32:2:l GCC L1L2unified 1.108064778 85.9075 95.19107492

3 1024:32:4:f 16384:32:2:r GCC L1L2unified 1.115354908 85.9025 95.81177496

4 1024:32:4:f 32768:32:1:f GCC L1L2unified 1.149159139 85.755 98.54614197

5 1024:32:4:f 32768:32:1:l GCC L1L2unified 1.149159139 85.7575 98.54901486

6 1024:32:4:f 32768:32:1:r GCC L1L2unified 1.149159139 85.7525 98.54326907

7 1024:32:4:f 4096:32:8:f GCC L1L2unified 1.098028367 86.805 95.31435237

8 1024:32:4:f 4096:32:8:l GCC L1L2unified 1.089889386 86.8075 94.6105729

9 1024:32:4:f 4096:32:8:r GCC L1L2unified 1.103470998 86.8025 95.78404128

10 1024:32:4:f 8192:32:4:f GCC L1L2unified 1.103570863 86.205 95.1333262

11 1024:32:4:f 8192:32:4:l GCC L1L2unified 1.096680192 86.2075 94.54205765

12 1024:32:4:f 8192:32:4:r GCC L1L2unified 1.107515522 86.2025 95.47060676

13 1024:32:4:l 16384:32:2:f GCC L1L2unified 1.104782958 85.9075 94.90914199

14 1024:32:4:l 16384:32:2:l GCC L1L2unified 1.101219231 85.91 94.60574415

15 1024:32:4:l 16384:32:2:r GCC L1L2unified 1.107260183 85.905 95.11918604

16 1024:32:4:l 32768:32:1:f GCC L1L2unified 1.136074221 85.7575 97.42688498

17 1024:32:4:l 32768:32:1:l GCC L1L2unified 1.136074221 85.76 97.42972516

18 1024:32:4:l 32768:32:1:r GCC L1L2unified 1.136074221 85.755 97.42404479

19 1024:32:4:l 4096:32:8:f GCC L1L2unified 1.091223411 86.8075 94.72637628

20 1024:32:4:l 4096:32:8:l GCC L1L2unified 1.083487516 86.81 94.05755126

21 1024:32:4:l 4096:32:8:r GCC L1L2unified 1.096351702 86.805 95.16880945

22 1024:32:4:l 8192:32:4:f GCC L1L2unified 1.096612462 86.2075 94.53621882

23 1024:32:4:l 8192:32:4:l GCC L1L2unified 1.09039767 86.21 94.0031831

24 1024:32:4:l 8192:32:4:r GCC L1L2unified 1.100350029 86.205 94.85567429

25 1024:32:4:r 16384:32:2:f GCC L1L2unified 1.11527412 85.9025 95.8048351

26 1024:32:4:r 16384:32:2:l GCC L1L2unified 1.111187786 85.905 95.45658672

27 1024:32:4:r 16384:32:2:r GCC L1L2unified 1.118367254 85.9 96.06774715

28 1024:32:4:r 32768:32:1:f GCC L1L2unified 1.149631591 85.7525 98.58378298

29 1024:32:4:r 32768:32:1:l GCC L1L2unified 1.149631591 85.755 98.58665706

30 1024:32:4:r 32768:32:1:r GCC L1L2unified 1.149703786 85.75 98.58709962

Page 16: Cache Design for an Alpha Microprocessor

16

31 1024:32:4:r 4096:32:8:f GCC L1L2unified 1.101294555 86.8025 95.59512057

32 1024:32:4:r 4096:32:8:l GCC L1L2unified 1.093175653 86.805 94.89311257

33 1024:32:4:r 4096:32:8:r GCC L1L2unified 1.107068127 86.8 96.09351342

34 1024:32:4:r 8192:32:4:f GCC L1L2unified 1.106725078 86.2025 95.40246855

35 1024:32:4:r 8192:32:4:l GCC L1L2unified 1.100004133 86.205 94.8258563

36 1024:32:4:r 8192:32:4:r GCC L1L2unified 1.110966593 86.2 95.7653203

37 1024:64:2:f 16384:64:1:f GCC L1L2unified 1.121501913 85.455 95.83794601

38 1024:64:2:f 16384:64:1:l GCC L1L2unified 1.121501913 85.4575 95.84074977

39 1024:64:2:f 16384:64:1:r GCC L1L2unified 1.121501913 85.4525 95.83514226

40 1024:64:2:f 2048:64:8:f GCC L1L2unified 1.078853515 86.505 93.32622333

41 1024:64:2:f 2048:64:8:l GCC L1L2unified 1.07324803 86.5075 92.84400397

42 1024:64:2:f 2048:64:8:r GCC L1L2unified 1.081796395 86.5025 93.57809264

43 1024:64:2:f 4096:64:4:f GCC L1L2unified 1.08268393 85.905 93.007963

44 1024:64:2:f 4096:64:4:l GCC L1L2unified 1.07796598 85.9075 92.60536243

45 1024:64:2:f 4096:64:4:r GCC L1L2unified 1.084879412 85.9025 93.19385365

46 1024:64:2:f 8192:64:2:f GCC L1L2unified 1.088616402 85.605 93.19100705

47 1024:64:2:f 8192:64:2:l GCC L1L2unified 1.08543996 85.6075 92.92180138

48 1024:64:2:f 8192:64:2:r GCC L1L2unified 1.090718458 85.6025 93.36822683

49 1024:64:2:l 16384:64:1:f GCC L1L2unified 1.113383427 85.4575 95.14696424

50 1024:64:2:l 16384:64:1:l GCC L1L2unified 1.113383427 85.46 95.14974769

51 1024:64:2:l 16384:64:1:r GCC L1L2unified 1.113383427 85.455 95.14418078

52 1024:64:2:l 2048:64:8:f GCC L1L2unified 1.074630245 86.5075 92.96357589

53 1024:64:2:l 2048:64:8:l GCC L1L2unified 1.069234774 86.51 92.49950029

54 1024:64:2:l 2048:64:8:r GCC L1L2unified 1.077499265 86.505 93.2090739

55 1024:64:2:l 4096:64:4:f GCC L1L2unified 1.078484152 85.9075 92.64987731

56 1024:64:2:l 4096:64:4:l GCC L1L2unified 1.073945105 85.91 92.26262401

57 1024:64:2:l 4096:64:4:r GCC L1L2unified 1.080368285 85.905 92.80903752

58 1024:64:2:l 8192:64:2:f GCC L1L2unified 1.08413655 85.6075 92.81021972

59 1024:64:2:l 8192:64:2:l GCC L1L2unified 1.08126753 85.61 92.56731325

60 1024:64:2:l 8192:64:2:r GCC L1L2unified 1.085892219 85.605 92.95780343

61 1024:64:2:r 16384:64:1:f GCC L1L2unified 1.120871514 85.4525 95.78127308

62 1024:64:2:r 16384:64:1:l GCC L1L2unified 1.120871514 85.455 95.78407526

63 1024:64:2:r 16384:64:1:r GCC L1L2unified 1.120801859 85.45 95.77251888

64 1024:64:2:r 2048:64:8:f GCC L1L2unified 1.080468975 86.5025 93.46326754

65 1024:64:2:r 2048:64:8:l GCC L1L2unified 1.074933051 86.505 92.98708353

66 1024:64:2:r 2048:64:8:r GCC L1L2unified 1.083577167 86.5 93.72942493

67 1024:64:2:r 4096:64:4:f GCC L1L2unified 1.084353835 85.9025 93.1487053

68 1024:64:2:r 4096:64:4:l GCC L1L2unified 1.079643443 85.905 92.74676994

69 1024:64:2:r 4096:64:4:r GCC L1L2unified 1.086481265 85.9 93.32874064

70 1024:64:2:r 8192:64:2:f GCC L1L2unified 1.090084003 85.6025 93.31391584

71 1024:64:2:r 8192:64:2:l GCC L1L2unified 1.086976115 85.605 93.05059033

Page 17: Cache Design for an Alpha Microprocessor

17

72 1024:64:2:r 8192:64:2:r GCC L1L2unified 1.092974606 85.6 93.55862631

73 2048:32:2:f 16384:32:2:f GCC L1L2unified 1.124854724 85.605 96.29318861

74 2048:32:2:f 16384:32:2:l GCC L1L2unified 1.120328983 85.6075 95.90856345

75 2048:32:2:f 16384:32:2:r GCC L1L2unified 1.128157291 85.6025 96.57308447

76 2048:32:2:f 32768:32:1:f GCC L1L2unified 1.168888951 85.455 99.88740534

77 2048:32:2:f 32768:32:1:l GCC L1L2unified 1.168888951 85.4575 99.89032756

78 2048:32:2:f 32768:32:1:r GCC L1L2unified 1.168888951 85.4525 99.88448312

79 2048:32:2:f 4096:32:8:f GCC L1L2unified 1.110360124 86.505 96.05170249

80 2048:32:2:f 4096:32:8:l GCC L1L2unified 1.102103706 86.5075 95.34023634

81 2048:32:2:f 4096:32:8:r GCC L1L2unified 1.115680926 86.5025 96.50918931

82 2048:32:2:f 8192:32:4:f GCC L1L2unified 1.115864402 85.905 95.85833146

83 2048:32:2:f 8192:32:4:l GCC L1L2unified 1.108892316 85.9075 95.26216664

84 2048:32:2:f 8192:32:4:r GCC L1L2unified 1.119839714 85.9025 96.19703106

85 2048:32:2:l 16384:32:2:f GCC L1L2unified 1.119501213 85.6075 95.83770012

86 2048:32:2:l 16384:32:2:l GCC L1L2unified 1.115445076 85.61 95.49325292

87 2048:32:2:l 16384:32:2:r GCC L1L2unified 1.122317976 85.605 96.0760303

88 2048:32:2:l 32768:32:1:f GCC L1L2unified 1.158823215 85.4575 99.03013486

89 2048:32:2:l 32768:32:1:l GCC L1L2unified 1.158823215 85.46 99.03303191

90 2048:32:2:l 32768:32:1:r GCC L1L2unified 1.158823215 85.455 99.0272378

91 2048:32:2:l 4096:32:8:f GCC L1L2unified 1.105361067 86.5075 95.62202248

92 2048:32:2:l 4096:32:8:l GCC L1L2unified 1.097305127 86.51 94.9278665

93 2048:32:2:l 4096:32:8:r GCC L1L2unified 1.110543909 86.505 96.06760087

94 2048:32:2:l 8192:32:4:f GCC L1L2unified 1.110825585 85.9075 95.42824899

95 2048:32:2:l 8192:32:4:l GCC L1L2unified 1.104121691 85.91 94.8550945

96 2048:32:2:l 8192:32:4:r GCC L1L2unified 1.114543712 85.905 95.74487755

97 2048:32:2:r 16384:32:2:f GCC L1L2unified 1.127216284 85.6025 96.49253191

98 2048:32:2:r 16384:32:2:l GCC L1L2unified 1.122811537 85.605 96.1182816

99 2048:32:2:r 16384:32:2:r GCC L1L2unified 1.130453758 85.6 96.76684172

100 2048:32:2:r 32768:32:1:f GCC L1L2unified 1.168582602 85.4525 99.85830476

101 2048:32:2:r 32768:32:1:l GCC L1L2unified 1.168582602 85.455 99.86122622

102 2048:32:2:r 32768:32:1:r GCC L1L2unified 1.168476424 85.45 99.84631039

103 2048:32:2:r 4096:32:8:f GCC L1L2unified 1.112789142 86.5025 96.25904273

104 2048:32:2:r 4096:32:8:l GCC L1L2unified 1.104618017 86.505 95.55498157

105 2048:32:2:r 4096:32:8:r GCC L1L2unified 1.118366239 86.5 96.73867968

106 2048:32:2:r 8192:32:4:f GCC L1L2unified 1.118279116 85.9025 96.06297176

107 2048:32:2:r 8192:32:4:l GCC L1L2unified 1.111448567 85.905 95.47898911

108 2048:32:2:r 8192:32:4:r GCC L1L2unified 1.122223797 85.9 96.39902419

109 2048:64:1:f 16384:64:1:f GCC L1L2unified 1.178586689 85.305 100.5393375

110 2048:64:1:f 16384:64:1:l GCC L1L2unified 1.178586689 85.3075 100.542284

111 2048:64:1:f 16384:64:1:r GCC L1L2unified 1.178586689 85.3025 100.536391

112 2048:64:1:f 2048:64:8:f GCC L1L2unified 1.119054642 86.355 96.63596363

Page 18: Cache Design for an Alpha Microprocessor

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113 2048:64:1:f 2048:64:8:l GCC L1L2unified 1.113428906 86.3575 96.15293674

114 2048:64:1:f 2048:64:8:r GCC L1L2unified 1.121909494 86.3525 96.87968955

115 2048:64:1:f 4096:64:4:f GCC L1L2unified 1.122917088 85.755 96.2957549

116 2048:64:1:f 4096:64:4:l GCC L1L2unified 1.118131014 85.7575 95.88812043

117 2048:64:1:f 4096:64:4:r GCC L1L2unified 1.124932277 85.7525 96.46575511

118 2048:64:1:f 8192:64:2:f GCC L1L2unified 1.128794723 85.455 96.46115308

119 2048:64:1:f 8192:64:2:l GCC L1L2unified 1.125352108 85.4575 96.16977781

120 2048:64:1:f 8192:64:2:r GCC L1L2unified 1.131145777 85.4525 96.65923453

121 2048:64:1:l 16384:64:1:f GCC L1L2unified 1.178586689 85.3075 100.542284

122 2048:64:1:l 16384:64:1:l GCC L1L2unified 1.178586689 85.31 100.5452304

123 2048:64:1:l 16384:64:1:r GCC L1L2unified 1.178586689 85.305 100.5393375

124 2048:64:1:l 2048:64:8:f GCC L1L2unified 1.119054642 86.3575 96.63876127

125 2048:64:1:l 2048:64:8:l GCC L1L2unified 1.113428906 86.36 96.15572031

126 2048:64:1:l 2048:64:8:r GCC L1L2unified 1.121909494 86.355 96.88249432

127 2048:64:1:l 4096:64:4:f GCC L1L2unified 1.122917088 85.7575 96.29856219

128 2048:64:1:l 4096:64:4:l GCC L1L2unified 1.118131014 85.76 95.89091575

129 2048:64:1:l 4096:64:4:r GCC L1L2unified 1.124932277 85.755 96.46856744

130 2048:64:1:l 8192:64:2:f GCC L1L2unified 1.128794723 85.4575 96.46397506

131 2048:64:1:l 8192:64:2:l GCC L1L2unified 1.125352108 85.46 96.17259119

132 2048:64:1:l 8192:64:2:r GCC L1L2unified 1.131145777 85.455 96.6620624

133 2048:64:1:r 16384:64:1:f GCC L1L2unified 1.178586689 85.3025 100.536391

134 2048:64:1:r 16384:64:1:l GCC L1L2unified 1.178586689 85.305 100.5393375

135 2048:64:1:r 16384:64:1:r GCC L1L2unified 1.178586689 85.3 100.5334446

136 2048:64:1:r 2048:64:8:f GCC L1L2unified 1.119054642 86.3525 96.633166

137 2048:64:1:r 2048:64:8:l GCC L1L2unified 1.113428906 86.355 96.15015316

138 2048:64:1:r 2048:64:8:r GCC L1L2unified 1.121741561 86.35 96.86238381

139 2048:64:1:r 4096:64:4:f GCC L1L2unified 1.122917088 85.7525 96.2929476

140 2048:64:1:r 4096:64:4:l GCC L1L2unified 1.118131014 85.755 95.8853251

141 2048:64:1:r 4096:64:4:r GCC L1L2unified 1.125016244 85.75 96.47014289

142 2048:64:1:r 8192:64:2:f GCC L1L2unified 1.128794723 85.4525 96.45833109

143 2048:64:1:r 8192:64:2:l GCC L1L2unified 1.125352108 85.455 96.16696443

144 2048:64:1:r 8192:64:2:r GCC L1L2unified 1.131229744 85.45 96.66358158

145 256:64:8:f 16384:64:1:f GCC L1L2unified 1.098341943 86.355 94.84731853

146 256:64:8:f 16384:64:1:l GCC L1L2unified 1.098341943 86.3575 94.85006438

147 256:64:8:f 16384:64:1:r GCC L1L2unified 1.098341943 86.3525 94.84457267

148 256:64:8:f 2048:64:8:f GCC L1L2unified 1.06401642 87.405 93.00035517

149 256:64:8:f 2048:64:8:l GCC L1L2unified 1.058540363 87.4075 92.52436682

150 256:64:8:f 2048:64:8:r GCC L1L2unified 1.066954791 87.4025 93.25451616

151 256:64:8:f 4096:64:4:f GCC L1L2unified 1.067889728 86.805 92.69816783

152 256:64:8:f 4096:64:4:l GCC L1L2unified 1.063248436 86.8075 92.29793863

153 256:64:8:f 4096:64:4:r GCC L1L2unified 1.070126897 86.8025 92.88969

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154 256:64:8:f 8192:64:2:f GCC L1L2unified 1.073399175 86.505 92.85439562

155 256:64:8:f 8192:64:2:l GCC L1L2unified 1.070494194 86.5075 92.60577646

156 256:64:8:f 8192:64:2:r GCC L1L2unified 1.075135485 86.5025 93.00190732

157 256:64:8:l 16384:64:1:f GCC L1L2unified 1.087020471 86.3575 93.87237031

158 256:64:8:l 16384:64:1:l GCC L1L2unified 1.087020471 86.36 93.87508786

159 256:64:8:l 16384:64:1:r GCC L1L2unified 1.087020471 86.355 93.86965276

160 256:64:8:l 2048:64:8:f GCC L1L2unified 1.057990675 87.4075 92.47631996

161 256:64:8:l 2048:64:8:l GCC L1L2unified 1.05296841 87.41 92.03996875

162 256:64:8:l 2048:64:8:r GCC L1L2unified 1.060832946 87.405 92.72210367

163 256:64:8:l 4096:64:4:f GCC L1L2unified 1.061798766 86.8075 92.17209642

164 256:64:8:l 4096:64:4:l GCC L1L2unified 1.057797511 86.81 91.82740196

165 256:64:8:l 4096:64:4:r GCC L1L2unified 1.063647622 86.805 92.32993185

166 256:64:8:l 8192:64:2:f GCC L1L2unified 1.066683057 86.5075 92.27608456

167 256:64:8:l 8192:64:2:l GCC L1L2unified 1.064309899 86.51 92.07344936

168 256:64:8:l 8192:64:2:r GCC L1L2unified 1.068035205 86.505 92.39038544

169 256:64:8:r 16384:64:1:f GCC L1L2unified 1.099248992 86.3525 94.92289861

170 256:64:8:r 16384:64:1:l GCC L1L2unified 1.099248992 86.355 94.92564674

171 256:64:8:r 16384:64:1:r GCC L1L2unified 1.099331277 86.35 94.92725574

172 256:64:8:r 2048:64:8:f GCC L1L2unified 1.067225384 87.4025 93.27816663

173 256:64:8:r 2048:64:8:l GCC L1L2unified 1.0618699 87.405 92.81273862

174 256:64:8:r 2048:64:8:r GCC L1L2unified 1.070485012 87.4 93.56039008

175 256:64:8:r 4096:64:4:f GCC L1L2unified 1.071087162 86.8025 92.97304335

176 256:64:8:r 4096:64:4:l GCC L1L2unified 1.066606042 86.805 92.58673751

177 256:64:8:r 4096:64:4:r GCC L1L2unified 1.073446877 86.8 93.1751889

178 256:64:8:r 8192:64:2:f GCC L1L2unified 1.076406214 86.5025 93.11182851

179 256:64:8:r 8192:64:2:l GCC L1L2unified 1.073528097 86.505 92.86554799

180 256:64:8:r 8192:64:2:r GCC L1L2unified 1.078152326 86.5 93.26017621

181 4096:32:1:f 16384:32:2:f GCC L1L2unified 1.172416832 85.455 100.1888804

182 4096:32:1:f 16384:32:2:l GCC L1L2unified 1.167558927 85.4575 99.77666697

183 4096:32:1:f 16384:32:2:r GCC L1L2unified 1.175796244 85.4525 100.4747286

184 4096:32:1:f 32768:32:1:f GCC L1L2unified 1.23366868 85.305 105.2381068

185 4096:32:1:f 32768:32:1:l GCC L1L2unified 1.23366868 85.3075 105.2411909

186 4096:32:1:f 32768:32:1:r GCC L1L2unified 1.23366868 85.3025 105.2350226

187 4096:32:1:f 4096:32:8:f GCC L1L2unified 1.157948723 86.355 99.99466196

188 4096:32:1:f 4096:32:8:l GCC L1L2unified 1.149605799 86.3575 99.27708276

189 4096:32:1:f 4096:32:8:r GCC L1L2unified 1.162806628 86.3525 100.4112593

190 4096:32:1:f 8192:32:4:f GCC L1L2unified 1.163440268 85.755 99.77082017

191 4096:32:1:f 8192:32:4:l GCC L1L2unified 1.15647023 85.7575 99.17599574

192 4096:32:1:f 8192:32:4:r GCC L1L2unified 1.1671365 85.7525 100.0848727

193 4096:32:1:l 16384:32:2:f GCC L1L2unified 1.172416832 85.4575 100.1918114

194 4096:32:1:l 16384:32:2:l GCC L1L2unified 1.167558927 85.46 99.77958587

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195 4096:32:1:l 16384:32:2:r GCC L1L2unified 1.175796244 85.455 100.477668

196 4096:32:1:l 32768:32:1:f GCC L1L2unified 1.23366868 85.3075 105.2411909

197 4096:32:1:l 32768:32:1:l GCC L1L2unified 1.23366868 85.31 105.2442751

198 4096:32:1:l 32768:32:1:r GCC L1L2unified 1.23366868 85.305 105.2381068

199 4096:32:1:l 4096:32:8:f GCC L1L2unified 1.157948723 86.3575 99.99755683

200 4096:32:1:l 4096:32:8:l GCC L1L2unified 1.149605799 86.36 99.27995677

201 4096:32:1:l 4096:32:8:r GCC L1L2unified 1.162806628 86.355 100.4141664

202 4096:32:1:l 8192:32:4:f GCC L1L2unified 1.163440268 85.7575 99.77372877

203 4096:32:1:l 8192:32:4:l GCC L1L2unified 1.15647023 85.76 99.17888692

204 4096:32:1:l 8192:32:4:r GCC L1L2unified 1.1671365 85.755 100.0877906

205 4096:32:1:r 16384:32:2:f GCC L1L2unified 1.172416832 85.4525 100.1859493

206 4096:32:1:r 16384:32:2:l GCC L1L2unified 1.167558927 85.455 99.77374807

207 4096:32:1:r 16384:32:2:r GCC L1L2unified 1.175901851 85.45 100.4808131

208 4096:32:1:r 32768:32:1:f GCC L1L2unified 1.23366868 85.3025 105.2350226

209 4096:32:1:r 32768:32:1:l GCC L1L2unified 1.23366868 85.305 105.2381068

210 4096:32:1:r 32768:32:1:r GCC L1L2unified 1.23366868 85.3 105.2319384

211 4096:32:1:r 4096:32:8:f GCC L1L2unified 1.157948723 86.3525 99.99176709

212 4096:32:1:r 4096:32:8:l GCC L1L2unified 1.149605799 86.355 99.27420874

213 4096:32:1:r 4096:32:8:r GCC L1L2unified 1.162806628 86.35 100.4083523

214 4096:32:1:r 8192:32:4:f GCC L1L2unified 1.163440268 85.7525 99.76791157

215 4096:32:1:r 8192:32:4:l GCC L1L2unified 1.15647023 85.755 99.17310457

216 4096:32:1:r 8192:32:4:r GCC L1L2unified 1.1671365 85.75 100.0819549

217 512:32:8:f 16384:32:2:f GCC L1L2unified 1.108088666 86.505 95.85521002

218 512:32:8:f 16384:32:2:l GCC L1L2unified 1.104027508 86.5075 95.50665961

219 512:32:8:f 16384:32:2:r GCC L1L2unified 1.111226833 86.5025 96.12389914

220 512:32:8:f 32768:32:1:f GCC L1L2unified 1.142931556 86.355 98.69785452

221 512:32:8:f 32768:32:1:l GCC L1L2unified 1.142931556 86.3575 98.70071184

222 512:32:8:f 32768:32:1:r GCC L1L2unified 1.142931556 86.3525 98.69499719

223 512:32:8:f 4096:32:8:f GCC L1L2unified 1.093874612 87.405 95.6101105

224 512:32:8:f 4096:32:8:l GCC L1L2unified 1.085798446 87.4075 94.90692765

225 512:32:8:f 4096:32:8:r GCC L1L2unified 1.099181808 87.4025 96.07123794

226 512:32:8:f 8192:32:4:f GCC L1L2unified 1.099412555 86.805 95.43450686

227 512:32:8:f 8192:32:4:l GCC L1L2unified 1.092628575 86.8075 94.84835505

228 512:32:8:f 8192:32:4:r GCC L1L2unified 1.103427564 86.8025 95.78027111

229 512:32:8:l 16384:32:2:f GCC L1L2unified 1.099524081 86.5075 95.11707944

230 512:32:8:l 16384:32:2:l GCC L1L2unified 1.096285349 86.51 94.83964557

231 512:32:8:l 16384:32:2:r GCC L1L2unified 1.101943375 86.505 95.32361162

232 512:32:8:l 32768:32:1:f GCC L1L2unified 1.1283605 86.3575 97.44239185

233 512:32:8:l 32768:32:1:l GCC L1L2unified 1.1283605 86.36 97.44521275

234 512:32:8:l 32768:32:1:r GCC L1L2unified 1.1283605 86.355 97.43957095

235 512:32:8:l 4096:32:8:f GCC L1L2unified 1.086217966 87.4075 94.94359689

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236 512:32:8:l 4096:32:8:l GCC L1L2unified 1.078647919 87.41 94.28461457

237 512:32:8:l 4096:32:8:r GCC L1L2unified 1.091407741 87.405 95.39449362

238 512:32:8:l 8192:32:4:f GCC L1L2unified 1.091641866 86.8075 94.76270132

239 512:32:8:l 8192:32:4:l GCC L1L2unified 1.085671674 86.81 94.24715804

240 512:32:8:l 8192:32:4:r GCC L1L2unified 1.095231786 86.805 95.07159518

241 512:32:8:r 16384:32:2:f GCC L1L2unified 1.111741929 86.5025 96.16845617

242 512:32:8:r 16384:32:2:l GCC L1L2unified 1.107851623 86.505 95.83470462

243 512:32:8:r 16384:32:2:r GCC L1L2unified 1.114791176 86.5 96.42943674

244 512:32:8:r 32768:32:1:f GCC L1L2unified 1.143925368 86.3525 98.78081536

245 512:32:8:r 32768:32:1:l GCC L1L2unified 1.143925368 86.355 98.78367517

246 512:32:8:r 32768:32:1:r GCC L1L2unified 1.143978171 86.35 98.78251503

247 512:32:8:r 4096:32:8:f GCC L1L2unified 1.097949026 87.4025 95.96348973

248 512:32:8:r 4096:32:8:l GCC L1L2unified 1.089915797 87.405 95.26409021

249 512:32:8:r 4096:32:8:r GCC L1L2unified 1.103738468 87.4 96.46674206

250 512:32:8:r 8192:32:4:f GCC L1L2unified 1.103405559 86.8025 95.77836101

251 512:32:8:r 8192:32:4:l GCC L1L2unified 1.09683751 86.805 95.21098004

252 512:32:8:r 8192:32:4:r GCC L1L2unified 1.107577561 86.8 96.13773225

253 512:64:4:f 16384:64:1:f GCC L1L2unified 1.104157357 85.755 94.68701418

254 512:64:4:f 16384:64:1:l GCC L1L2unified 1.104157357 85.7575 94.68977457

255 512:64:4:f 16384:64:1:r GCC L1L2unified 1.104157357 85.7525 94.68425378

256 512:64:4:f 2048:64:8:f GCC L1L2unified 1.068143166 86.805 92.72016756

257 512:64:4:f 2048:64:8:l GCC L1L2unified 1.062642017 86.8075 92.2452969

258 512:64:4:f 2048:64:8:r GCC L1L2unified 1.071113787 86.8025 92.9753545

259 512:64:4:f 4096:64:4:f GCC L1L2unified 1.071993971 86.205 92.41124027

260 512:64:4:f 4096:64:4:l GCC L1L2unified 1.067336331 86.2075 92.01239677

261 512:64:4:f 4096:64:4:r GCC L1L2unified 1.074047733 86.2025 92.58559974

262 512:64:4:f 8192:64:2:f GCC L1L2unified 1.077568469 85.905 92.56851933

263 512:64:4:f 8192:64:2:l GCC L1L2unified 1.074597848 85.9075 92.31601465

264 512:64:4:f 8192:64:2:r GCC L1L2unified 1.07943886 85.9025 92.72649665

265 512:64:4:l 16384:64:1:f GCC L1L2unified 1.093119318 85.7575 93.74317991

266 512:64:4:l 16384:64:1:l GCC L1L2unified 1.093119318 85.76 93.7459127

267 512:64:4:l 16384:64:1:r GCC L1L2unified 1.093119318 85.755 93.74044711

268 512:64:4:l 2048:64:8:f GCC L1L2unified 1.062216663 86.8075 92.20837293

269 512:64:4:l 2048:64:8:l GCC L1L2unified 1.057024261 86.81 91.76027611

270 512:64:4:l 2048:64:8:r GCC L1L2unified 1.065080351 86.805 92.45429983

271 512:64:4:l 4096:64:4:f GCC L1L2unified 1.066024424 86.2075 91.89930049

272 512:64:4:l 4096:64:4:l GCC L1L2unified 1.061776095 86.21 91.53571716

273 512:64:4:l 4096:64:4:r GCC L1L2unified 1.067944039 86.205 92.06211584

274 512:64:4:l 8192:64:2:f GCC L1L2unified 1.071090948 85.9075 92.01474566

275 512:64:4:l 8192:64:2:l GCC L1L2unified 1.068541951 85.91 91.79843905

276 512:64:4:l 8192:64:2:r GCC L1L2unified 1.07244412 85.905 92.12831211

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277 512:64:4:r 16384:64:1:f GCC L1L2unified 1.104460372 85.7525 94.71023807

278 512:64:4:r 16384:64:1:l GCC L1L2unified 1.104460372 85.755 94.71299922

279 512:64:4:r 16384:64:1:r GCC L1L2unified 1.104537586 85.75 94.71409801

280 512:64:4:r 2048:64:8:f GCC L1L2unified 1.070551127 86.8025 92.92651424

281 512:64:4:r 2048:64:8:l GCC L1L2unified 1.065122501 86.805 92.45795872

282 512:64:4:r 2048:64:8:r GCC L1L2unified 1.073937809 86.8 93.21780182

283 512:64:4:r 4096:64:4:f GCC L1L2unified 1.074406239 86.2025 92.6165038

284 512:64:4:r 4096:64:4:l GCC L1L2unified 1.069843046 86.205 92.22581976

285 512:64:4:r 4096:64:4:r GCC L1L2unified 1.076706735 86.2 92.81212054

286 512:64:4:r 8192:64:2:f GCC L1L2unified 1.079834865 85.9025 92.76051449

287 512:64:4:r 8192:64:2:l GCC L1L2unified 1.076884525 85.905 92.50976509

288 512:64:4:r 8192:64:2:r GCC L1L2unified 1.081679127 85.9 92.91623701

289 1024:32:4:f 16384:32:2:f Anagram L1L2unified 1.15419899 85.905 99.15146424

290 1024:32:4:f 16384:32:2:l Anagram L1L2unified 1.15419899 85.9075 99.15434973

291 1024:32:4:f 16384:32:2:r Anagram L1L2unified 1.154234612 85.9025 99.15163873

292 1024:32:4:f 32768:32:1:f Anagram L1L2unified 1.139950304 85.755 97.7564383

293 1024:32:4:f 32768:32:1:l Anagram L1L2unified 1.139950304 85.7575 97.75928817

294 1024:32:4:f 32768:32:1:r Anagram L1L2unified 1.139950304 85.7525 97.75358842

295 1024:32:4:f 4096:32:8:f Anagram L1L2unified 1.187362807 86.805 103.0690285

296 1024:32:4:f 4096:32:8:l Anagram L1L2unified 1.18700659 86.8075 103.0410746

297 1024:32:4:f 4096:32:8:r Anagram L1L2unified 1.162391985 86.8025 100.8985302

298 1024:32:4:f 8192:32:4:f Anagram L1L2unified 1.184441827 86.205 102.1048077

299 1024:32:4:f 8192:32:4:l Anagram L1L2unified 1.184441827 86.2075 102.1077688

300 1024:32:4:f 8192:32:4:r Anagram L1L2unified 1.160860251 86.2025 100.0690558

301 1024:32:4:l 16384:32:2:f Anagram L1L2unified 1.15418893 85.9075 99.15348548

302 1024:32:4:l 16384:32:2:l Anagram L1L2unified 1.15418893 85.91 99.15637095

303 1024:32:4:l 16384:32:2:r Anagram L1L2unified 1.154578804 85.905 99.18409214

304 1024:32:4:l 32768:32:1:f Anagram L1L2unified 1.139905362 85.7575 97.75543412

305 1024:32:4:l 32768:32:1:l Anagram L1L2unified 1.139905362 85.76 97.75828389

306 1024:32:4:l 32768:32:1:r Anagram L1L2unified 1.139905362 85.755 97.75258436

307 1024:32:4:l 4096:32:8:f Anagram L1L2unified 1.187363666 86.8075 103.0720715

308 1024:32:4:l 4096:32:8:l Anagram L1L2unified 1.187009236 86.81 103.0442717

309 1024:32:4:l 4096:32:8:r Anagram L1L2unified 1.161986411 86.805 100.8662304

310 1024:32:4:l 8192:32:4:f Anagram L1L2unified 1.18442189 86.2075 102.10605

311 1024:32:4:l 8192:32:4:l Anagram L1L2unified 1.18442189 86.21 102.1090111

312 1024:32:4:l 8192:32:4:r Anagram L1L2unified 1.160994004 86.205 100.0834881

313 1024:32:4:r 16384:32:2:f Anagram L1L2unified 1.154294264 85.9025 99.15676303

314 1024:32:4:r 16384:32:2:l Anagram L1L2unified 1.153872189 85.905 99.1233904

315 1024:32:4:r 16384:32:2:r Anagram L1L2unified 1.156006744 85.9 99.30097935

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321 1024:32:4:r 4096:32:8:r Anagram L1L2unified 1.167109777 86.8 101.3051286

322 1024:32:4:r 8192:32:4:f Anagram L1L2unified 1.184437464 86.2025 102.1014705

323 1024:32:4:r 8192:32:4:l Anagram L1L2unified 1.181658803 86.205 101.8648971

324 1024:32:4:r 8192:32:4:r Anagram L1L2unified 1.16280916 86.2 100.2341496

325 1024:64:2:f 16384:64:1:f Anagram L1L2unified 1.070921125 85.455 91.51556475

326 1024:64:2:f 16384:64:1:l Anagram L1L2unified 1.070921125 85.4575 91.51824206

327 1024:64:2:f 16384:64:1:r Anagram L1L2unified 1.070921125 85.4525 91.51288745

328 1024:64:2:f 2048:64:8:f Anagram L1L2unified 1.094472569 86.505 94.67734962

329 1024:64:2:f 2048:64:8:l Anagram L1L2unified 1.094291404 86.5075 94.66441367

330 1024:64:2:f 2048:64:8:r Anagram L1L2unified 1.08200842 86.5025 93.59643339

331 1024:64:2:f 4096:64:4:f Anagram L1L2unified 1.093005133 85.905 93.89460597

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333 1024:64:2:f 4096:64:4:r Anagram L1L2unified 1.081374343 85.9025 92.89275951

334 1024:64:2:f 8192:64:2:f Anagram L1L2unified 1.077895976 85.605 92.27328502

335 1024:64:2:f 8192:64:2:l Anagram L1L2unified 1.077895976 85.6075 92.27597976

336 1024:64:2:f 8192:64:2:r Anagram L1L2unified 1.078203956 85.6025 92.29695418

337 1024:64:2:l 16384:64:1:f Anagram L1L2unified 1.070865752 85.4575 91.51351

338 1024:64:2:l 16384:64:1:l Anagram L1L2unified 1.070865752 85.46 91.51618717

339 1024:64:2:l 16384:64:1:r Anagram L1L2unified 1.070865752 85.455 91.51083284

340 1024:64:2:l 2048:64:8:f Anagram L1L2unified 1.094464505 86.5075 94.67938819

341 1024:64:2:l 2048:64:8:l Anagram L1L2unified 1.094284637 86.51 94.66656392

342 1024:64:2:l 2048:64:8:r Anagram L1L2unified 1.082125523 86.505 93.60926837

343 1024:64:2:l 4096:64:4:f Anagram L1L2unified 1.09300757 85.9075 93.89754782

344 1024:64:2:l 4096:64:4:l Anagram L1L2unified 1.09300757 85.91 93.90028034

345 1024:64:2:l 4096:64:4:r Anagram L1L2unified 1.081693838 85.905 92.92290919

346 1024:64:2:l 8192:64:2:f Anagram L1L2unified 1.077898612 85.6075 92.27620544

347 1024:64:2:l 8192:64:2:l Anagram L1L2unified 1.077898612 85.61 92.27890019

348 1024:64:2:l 8192:64:2:r Anagram L1L2unified 1.078258349 85.605 92.30430599

349 1024:64:2:r 16384:64:1:f Anagram L1L2unified 1.071952102 85.4525 91.60098704

350 1024:64:2:r 16384:64:1:l Anagram L1L2unified 1.071952102 85.455 91.60366692

351 1024:64:2:r 16384:64:1:r Anagram L1L2unified 1.072037987 85.45 91.605646

352 1024:64:2:r 2048:64:8:f Anagram L1L2unified 1.094467508 86.5025 94.67417558

353 1024:64:2:r 2048:64:8:l Anagram L1L2unified 1.092848988 86.505 94.53690171

354 1024:64:2:r 2048:64:8:r Anagram L1L2unified 1.083444532 86.5 93.71795198

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361 2048:32:2:f 16384:32:2:f Anagram L1L2unified 1.154186291 85.605 98.80411748

362 2048:32:2:f 16384:32:2:l Anagram L1L2unified 1.154186291 85.6075 98.80700294

363 2048:32:2:f 16384:32:2:r Anagram L1L2unified 1.154579501 85.6025 98.83489171

364 2048:32:2:f 32768:32:1:f Anagram L1L2unified 1.139923516 85.455 97.4121641

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367 2048:32:2:f 4096:32:8:f Anagram L1L2unified 1.187358861 86.505 102.7124782

368 2048:32:2:f 4096:32:8:l Anagram L1L2unified 1.187037144 86.5075 102.6876157

369 2048:32:2:f 4096:32:8:r Anagram L1L2unified 1.162372195 86.5025 100.5481008

370 2048:32:2:f 8192:32:4:f Anagram L1L2unified 1.184427664 85.905 101.7482585

371 2048:32:2:f 8192:32:4:l Anagram L1L2unified 1.184427664 85.9075 101.7512195

372 2048:32:2:f 8192:32:4:r Anagram L1L2unified 1.160978089 85.9025 99.73092029

373 2048:32:2:l 16384:32:2:f Anagram L1L2unified 1.15420365 85.6075 98.80848894

374 2048:32:2:l 16384:32:2:l Anagram L1L2unified 1.15420365 85.61 98.81137445

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376 2048:32:2:l 32768:32:1:f Anagram L1L2unified 1.139906848 85.4575 97.41358945

377 2048:32:2:l 32768:32:1:l Anagram L1L2unified 1.139906848 85.46 97.41643921

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379 2048:32:2:l 4096:32:8:f Anagram L1L2unified 1.187385033 86.5075 102.7177108

380 2048:32:2:l 4096:32:8:l Anagram L1L2unified 1.187029391 86.51 102.6899126

381 2048:32:2:l 4096:32:8:r Anagram L1L2unified 1.162347848 86.505 100.5489006

382 2048:32:2:l 8192:32:4:f Anagram L1L2unified 1.184433206 85.9075 101.7516956

383 2048:32:2:l 8192:32:4:l Anagram L1L2unified 1.184433206 85.91 101.7546567

384 2048:32:2:l 8192:32:4:r Anagram L1L2unified 1.161031973 85.905 99.73845164

385 2048:32:2:r 16384:32:2:f Anagram L1L2unified 1.154223578 85.6025 98.80442386

386 2048:32:2:r 16384:32:2:l Anagram L1L2unified 1.154011096 85.605 98.78911985

387 2048:32:2:r 16384:32:2:r Anagram L1L2unified 1.155751394 85.6 98.93231931

388 2048:32:2:r 32768:32:1:f Anagram L1L2unified 1.14204125 85.4525 97.59027989

389 2048:32:2:r 32768:32:1:l Anagram L1L2unified 1.14204125 85.455 97.59313499

390 2048:32:2:r 32768:32:1:r Anagram L1L2unified 1.14200969 85.45 97.58472802

391 2048:32:2:r 4096:32:8:f Anagram L1L2unified 1.187335431 86.5025 102.7074831

392 2048:32:2:r 4096:32:8:l Anagram L1L2unified 1.184041952 86.505 102.4255491

393 2048:32:2:r 4096:32:8:r Anagram L1L2unified 1.166079438 86.5 100.8658714

394 2048:32:2:r 8192:32:4:f Anagram L1L2unified 1.184431503 85.9025 101.7456272

395 2048:32:2:r 8192:32:4:l Anagram L1L2unified 1.182660816 85.905 101.5964774

396 2048:32:2:r 8192:32:4:r Anagram L1L2unified 1.161005521 85.9 99.73037425

397 2048:64:1:f 16384:64:1:f Anagram L1L2unified 1.086334221 85.305 92.6697407

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402 2048:64:1:f 2048:64:8:r Anagram L1L2unified 1.085610815 86.3525 93.74520794

403 2048:64:1:f 4096:64:4:f Anagram L1L2unified 1.097294906 85.755 94.09852462

404 2048:64:1:f 4096:64:4:l Anagram L1L2unified 1.097316827 85.7575 94.10314778

405 2048:64:1:f 4096:64:4:r Anagram L1L2unified 1.084032477 85.7525 92.95849497

406 2048:64:1:f 8192:64:2:f Anagram L1L2unified 1.082213003 85.455 92.48051219

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410 2048:64:1:l 16384:64:1:l Anagram L1L2unified 1.086334221 85.31 92.67517237

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412 2048:64:1:l 2048:64:8:f Anagram L1L2unified 1.098763637 86.3575 94.88648081

413 2048:64:1:l 2048:64:8:l Anagram L1L2unified 1.098588266 86.36 94.87408268

414 2048:64:1:l 2048:64:8:r Anagram L1L2unified 1.085610815 86.355 93.74792197

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417 2048:64:1:l 4096:64:4:r Anagram L1L2unified 1.084032477 85.755 92.96120505

418 2048:64:1:l 8192:64:2:f Anagram L1L2unified 1.082213003 85.4575 92.48321772

419 2048:64:1:l 8192:64:2:l Anagram L1L2unified 1.082213003 85.46 92.48592325

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421 2048:64:1:r 16384:64:1:f Anagram L1L2unified 1.086334221 85.3025 92.66702486

422 2048:64:1:r 16384:64:1:l Anagram L1L2unified 1.086334221 85.305 92.6697407

423 2048:64:1:r 16384:64:1:r Anagram L1L2unified 1.086334221 85.3 92.66430902

424 2048:64:1:r 2048:64:8:f Anagram L1L2unified 1.098763637 86.3525 94.88098699

425 2048:64:1:r 2048:64:8:l Anagram L1L2unified 1.098588266 86.355 94.86858974

426 2048:64:1:r 2048:64:8:r Anagram L1L2unified 1.085720422 86.35 93.75195847

427 2048:64:1:r 4096:64:4:f Anagram L1L2unified 1.097294906 85.7525 94.09578139

428 2048:64:1:r 4096:64:4:l Anagram L1L2unified 1.097316827 85.755 94.10040449

429 2048:64:1:r 4096:64:4:r Anagram L1L2unified 1.084010555 85.75 92.95390513

430 2048:64:1:r 8192:64:2:f Anagram L1L2unified 1.082213003 85.4525 92.47780665

431 2048:64:1:r 8192:64:2:l Anagram L1L2unified 1.082213003 85.455 92.48051219

432 2048:64:1:r 8192:64:2:r Anagram L1L2unified 1.082673352 85.45 92.51443792

433 256:64:8:f 16384:64:1:f Anagram L1L2unified 1.070904025 86.355 92.47791708

434 256:64:8:f 16384:64:1:l Anagram L1L2unified 1.070904025 86.3575 92.48059434

435 256:64:8:f 16384:64:1:r Anagram L1L2unified 1.070904025 86.3525 92.47523982

436 256:64:8:f 2048:64:8:f Anagram L1L2unified 1.094462682 87.405 95.66151073

437 256:64:8:f 2048:64:8:l Anagram L1L2unified 1.094283529 87.4075 95.64858755

438 256:64:8:f 2048:64:8:r Anagram L1L2unified 1.082154851 87.4025 94.5830394

439 256:64:8:f 4096:64:4:f Anagram L1L2unified 1.09301154 86.805 94.87886677

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446 256:64:8:l 16384:64:1:l Anagram L1L2unified 1.070845642 86.36 92.47822967

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450 256:64:8:l 2048:64:8:r Anagram L1L2unified 1.08200519 87.405 94.57266361

451 256:64:8:l 4096:64:4:f Anagram L1L2unified 1.093004552 86.8075 94.88099268

452 256:64:8:l 4096:64:4:l Anagram L1L2unified 1.093004552 86.81 94.88372519

453 256:64:8:l 4096:64:4:r Anagram L1L2unified 1.081239862 86.805 93.85702622

454 256:64:8:l 8192:64:2:f Anagram L1L2unified 1.077911576 86.5075 93.24743565

455 256:64:8:l 8192:64:2:l Anagram L1L2unified 1.077911576 86.51 93.25013043

456 256:64:8:l 8192:64:2:r Anagram L1L2unified 1.078267542 86.505 93.27553375

457 256:64:8:r 16384:64:1:f Anagram L1L2unified 1.071832535 86.3525 92.55541902

458 256:64:8:r 16384:64:1:l Anagram L1L2unified 1.071832535 86.355 92.5580986

459 256:64:8:r 16384:64:1:r Anagram L1L2unified 1.072661981 86.35 92.6243621

460 256:64:8:r 2048:64:8:f Anagram L1L2unified 1.093498812 87.4025 95.5745299

461 256:64:8:r 2048:64:8:l Anagram L1L2unified 1.091022666 87.405 95.36083612

462 256:64:8:r 2048:64:8:r Anagram L1L2unified 1.085128204 87.4 94.84020505

463 256:64:8:r 4096:64:4:f Anagram L1L2unified 1.092136932 86.8025 94.800216

464 256:64:8:r 4096:64:4:l Anagram L1L2unified 1.09045669 86.805 94.65709295

465 256:64:8:r 4096:64:4:r Anagram L1L2unified 1.082651112 86.8 93.97411651

466 256:64:8:r 8192:64:2:f Anagram L1L2unified 1.077067815 86.5025 93.16905869

467 256:64:8:r 8192:64:2:l Anagram L1L2unified 1.076784827 86.505 93.14727148

468 256:64:8:r 8192:64:2:r Anagram L1L2unified 1.079050254 86.5 93.33784697

469 4096:32:1:f 16384:32:2:f Anagram L1L2unified 1.156787617 85.455 98.85328577

470 4096:32:1:f 16384:32:2:l Anagram L1L2unified 1.156787617 85.4575 98.85617774

471 4096:32:1:f 16384:32:2:r Anagram L1L2unified 1.15758611 85.4525 98.91862702

472 4096:32:1:f 32768:32:1:f Anagram L1L2unified 1.142718931 85.305 97.47963841

473 4096:32:1:f 32768:32:1:l Anagram L1L2unified 1.142718931 85.3075 97.48249521

474 4096:32:1:f 32768:32:1:r Anagram L1L2unified 1.142718931 85.3025 97.47678161

475 4096:32:1:f 4096:32:8:f Anagram L1L2unified 1.189944086 86.355 102.7576216

476 4096:32:1:f 4096:32:8:l Anagram L1L2unified 1.189601875 86.3575 102.7310439

477 4096:32:1:f 4096:32:8:r Anagram L1L2unified 1.163669865 86.3525 100.4858021

478 4096:32:1:f 8192:32:4:f Anagram L1L2unified 1.187016279 85.755 101.792581

479 4096:32:1:f 8192:32:4:l Anagram L1L2unified 1.187016279 85.7575 101.7955485

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495 4096:32:1:r 16384:32:2:r Anagram L1L2unified 1.157243898 85.45 98.88649111

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501 4096:32:1:r 4096:32:8:r Anagram L1L2unified 1.163365678 86.35 100.4566263

502 4096:32:1:r 8192:32:4:f Anagram L1L2unified 1.187016279 85.7525 101.7896134

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504 4096:32:1:r 8192:32:4:r Anagram L1L2unified 1.160247753 85.75 99.4912448

505 512:32:8:f 16384:32:2:f Anagram L1L2unified 1.154214157 86.505 99.84529562

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508 512:32:8:f 32768:32:1:f Anagram L1L2unified 1.139932109 86.355 98.43883727

509 512:32:8:f 32768:32:1:l Anagram L1L2unified 1.139932109 86.3575 98.4416871

510 512:32:8:f 32768:32:1:r Anagram L1L2unified 1.139932109 86.3525 98.43598744

511 512:32:8:f 4096:32:8:f Anagram L1L2unified 1.187372726 87.405 103.7823131

512 512:32:8:f 4096:32:8:l Anagram L1L2unified 1.187016565 87.4075 103.7541504

513 512:32:8:f 4096:32:8:r Anagram L1L2unified 1.162227774 87.4025 101.5816131

514 512:32:8:f 8192:32:4:f Anagram L1L2unified 1.184416592 86.805 102.8132822

515 512:32:8:f 8192:32:4:l Anagram L1L2unified 1.184416592 86.8075 102.8162433

516 512:32:8:f 8192:32:4:r Anagram L1L2unified 1.161052444 86.8025 100.7822548

517 512:32:8:l 16384:32:2:f Anagram L1L2unified 1.154203816 86.5075 99.84728663

518 512:32:8:l 16384:32:2:l Anagram L1L2unified 1.154203816 86.51 99.85017214

519 512:32:8:l 16384:32:2:r Anagram L1L2unified 1.154310129 86.505 99.85359768

520 512:32:8:l 32768:32:1:f Anagram L1L2unified 1.139887083 86.3575 98.43779878

521 512:32:8:l 32768:32:1:l Anagram L1L2unified 1.139887083 86.36 98.4406485

522 512:32:8:l 32768:32:1:r Anagram L1L2unified 1.139887083 86.355 98.43494906

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28

523 512:32:8:l 4096:32:8:f Anagram L1L2unified 1.187373277 87.4075 103.7853297

524 512:32:8:l 4096:32:8:l Anagram L1L2unified 1.187018903 87.41 103.7573223

525 512:32:8:l 4096:32:8:r Anagram L1L2unified 1.162602494 87.405 101.617271

526 512:32:8:l 8192:32:4:f Anagram L1L2unified 1.184431968 86.8075 102.8175781

527 512:32:8:l 8192:32:4:l Anagram L1L2unified 1.184431968 86.81 102.8205392

528 512:32:8:l 8192:32:4:r Anagram L1L2unified 1.161184996 86.805 100.7966635

529 512:32:8:r 16384:32:2:f Anagram L1L2unified 1.1542611 86.5025 99.84647084

530 512:32:8:r 16384:32:2:l Anagram L1L2unified 1.153699089 86.505 99.80073972

531 512:32:8:r 16384:32:2:r Anagram L1L2unified 1.156319208 86.5 100.0216115

532 512:32:8:r 32768:32:1:f Anagram L1L2unified 1.143723391 86.3525 98.76337412

533 512:32:8:r 32768:32:1:l Anagram L1L2unified 1.143723391 86.355 98.76623343

534 512:32:8:r 32768:32:1:r Anagram L1L2unified 1.143722734 86.35 98.76045807

535 512:32:8:r 4096:32:8:f Anagram L1L2unified 1.187349508 87.4025 103.7773154

536 512:32:8:r 4096:32:8:l Anagram L1L2unified 1.182150905 87.405 103.3258998

537 512:32:8:r 4096:32:8:r Anagram L1L2unified 1.168534 87.4 102.1298716

538 512:32:8:r 8192:32:4:f Anagram L1L2unified 1.184434075 86.8025 102.8118388

539 512:32:8:r 8192:32:4:l Anagram L1L2unified 1.180921505 86.805 102.5098913

540 512:32:8:r 8192:32:4:r Anagram L1L2unified 1.163263992 86.8 100.9713145

541 512:64:4:f 16384:64:1:f Anagram L1L2unified 1.070924787 85.755 91.83715513

542 512:64:4:f 16384:64:1:l Anagram L1L2unified 1.070924787 85.7575 91.83983244

543 512:64:4:f 16384:64:1:r Anagram L1L2unified 1.070924787 85.7525 91.83447782

544 512:64:4:f 2048:64:8:f Anagram L1L2unified 1.094473957 86.805 95.00581184

545 512:64:4:f 2048:64:8:l Anagram L1L2unified 1.09429474 86.8075 94.9929906

546 512:64:4:f 2048:64:8:r Anagram L1L2unified 1.082179642 86.8025 93.93589834

547 512:64:4:f 4096:64:4:f Anagram L1L2unified 1.093004374 86.205 94.22244207

548 512:64:4:f 4096:64:4:l Anagram L1L2unified 1.093004374 86.2075 94.22517458

549 512:64:4:f 4096:64:4:r Anagram L1L2unified 1.081373163 86.2025 93.2170701

550 512:64:4:f 8192:64:2:f Anagram L1L2unified 1.077896345 85.905 92.59668552

551 512:64:4:f 8192:64:2:l Anagram L1L2unified 1.077896345 85.9075 92.59938027

552 512:64:4:f 8192:64:2:r Anagram L1L2unified 1.078201015 85.9025 92.62016267

553 512:64:4:l 16384:64:1:f Anagram L1L2unified 1.07084492 85.7575 91.83298326

554 512:64:4:l 16384:64:1:l Anagram L1L2unified 1.07084492 85.76 91.83566038

555 512:64:4:l 16384:64:1:r Anagram L1L2unified 1.07084492 85.755 91.83030615

556 512:64:4:l 2048:64:8:f Anagram L1L2unified 1.094470257 86.8075 95.00822681

557 512:64:4:l 2048:64:8:l Anagram L1L2unified 1.094292221 86.81 94.9955077

558 512:64:4:l 2048:64:8:r Anagram L1L2unified 1.081847526 86.805 93.90977451

559 512:64:4:l 4096:64:4:f Anagram L1L2unified 1.093010364 86.2075 94.22569096

560 512:64:4:l 4096:64:4:l Anagram L1L2unified 1.093010364 86.21 94.22842348

561 512:64:4:l 4096:64:4:r Anagram L1L2unified 1.081295616 86.205 93.21308854

562 512:64:4:l 8192:64:2:f Anagram L1L2unified 1.077895134 85.9075 92.59927621

563 512:64:4:l 8192:64:2:l Anagram L1L2unified 1.077895134 85.91 92.60197095

Page 29: Cache Design for an Alpha Microprocessor

29

564 512:64:4:l 8192:64:2:r Anagram L1L2unified 1.078269009 85.905 92.6286992

565 512:64:4:r 16384:64:1:f Anagram L1L2unified 1.072468348 85.7525 91.96684202

566 512:64:4:r 16384:64:1:l Anagram L1L2unified 1.072468348 85.755 91.96952319

567 512:64:4:r 16384:64:1:r Anagram L1L2unified 1.072296851 85.75 91.94945495

568 512:64:4:r 2048:64:8:f Anagram L1L2unified 1.094440898 86.8025 95.00020603

569 512:64:4:r 2048:64:8:l Anagram L1L2unified 1.092208203 86.805 94.80913308

570 512:64:4:r 2048:64:8:r Anagram L1L2unified 1.084692914 86.8 94.15134489

571 512:64:4:r 4096:64:4:f Anagram L1L2unified 1.093005594 86.2025 94.21981473

572 512:64:4:r 4096:64:4:l Anagram L1L2unified 1.09162345 86.205 94.10339949

573 512:64:4:r 4096:64:4:r Anagram L1L2unified 1.082107918 86.2 93.27770255

574 512:64:4:r 8192:64:2:f Anagram L1L2unified 1.077943766 85.9025 92.59806433

575 512:64:4:r 8192:64:2:l Anagram L1L2unified 1.077713408 85.905 92.58097034

576 512:64:4:r 8192:64:2:r Anagram L1L2unified 1.078497182 85.9 92.64290796

577 1024:32:4:f 16384:32:2:f GO L1L2unified 1.020886414 85.905 87.69924741

578 1024:32:4:f 16384:32:2:l GO L1L2unified 1.020886414 85.9075 87.70179962

579 1024:32:4:f 16384:32:2:r GO L1L2unified 1.021604357 85.9025 87.75836825

580 1024:32:4:f 32768:32:1:f GO L1L2unified 1.038203187 85.755 89.0311143

581 1024:32:4:f 32768:32:1:l GO L1L2unified 1.038203187 85.7575 89.03370981

582 1024:32:4:f 32768:32:1:r GO L1L2unified 1.038203187 85.7525 89.02851879

583 1024:32:4:f 4096:32:8:f GO L1L2unified 1.021963328 86.805 88.71152668

584 1024:32:4:f 4096:32:8:l GO L1L2unified 1.021920251 86.8075 88.71034222

585 1024:32:4:f 4096:32:8:r GO L1L2unified 1.02143205 86.8025 88.66285556

586 1024:32:4:f 8192:32:4:f GO L1L2unified 1.021001285 86.205 88.01541577

587 1024:32:4:f 8192:32:4:l GO L1L2unified 1.020972567 86.2075 88.01549259

588 1024:32:4:f 8192:32:4:r GO L1L2unified 1.021374615 86.2025 88.04504525

589 1024:32:4:l 16384:32:2:f GO L1L2unified 1.018359866 85.9075 87.48475015

590 1024:32:4:l 16384:32:2:l GO L1L2unified 1.018371345 85.91 87.48828227

591 1024:32:4:l 16384:32:2:r GO L1L2unified 1.019106046 85.905 87.54630492

592 1024:32:4:l 32768:32:1:f GO L1L2unified 1.029345944 85.7575 88.27413478

593 1024:32:4:l 32768:32:1:l GO L1L2unified 1.029345944 85.76 88.27670815

594 1024:32:4:l 32768:32:1:r GO L1L2unified 1.029345944 85.755 88.27156142

595 1024:32:4:l 4096:32:8:f GO L1L2unified 1.019461917 86.8075 88.49694039

596 1024:32:4:l 4096:32:8:l GO L1L2unified 1.019415999 86.81 88.49550283

597 1024:32:4:l 4096:32:8:r GO L1L2unified 1.01895681 86.805 88.45054592

598 1024:32:4:l 8192:32:4:f GO L1L2unified 1.018497622 86.2075 87.80213375

599 1024:32:4:l 8192:32:4:l GO L1L2unified 1.018463183 86.21 87.801711

600 1024:32:4:l 8192:32:4:r GO L1L2unified 1.018853493 86.205 87.83026536

601 1024:32:4:r 16384:32:2:f GO L1L2unified 1.019155295 85.9025 87.54798771

602 1024:32:4:r 16384:32:2:l GO L1L2unified 1.019155295 85.905 87.5505356

603 1024:32:4:r 16384:32:2:r GO L1L2unified 1.019917903 85.9 87.61094783

604 1024:32:4:r 32768:32:1:f GO L1L2unified 1.031102274 85.7525 88.41959771

Page 30: Cache Design for an Alpha Microprocessor

30

605 1024:32:4:r 32768:32:1:l GO L1L2unified 1.031102274 85.755 88.42217547

606 1024:32:4:r 32768:32:1:r GO L1L2unified 1.031118349 85.75 88.41839847

607 1024:32:4:r 4096:32:8:f GO L1L2unified 1.020290067 86.8025 88.5637285

608 1024:32:4:r 4096:32:8:l GO L1L2unified 1.020060562 86.805 88.54635709

609 1024:32:4:r 4096:32:8:r GO L1L2unified 1.020043883 86.8 88.53980902

610 1024:32:4:r 8192:32:4:f GO L1L2unified 1.019333798 86.2025 87.86912174

611 1024:32:4:r 8192:32:4:l GO L1L2unified 1.019282797 86.205 87.86727353

612 1024:32:4:r 8192:32:4:r GO L1L2unified 1.019810998 86.2 87.90770802

613 1024:64:2:f 16384:64:1:f GO L1L2unified 1.03617135 85.455 88.54602267

614 1024:64:2:f 16384:64:1:l GO L1L2unified 1.03617135 85.4575 88.5486131

615 1024:64:2:f 16384:64:1:r GO L1L2unified 1.03617135 85.4525 88.54343225

616 1024:64:2:f 2048:64:8:f GO L1L2unified 1.021568026 86.505 88.3707421

617 1024:64:2:f 2048:64:8:l GO L1L2unified 1.021550261 86.5075 88.37175916

618 1024:64:2:f 2048:64:8:r GO L1L2unified 1.021266011 86.5025 88.34206311

619 1024:64:2:f 4096:64:4:f GO L1L2unified 1.021088355 85.905 87.71659513

620 1024:64:2:f 4096:64:4:l GO L1L2unified 1.021070589 85.9075 87.71762165

621 1024:64:2:f 4096:64:4:r GO L1L2unified 1.021248245 85.9025 87.7277774

622 1024:64:2:f 8192:64:2:f GO L1L2unified 1.021159417 85.605 87.41635192

623 1024:64:2:f 8192:64:2:l GO L1L2unified 1.021177183 85.6075 87.42042569

624 1024:64:2:f 8192:64:2:r GO L1L2unified 1.021514729 85.6025 87.44421462

625 1024:64:2:l 16384:64:1:f GO L1L2unified 1.030714985 85.4575 88.08232581

626 1024:64:2:l 16384:64:1:l GO L1L2unified 1.030714985 85.46 88.08490259

627 1024:64:2:l 16384:64:1:r GO L1L2unified 1.030714985 85.455 88.07974902

628 1024:64:2:l 2048:64:8:f GO L1L2unified 1.01906772 86.5075 88.15700077

629 1024:64:2:l 2048:64:8:l GO L1L2unified 1.01905271 86.51 88.15824998

630 1024:64:2:l 2048:64:8:r GO L1L2unified 1.018767533 86.505 88.1284854

631 1024:64:2:l 4096:64:4:f GO L1L2unified 1.018572411 85.9075 87.50300938

632 1024:64:2:l 4096:64:4:l GO L1L2unified 1.018557401 85.91 87.50426636

633 1024:64:2:l 4096:64:4:r GO L1L2unified 1.018737514 85.905 87.51464612

634 1024:64:2:l 8192:64:2:f GO L1L2unified 1.018647458 85.6075 87.20386223

635 1024:64:2:l 8192:64:2:l GO L1L2unified 1.018662467 85.61 87.2076938

636 1024:64:2:l 8192:64:2:r GO L1L2unified 1.019007682 85.605 87.23215264

637 1024:64:2:r 16384:64:1:f GO L1L2unified 1.03468011 85.4525 88.41600212

638 1024:64:2:r 16384:64:1:l GO L1L2unified 1.03468011 85.455 88.41858882

639 1024:64:2:r 16384:64:1:r GO L1L2unified 1.034676764 85.45 88.41312951

640 1024:64:2:r 2048:64:8:f GO L1L2unified 1.021570397 86.5025 88.36839329

641 1024:64:2:r 2048:64:8:l GO L1L2unified 1.021497363 86.505 88.36462936

642 1024:64:2:r 2048:64:8:r GO L1L2unified 1.021349163 86.5 88.34670256

643 1024:64:2:r 4096:64:4:f GO L1L2unified 1.021077414 85.9025 87.71310252

644 1024:64:2:r 4096:64:4:l GO L1L2unified 1.021077414 85.905 87.71565522

645 1024:64:2:r 4096:64:4:r GO L1L2unified 1.021273352 85.9 87.72738093

Page 31: Cache Design for an Alpha Microprocessor

31

646 1024:64:2:r 8192:64:2:f GO L1L2unified 1.021186966 85.6025 87.41615722

647 1024:64:2:r 8192:64:2:l GO L1L2unified 1.021205224 85.605 87.42027322

648 1024:64:2:r 8192:64:2:r GO L1L2unified 1.021511983 85.6 87.44142573

649 2048:32:2:f 16384:32:2:f GO L1L2unified 1.029224174 85.605 88.10673543

650 2048:32:2:f 16384:32:2:l GO L1L2unified 1.029201223 85.6075 88.10734368

651 2048:32:2:f 16384:32:2:r GO L1L2unified 1.029958621 85.6025 88.16703282

652 2048:32:2:f 32768:32:1:f GO L1L2unified 1.050614926 85.455 89.78029854

653 2048:32:2:f 32768:32:1:l GO L1L2unified 1.050614926 85.4575 89.78292507

654 2048:32:2:f 32768:32:1:r GO L1L2unified 1.050614926 85.4525 89.777672

655 2048:32:2:f 4096:32:8:f GO L1L2unified 1.030302892 86.505 89.12635171

656 2048:32:2:f 4096:32:8:l GO L1L2unified 1.030279941 86.5075 89.12694199

657 2048:32:2:f 4096:32:8:r GO L1L2unified 1.029775009 86.5025 89.07811272

658 2048:32:2:f 8192:32:4:f GO L1L2unified 1.029361883 85.905 88.42733255

659 2048:32:2:f 8192:32:4:l GO L1L2unified 1.02931598 85.9075 88.42596255

660 2048:32:2:f 8192:32:4:r GO L1L2unified 1.029706155 85.9025 88.45433295

661 2048:32:2:l 16384:32:2:f GO L1L2unified 1.026695708 85.6075 87.89285285

662 2048:32:2:l 16384:32:2:l GO L1L2unified 1.026695708 85.61 87.89541959

663 2048:32:2:l 16384:32:2:r GO L1L2unified 1.027406675 85.605 87.95114843

664 2048:32:2:l 32768:32:1:f GO L1L2unified 1.04381816 85.4575 89.20209044

665 2048:32:2:l 32768:32:1:l GO L1L2unified 1.04381816 85.46 89.20469998

666 2048:32:2:l 32768:32:1:r GO L1L2unified 1.04381816 85.455 89.19948089

667 2048:32:2:l 4096:32:8:f GO L1L2unified 1.027801657 86.5075 88.91255182

668 2048:32:2:l 4096:32:8:l GO L1L2unified 1.027762159 86.51 88.91170434

669 2048:32:2:l 4096:32:8:r GO L1L2unified 1.027268432 86.505 88.86385568

670 2048:32:2:l 8192:32:4:f GO L1L2unified 1.026853701 85.9075 88.21443431

671 2048:32:2:l 8192:32:4:l GO L1L2unified 1.026794454 85.91 88.21191152

672 2048:32:2:l 8192:32:4:r GO L1L2unified 1.027189435 85.905 88.24070844

673 2048:32:2:r 16384:32:2:f GO L1L2unified 1.029238215 85.6025 88.10536432

674 2048:32:2:r 16384:32:2:l GO L1L2unified 1.029238215 85.605 88.10793741

675 2048:32:2:r 16384:32:2:r GO L1L2unified 1.029979304 85.6 88.16622845

676 2048:32:2:r 32768:32:1:f GO L1L2unified 1.048131751 85.4525 89.56547849

677 2048:32:2:r 32768:32:1:l GO L1L2unified 1.048131751 85.455 89.56809882

678 2048:32:2:r 32768:32:1:r GO L1L2unified 1.048098834 85.45 89.56004533

679 2048:32:2:r 4096:32:8:f GO L1L2unified 1.030307222 86.5025 89.12415049

680 2048:32:2:r 4096:32:8:l GO L1L2unified 1.030144547 86.505 89.11265406

681 2048:32:2:r 4096:32:8:r GO L1L2unified 1.029938179 86.5 89.08965244

682 2048:32:2:r 8192:32:4:f GO L1L2unified 1.029354412 85.9025 88.42411734

683 2048:32:2:r 8192:32:4:l GO L1L2unified 1.029331172 85.905 88.42469436

684 2048:32:2:r 8192:32:4:r GO L1L2unified 1.029793654 85.9 88.45927491

685 2048:64:1:f 16384:64:1:f GO L1L2unified 1.120351157 85.305 95.57155542

686 2048:64:1:f 16384:64:1:l GO L1L2unified 1.120351157 85.3075 95.5743563

Page 32: Cache Design for an Alpha Microprocessor

32

687 2048:64:1:f 16384:64:1:r GO L1L2unified 1.120351157 85.3025 95.56875454

688 2048:64:1:f 2048:64:8:f GO L1L2unified 1.099228122 86.355 94.92384446

689 2048:64:1:f 2048:64:8:l GO L1L2unified 1.099228122 86.3575 94.92659253

690 2048:64:1:f 2048:64:8:r GO L1L2unified 1.098852601 86.3525 94.88866925

691 2048:64:1:f 4096:64:4:f GO L1L2unified 1.098758721 85.755 94.22405413

692 2048:64:1:f 4096:64:4:l GO L1L2unified 1.098758721 85.7575 94.22680102

693 2048:64:1:f 4096:64:4:r GO L1L2unified 1.098852601 85.7525 94.22935769

694 2048:64:1:f 8192:64:2:f GO L1L2unified 1.098852601 85.455 93.90244904

695 2048:64:1:f 8192:64:2:l GO L1L2unified 1.098852601 85.4575 93.90519617

696 2048:64:1:f 8192:64:2:r GO L1L2unified 1.099134242 85.4525 93.92376879

697 2048:64:1:l 16384:64:1:f GO L1L2unified 1.120351157 85.3075 95.5743563

698 2048:64:1:l 16384:64:1:l GO L1L2unified 1.120351157 85.31 95.57715717

699 2048:64:1:l 16384:64:1:r GO L1L2unified 1.120351157 85.305 95.57155542

700 2048:64:1:l 2048:64:8:f GO L1L2unified 1.099228122 86.3575 94.92659253

701 2048:64:1:l 2048:64:8:l GO L1L2unified 1.099228122 86.36 94.9293406

702 2048:64:1:l 2048:64:8:r GO L1L2unified 1.098852601 86.355 94.89141638

703 2048:64:1:l 4096:64:4:f GO L1L2unified 1.098758721 85.7575 94.22680102

704 2048:64:1:l 4096:64:4:l GO L1L2unified 1.098758721 85.76 94.22954792

705 2048:64:1:l 4096:64:4:r GO L1L2unified 1.098852601 85.755 94.23210482

706 2048:64:1:l 8192:64:2:f GO L1L2unified 1.098852601 85.4575 93.90519617

707 2048:64:1:l 8192:64:2:l GO L1L2unified 1.098852601 85.46 93.9079433

708 2048:64:1:l 8192:64:2:r GO L1L2unified 1.099134242 85.455 93.92651662

709 2048:64:1:r 16384:64:1:f GO L1L2unified 1.120351157 85.3025 95.56875454

710 2048:64:1:r 16384:64:1:l GO L1L2unified 1.120351157 85.305 95.57155542

711 2048:64:1:r 16384:64:1:r GO L1L2unified 1.120351157 85.3 95.56595366

712 2048:64:1:r 2048:64:8:f GO L1L2unified 1.099228122 86.3525 94.92109639

713 2048:64:1:r 2048:64:8:l GO L1L2unified 1.099228122 86.355 94.92384446

714 2048:64:1:r 2048:64:8:r GO L1L2unified 1.098946481 86.35 94.89402867

715 2048:64:1:r 4096:64:4:f GO L1L2unified 1.098758721 85.7525 94.22130723

716 2048:64:1:r 4096:64:4:l GO L1L2unified 1.098758721 85.755 94.22405413

717 2048:64:1:r 4096:64:4:r GO L1L2unified 1.098852601 85.75 94.22661056

718 2048:64:1:r 8192:64:2:f GO L1L2unified 1.098852601 85.4525 93.89970191

719 2048:64:1:r 8192:64:2:l GO L1L2unified 1.098852601 85.455 93.90244904

720 2048:64:1:r 8192:64:2:r GO L1L2unified 1.099134242 85.45 93.92102095

721 256:64:8:f 16384:64:1:f GO L1L2unified 1.022288121 86.355 88.27969069

722 256:64:8:f 16384:64:1:l GO L1L2unified 1.022288121 86.3575 88.28224641

723 256:64:8:f 16384:64:1:r GO L1L2unified 1.022288121 86.3525 88.27713497

724 256:64:8:f 2048:64:8:f GO L1L2unified 1.013220302 87.405 88.56052053

725 256:64:8:f 2048:64:8:l GO L1L2unified 1.013220302 87.4075 88.56305358

726 256:64:8:f 2048:64:8:r GO L1L2unified 1.0129392 87.4025 88.53341843

727 256:64:8:f 4096:64:4:f GO L1L2unified 1.01273064 86.805 87.91008322

Page 33: Cache Design for an Alpha Microprocessor

33

728 256:64:8:f 4096:64:4:l GO L1L2unified 1.01273064 86.8075 87.91261504

729 256:64:8:f 4096:64:4:r GO L1L2unified 1.012911997 86.8025 87.92329358

730 256:64:8:f 8192:64:2:f GO L1L2unified 1.012821318 86.505 87.61410814

731 256:64:8:f 8192:64:2:l GO L1L2unified 1.012875725 86.5075 87.6213468

732 256:64:8:f 8192:64:2:r GO L1L2unified 1.013193099 86.5025 87.64373604

733 256:64:8:l 16384:64:1:f GO L1L2unified 1.016169097 86.3575 87.75382279

734 256:64:8:l 16384:64:1:l GO L1L2unified 1.016169097 86.36 87.75636322

735 256:64:8:l 16384:64:1:r GO L1L2unified 1.016169097 86.355 87.75128237

736 256:64:8:l 2048:64:8:f GO L1L2unified 1.011550504 87.4075 88.41710068

737 256:64:8:l 2048:64:8:l GO L1L2unified 1.011550504 87.41 88.41962956

738 256:64:8:l 2048:64:8:r GO L1L2unified 1.011275668 87.405 88.39054973

739 256:64:8:l 4096:64:4:f GO L1L2unified 1.011061161 86.8075 87.76769175

740 256:64:8:l 4096:64:4:l GO L1L2unified 1.011061161 86.81 87.7702194

741 256:64:8:l 4096:64:4:r GO L1L2unified 1.011235448 86.805 87.78029303

742 256:64:8:l 8192:64:2:f GO L1L2unified 1.011134898 86.5075 87.47075217

743 256:64:8:l 8192:64:2:l GO L1L2unified 1.011188524 86.51 87.47791924

744 256:64:8:l 8192:64:2:r GO L1L2unified 1.011490174 86.505 87.49895751

745 256:64:8:r 16384:64:1:f GO L1L2unified 1.016923731 86.3525 87.81390647

746 256:64:8:r 16384:64:1:l GO L1L2unified 1.016923731 86.355 87.81644878

747 256:64:8:r 16384:64:1:r GO L1L2unified 1.016885941 86.35 87.80810104

748 256:64:8:r 2048:64:8:f GO L1L2unified 1.011550628 87.4025 88.41205375

749 256:64:8:r 2048:64:8:l GO L1L2unified 1.01143663 87.405 88.40461864

750 256:64:8:r 2048:64:8:r GO L1L2unified 1.011387128 87.4 88.39523502

751 256:64:8:r 4096:64:4:f GO L1L2unified 1.011064237 86.8025 87.7629034

752 256:64:8:r 4096:64:4:l GO L1L2unified 1.011049037 86.805 87.76411165

753 256:64:8:r 4096:64:4:r GO L1L2unified 1.011302729 86.8 87.78107684

754 256:64:8:r 8192:64:2:f GO L1L2unified 1.011094636 86.5025 87.46221376

755 256:64:8:r 8192:64:2:l GO L1L2unified 1.011117436 86.505 87.46671377

756 256:64:8:r 8192:64:2:r GO L1L2unified 1.011460029 86.5 87.49129247

757 4096:32:1:f 16384:32:2:f GO L1L2unified 1.111897854 85.455 95.01723111

758 4096:32:1:f 16384:32:2:l GO L1L2unified 1.111897854 85.4575 95.02001086

759 4096:32:1:f 16384:32:2:r GO L1L2unified 1.112515064 85.4525 95.06719353

760 4096:32:1:f 32768:32:1:f GO L1L2unified 1.141729684 85.305 97.39525066

761 4096:32:1:f 32768:32:1:l GO L1L2unified 1.141729684 85.3075 97.39810499

762 4096:32:1:f 32768:32:1:r GO L1L2unified 1.141729684 85.3025 97.39239634

763 4096:32:1:f 4096:32:8:f GO L1L2unified 1.113029406 86.355 96.11565437

764 4096:32:1:f 4096:32:8:l GO L1L2unified 1.113029406 86.3575 96.11843694

765 4096:32:1:f 4096:32:8:r GO L1L2unified 1.112412196 86.3525 96.05957415

766 4096:32:1:f 8192:32:4:f GO L1L2unified 1.112000722 85.755 95.35962195

767 4096:32:1:f 8192:32:4:l GO L1L2unified 1.112000722 85.7575 95.36240195

768 4096:32:1:f 8192:32:4:r GO L1L2unified 1.112309328 85.7525 95.38330561

Page 34: Cache Design for an Alpha Microprocessor

34

769 4096:32:1:l 16384:32:2:f GO L1L2unified 1.111897854 85.4575 95.02001086

770 4096:32:1:l 16384:32:2:l GO L1L2unified 1.111897854 85.46 95.0227906

771 4096:32:1:l 16384:32:2:r GO L1L2unified 1.112515064 85.455 95.06997482

772 4096:32:1:l 32768:32:1:f GO L1L2unified 1.141729684 85.3075 97.39810499

773 4096:32:1:l 32768:32:1:l GO L1L2unified 1.141729684 85.31 97.40095931

774 4096:32:1:l 32768:32:1:r GO L1L2unified 1.141729684 85.305 97.39525066

775 4096:32:1:l 4096:32:8:f GO L1L2unified 1.113029406 86.3575 96.11843694

776 4096:32:1:l 4096:32:8:l GO L1L2unified 1.113029406 86.36 96.12121952

777 4096:32:1:l 4096:32:8:r GO L1L2unified 1.112412196 86.355 96.06235518

778 4096:32:1:l 8192:32:4:f GO L1L2unified 1.112000722 85.7575 95.36240195

779 4096:32:1:l 8192:32:4:l GO L1L2unified 1.112000722 85.76 95.36518195

780 4096:32:1:l 8192:32:4:r GO L1L2unified 1.112309328 85.755 95.38608638

781 4096:32:1:r 16384:32:2:f GO L1L2unified 1.111897854 85.4525 95.01445137

782 4096:32:1:r 16384:32:2:l GO L1L2unified 1.111897854 85.455 95.01723111

783 4096:32:1:r 16384:32:2:r GO L1L2unified 1.112515064 85.45 95.06441224

784 4096:32:1:r 32768:32:1:f GO L1L2unified 1.141729684 85.3025 97.39239634

785 4096:32:1:r 32768:32:1:l GO L1L2unified 1.141729684 85.305 97.39525066

786 4096:32:1:r 32768:32:1:r GO L1L2unified 1.141729684 85.3 97.38954201

787 4096:32:1:r 4096:32:8:f GO L1L2unified 1.113029406 86.3525 96.1128718

788 4096:32:1:r 4096:32:8:l GO L1L2unified 1.113029406 86.355 96.11565437

789 4096:32:1:r 4096:32:8:r GO L1L2unified 1.112412196 86.35 96.05679312

790 4096:32:1:r 8192:32:4:f GO L1L2unified 1.112000722 85.7525 95.35684195

791 4096:32:1:r 8192:32:4:l GO L1L2unified 1.112000722 85.755 95.35962195

792 4096:32:1:r 8192:32:4:r GO L1L2unified 1.112309328 85.75 95.38052483

793 512:32:8:f 16384:32:2:f GO L1L2unified 1.020048418 86.505 88.23928841

794 512:32:8:f 16384:32:2:l GO L1L2unified 1.02008879 86.5075 88.24533098

795 512:32:8:f 16384:32:2:r GO L1L2unified 1.020802023 86.5025 88.30192695

796 512:32:8:f 32768:32:1:f GO L1L2unified 1.032590549 86.355 89.16935683

797 512:32:8:f 32768:32:1:l GO L1L2unified 1.032590549 86.3575 89.1719383

798 512:32:8:f 32768:32:1:r GO L1L2unified 1.032590549 86.3525 89.16677535

799 512:32:8:f 4096:32:8:f GO L1L2unified 1.021124996 87.405 89.25143026

800 512:32:8:f 4096:32:8:l GO L1L2unified 1.021098081 87.4075 89.25163055

801 512:32:8:f 4096:32:8:r GO L1L2unified 1.020640536 87.4025 89.20653444

802 512:32:8:f 8192:32:4:f GO L1L2unified 1.020169533 86.805 88.55581632

803 512:32:8:f 8192:32:4:l GO L1L2unified 1.020142619 86.8075 88.55603037

804 512:32:8:f 8192:32:4:r GO L1L2unified 1.02057325 86.8025 88.58830951

805 512:32:8:l 16384:32:2:f GO L1L2unified 1.017519524 86.5075 88.02307026

806 512:32:8:l 16384:32:2:l GO L1L2unified 1.017560161 86.51 88.02912952

807 512:32:8:l 16384:32:2:r GO L1L2unified 1.018271299 86.505 88.08555871

808 512:32:8:l 32768:32:1:f GO L1L2unified 1.024275335 86.3575 88.45385728

809 512:32:8:l 32768:32:1:l GO L1L2unified 1.024275335 86.36 88.45641797

Page 35: Cache Design for an Alpha Microprocessor

35

810 512:32:8:l 32768:32:1:r GO L1L2unified 1.024275335 86.355 88.45129659

811 512:32:8:l 4096:32:8:f GO L1L2unified 1.018626868 87.4075 89.03562795

812 512:32:8:l 4096:32:8:l GO L1L2unified 1.018596391 87.41 89.0355105

813 512:32:8:l 4096:32:8:r GO L1L2unified 1.018118912 87.405 88.98868352

814 512:32:8:l 8192:32:4:f GO L1L2unified 1.017661752 86.8075 88.34067254

815 512:32:8:l 8192:32:4:l GO L1L2unified 1.017631275 86.81 88.34057095

816 512:32:8:l 8192:32:4:r GO L1L2unified 1.018057957 86.805 88.372521

817 512:32:8:r 16384:32:2:f GO L1L2unified 1.018310321 86.5025 88.08638853

818 512:32:8:r 16384:32:2:l GO L1L2unified 1.018321794 86.505 88.08992681

819 512:32:8:r 16384:32:2:r GO L1L2unified 1.019070255 86.5 88.14957704

820 512:32:8:r 32768:32:1:f GO L1L2unified 1.026100774 86.3525 88.6063671

821 512:32:8:r 32768:32:1:l GO L1L2unified 1.026100774 86.355 88.60893235

822 512:32:8:r 32768:32:1:r GO L1L2unified 1.026129773 86.35 88.60630589

823 512:32:8:r 4096:32:8:f GO L1L2unified 1.019457663 87.4025 89.10314839

824 512:32:8:r 4096:32:8:l GO L1L2unified 1.019205248 87.405 89.08363468

825 512:32:8:r 4096:32:8:r GO L1L2unified 1.019224701 87.4 89.08023891

826 512:32:8:r 8192:32:4:f GO L1L2unified 1.018493896 86.8025 88.40781637

827 512:32:8:r 8192:32:4:l GO L1L2unified 1.018448002 86.805 88.40637881

828 512:32:8:r 8192:32:4:r GO L1L2unified 1.019027366 86.8 88.45157535

829 512:64:4:f 16384:64:1:f GO L1L2unified 1.024908163 85.755 87.89099954

830 512:64:4:f 16384:64:1:l GO L1L2unified 1.024908163 85.7575 87.89356181

831 512:64:4:f 16384:64:1:r GO L1L2unified 1.024908163 85.7525 87.88843727

832 512:64:4:f 2048:64:8:f GO L1L2unified 1.013221871 86.805 87.95272449

833 512:64:4:f 2048:64:8:l GO L1L2unified 1.013212654 86.8075 87.9544575

834 512:64:4:f 2048:64:8:r GO L1L2unified 1.012936165 86.8025 87.92539145

835 512:64:4:f 4096:64:4:f GO L1L2unified 1.012733406 86.205 87.30268325

836 512:64:4:f 4096:64:4:l GO L1L2unified 1.01272419 86.2075 87.30442057

837 512:64:4:f 4096:64:4:r GO L1L2unified 1.012908516 86.2025 87.31524634

838 512:64:4:f 8192:64:2:f GO L1L2unified 1.012825569 85.905 87.00678051

839 512:64:4:f 8192:64:2:l GO L1L2unified 1.012853218 85.9075 87.01168783

840 512:64:4:f 8192:64:2:r GO L1L2unified 1.013185005 85.9025 87.03512493

841 512:64:4:l 16384:64:1:f GO L1L2unified 1.018806631 85.7575 87.37030965

842 512:64:4:l 16384:64:1:l GO L1L2unified 1.018806631 85.76 87.37285667

843 512:64:4:l 16384:64:1:r GO L1L2unified 1.018806631 85.755 87.36776264

844 512:64:4:l 2048:64:8:f GO L1L2unified 1.011550884 86.8075 87.81020338

845 512:64:4:l 2048:64:8:l GO L1L2unified 1.011543665 86.81 87.81210552

846 512:64:4:l 2048:64:8:r GO L1L2unified 1.011254879 86.805 87.78197974

847 512:64:4:l 4096:64:4:f GO L1L2unified 1.011059948 86.2075 87.16095047

848 512:64:4:l 4096:64:4:l GO L1L2unified 1.011059948 86.21 87.16347812

849 512:64:4:l 4096:64:4:r GO L1L2unified 1.01123322 86.205 87.1733597

850 512:64:4:l 8192:64:2:f GO L1L2unified 1.011139364 85.9075 86.86445493

Page 36: Cache Design for an Alpha Microprocessor

36

851 512:64:4:l 8192:64:2:l GO L1L2unified 1.011175462 85.91 86.87008398

852 512:64:4:l 8192:64:2:r GO L1L2unified 1.011493127 85.905 86.89231707

853 512:64:4:r 16384:64:1:f GO L1L2unified 1.020708464 85.7525 87.52830258

854 512:64:4:r 16384:64:1:l GO L1L2unified 1.020708464 85.755 87.53085435

855 512:64:4:r 16384:64:1:r GO L1L2unified 1.020746947 85.75 87.52905071

856 512:64:4:r 2048:64:8:f GO L1L2unified 1.012388734 86.8025 87.87787312

857 512:64:4:r 2048:64:8:l GO L1L2unified 1.012280034 86.805 87.87096839

858 512:64:4:r 2048:64:8:r GO L1L2unified 1.012223955 86.8 87.86103932

859 512:64:4:r 4096:64:4:f GO L1L2unified 1.011895404 86.2025 87.22791354

860 512:64:4:r 4096:64:4:l GO L1L2unified 1.011878681 86.205 87.22900167

861 512:64:4:r 4096:64:4:r GO L1L2unified 1.0121254 86.2 87.24520947

862 512:64:4:r 8192:64:2:f GO L1L2unified 1.011945573 85.9025 86.92865458

863 512:64:4:r 8192:64:2:l GO L1L2unified 1.011962296 85.905 86.93262104

864 512:64:4:r 8192:64:2:r GO L1L2unified 1.012307199 85.9 86.95718838

865 2048:32:2:f 16384:32:2:f GCC L1sepL2unified 1.131582136 85.68 96.95395738

866 2048:32:2:f 16384:32:2:l GCC L1sepL2unified 1.127655134 85.6825 96.62031098

867 2048:32:2:f 16384:32:2:r GCC L1sepL2unified 1.134177951 85.6775 97.17353136

868 2048:32:2:f 32768:32:1:f GCC L1sepL2unified 1.165527408 85.53 99.68755918

869 2048:32:2:f 32768:32:1:l GCC L1sepL2unified 1.165527408 85.5325 99.690473

870 2048:32:2:f 32768:32:1:r GCC L1sepL2unified 1.165527408 85.5275 99.68464537

871 2048:32:2:f 4096:32:8:f GCC L1sepL2unified 1.117737789 86.58 96.7737378

872 2048:32:2:f 4096:32:8:l GCC L1sepL2unified 1.109750666 86.5825 96.08498708

873 2048:32:2:f 4096:32:8:r GCC L1sepL2unified 1.122929419 86.5775 97.22042179

874 2048:32:2:f 8192:32:4:f GCC L1sepL2unified 1.123195657 85.98 96.57236255

875 2048:32:2:f 8192:32:4:l GCC L1sepL2unified 1.116539721 85.9825 96.00287655

876 2048:32:2:f 8192:32:4:r GCC L1sepL2unified 1.126922981 85.9775 96.89002056

877 2048:32:2:l 16384:32:2:f GCC L1sepL2unified 1.126487616 85.6825 96.52027516

878 2048:32:2:l 16384:32:2:l GCC L1sepL2unified 1.122926333 85.685 96.21794287

879 2048:32:2:l 16384:32:2:r GCC L1sepL2unified 1.128861804 85.68 96.72087941

880 2048:32:2:l 32768:32:1:f GCC L1sepL2unified 1.157726938 85.5325 99.02327934

881 2048:32:2:l 32768:32:1:l GCC L1sepL2unified 1.157726938 85.535 99.02617366

882 2048:32:2:l 32768:32:1:r GCC L1sepL2unified 1.157726938 85.53 99.02038503

883 2048:32:2:l 4096:32:8:f GCC L1sepL2unified 1.113242143 86.5825 96.38728788

884 2048:32:2:l 4096:32:8:l GCC L1sepL2unified 1.105494791 86.585 95.71926652

885 2048:32:2:l 4096:32:8:r GCC L1sepL2unified 1.118177956 86.58 96.81184746

886 2048:32:2:l 8192:32:4:f GCC L1sepL2unified 1.118615307 85.9825 96.18134062

887 2048:32:2:l 8192:32:4:l GCC L1sepL2unified 1.112242485 85.985 95.63617008

888 2048:32:2:l 8192:32:4:r GCC L1sepL2unified 1.122051632 85.98 96.47399934

889 2048:32:2:r 16384:32:2:f GCC L1sepL2unified 1.132966756 85.6775 97.0697592

890 2048:32:2:r 16384:32:2:l GCC L1sepL2unified 1.129072337 85.68 96.73891783

891 2048:32:2:r 16384:32:2:r GCC L1sepL2unified 1.135557366 85.675 97.28887733

Page 37: Cache Design for an Alpha Microprocessor

37

892 2048:32:2:r 32768:32:1:f GCC L1sepL2unified 1.165488568 85.5275 99.68132348

893 2048:32:2:r 32768:32:1:l GCC L1sepL2unified 1.165488568 85.53 99.6842372

894 2048:32:2:r 32768:32:1:r GCC L1sepL2unified 1.165396968 85.525 99.67057573

895 2048:32:2:r 4096:32:8:f GCC L1sepL2unified 1.119370452 86.5775 96.91229529

896 2048:32:2:r 4096:32:8:l GCC L1sepL2unified 1.111444968 86.58 96.22890534

897 2048:32:2:r 4096:32:8:r GCC L1sepL2unified 1.124627135 86.575 97.36459418

898 2048:32:2:r 8192:32:4:f GCC L1sepL2unified 1.124767979 85.9775 96.70473895

899 2048:32:2:r 8192:32:4:l GCC L1sepL2unified 1.118208958 85.98 96.14360625

900 2048:32:2:r 8192:32:4:r GCC L1sepL2unified 1.128508021 85.975 97.02347707

901 2048:64:1:f 16384:64:1:f GCC L1sepL2unified 1.152854236 85.38 98.43069468

902 2048:64:1:f 16384:64:1:l GCC L1sepL2unified 1.152854236 85.3825 98.43357682

903 2048:64:1:f 16384:64:1:r GCC L1sepL2unified 1.152854236 85.3775 98.42781255

904 2048:64:1:f 2048:64:8:f GCC L1sepL2unified 1.113915777 86.43 96.27574062

905 2048:64:1:f 2048:64:8:l GCC L1sepL2unified 1.10854227 86.4325 95.81407973

906 2048:64:1:f 2048:64:8:r GCC L1sepL2unified 1.116641469 86.4275 96.50853058

907 2048:64:1:f 4096:64:4:f GCC L1sepL2unified 1.117731746 85.83 95.93491577

908 2048:64:1:f 4096:64:4:l GCC L1sepL2unified 1.113214885 85.8325 95.5500166

909 2048:64:1:f 4096:64:4:r GCC L1sepL2unified 1.119600792 85.8275 96.09253699

910 2048:64:1:f 8192:64:2:f GCC L1sepL2unified 1.1229495 85.53 96.0458707

911 2048:64:1:f 8192:64:2:l GCC L1sepL2unified 1.120145931 85.5325 95.80888181

912 2048:64:1:f 8192:64:2:r GCC L1sepL2unified 1.124662792 85.5275 96.18959693

913 2048:64:1:l 16384:64:1:f GCC L1sepL2unified 1.152854236 85.3825 98.43357682

914 2048:64:1:l 16384:64:1:l GCC L1sepL2unified 1.152854236 85.385 98.43645895

915 2048:64:1:l 16384:64:1:r GCC L1sepL2unified 1.152854236 85.38 98.43069468

916 2048:64:1:l 2048:64:8:f GCC L1sepL2unified 1.113915777 86.4325 96.27852541

917 2048:64:1:l 2048:64:8:l GCC L1sepL2unified 1.10854227 86.435 95.81685109

918 2048:64:1:l 2048:64:8:r GCC L1sepL2unified 1.116641469 86.43 96.51132219

919 2048:64:1:l 4096:64:4:f GCC L1sepL2unified 1.117731746 85.8325 95.9377101

920 2048:64:1:l 4096:64:4:l GCC L1sepL2unified 1.113214885 85.835 95.55279964

921 2048:64:1:l 4096:64:4:r GCC L1sepL2unified 1.119600792 85.83 96.09533599

922 2048:64:1:l 8192:64:2:f GCC L1sepL2unified 1.1229495 85.5325 96.04867808

923 2048:64:1:l 8192:64:2:l GCC L1sepL2unified 1.120145931 85.535 95.81168217

924 2048:64:1:l 8192:64:2:r GCC L1sepL2unified 1.124662792 85.53 96.19240858

925 2048:64:1:r 16384:64:1:f GCC L1sepL2unified 1.152854236 85.3775 98.42781255

926 2048:64:1:r 16384:64:1:l GCC L1sepL2unified 1.152854236 85.38 98.43069468

927 2048:64:1:r 16384:64:1:r GCC L1sepL2unified 1.152854236 85.375 98.42493041

928 2048:64:1:r 2048:64:8:f GCC L1sepL2unified 1.113915777 86.4275 96.27295583

929 2048:64:1:r 2048:64:8:l GCC L1sepL2unified 1.10854227 86.43 95.81130838

930 2048:64:1:r 2048:64:8:r GCC L1sepL2unified 1.116719346 86.425 96.51246949

931 2048:64:1:r 4096:64:4:f GCC L1sepL2unified 1.117731746 85.8275 95.93212144

932 2048:64:1:r 4096:64:4:l GCC L1sepL2unified 1.113214885 85.83 95.54723357

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933 2048:64:1:r 4096:64:4:r GCC L1sepL2unified 1.119756546 85.825 96.10310556

934 2048:64:1:r 8192:64:2:f GCC L1sepL2unified 1.1229495 85.5275 96.04306333

935 2048:64:1:r 8192:64:2:l GCC L1sepL2unified 1.120145931 85.53 95.80608144

936 2048:64:1:r 8192:64:2:r GCC L1sepL2unified 1.124662792 85.525 96.18678527

937 256:64:8:f 16384:64:1:f GCC L1sepL2unified 1.103134863 86.43 95.3439462

938 256:64:8:f 16384:64:1:l GCC L1sepL2unified 1.103134863 86.4325 95.34670404

939 256:64:8:f 16384:64:1:r GCC L1sepL2unified 1.103134863 86.4275 95.34118836

940 256:64:8:f 2048:64:8:f GCC L1sepL2unified 1.070607661 87.48 93.65675817

941 256:64:8:f 2048:64:8:l GCC L1sepL2unified 1.065244338 87.4825 93.19023781

942 256:64:8:f 2048:64:8:r GCC L1sepL2unified 1.073462955 87.4775 93.90385565

943 256:64:8:f 4096:64:4:f GCC L1sepL2unified 1.074504752 86.88 93.35297281

944 256:64:8:f 4096:64:4:l GCC L1sepL2unified 1.0699903 86.8825 92.96343224

945 256:64:8:f 4096:64:4:r GCC L1sepL2unified 1.076549759 86.8775 93.52795173

946 256:64:8:f 8192:64:2:f GCC L1sepL2unified 1.079790904 86.58 93.48829648

947 256:64:8:f 8192:64:2:l GCC L1sepL2unified 1.077051365 86.5825 93.25379983

948 256:64:8:f 8192:64:2:r GCC L1sepL2unified 1.081334306 86.5775 93.61922091

949 256:64:8:l 16384:64:1:f GCC L1sepL2unified 1.093307993 86.4325 94.49734308

950 256:64:8:l 16384:64:1:l GCC L1sepL2unified 1.093307993 86.435 94.50007635

951 256:64:8:l 16384:64:1:r GCC L1sepL2unified 1.093307993 86.43 94.49460981

952 256:64:8:l 2048:64:8:f GCC L1sepL2unified 1.064909168 87.4825 93.16091627

953 256:64:8:l 2048:64:8:l GCC L1sepL2unified 1.059915236 87.485 92.72668443

954 256:64:8:l 2048:64:8:r GCC L1sepL2unified 1.067672477 87.48 93.39998826

955 256:64:8:l 4096:64:4:f GCC L1sepL2unified 1.068704556 86.8825 92.85172358

956 256:64:8:l 4096:64:4:l GCC L1sepL2unified 1.064709411 86.885 92.50727714

957 256:64:8:l 4096:64:4:r GCC L1sepL2unified 1.07060225 86.88 93.01392348

958 256:64:8:l 8192:64:2:f GCC L1sepL2unified 1.073365559 86.5825 92.9346735

959 256:64:8:l 8192:64:2:l GCC L1sepL2unified 1.071101643 86.585 92.74133577

960 256:64:8:l 8192:64:2:r GCC L1sepL2unified 1.074564102 86.58 93.03575999

961 256:64:8:r 16384:64:1:f GCC L1sepL2unified 1.10334704 86.4275 95.35952631

962 256:64:8:r 16384:64:1:l GCC L1sepL2unified 1.10334704 86.43 95.36228468

963 256:64:8:r 16384:64:1:r GCC L1sepL2unified 1.103345627 86.425 95.35664584

964 256:64:8:r 2048:64:8:f GCC L1sepL2unified 1.07277223 87.4775 93.84343275

965 256:64:8:r 2048:64:8:l GCC L1sepL2unified 1.067520365 87.48 93.38668155

966 256:64:8:r 2048:64:8:r GCC L1sepL2unified 1.075785151 87.475 94.10430606

967 256:64:8:r 4096:64:4:f GCC L1sepL2unified 1.07659917 86.8775 93.53224442

968 256:64:8:r 4096:64:4:l GCC L1sepL2unified 1.072283684 86.88 93.16000651

969 256:64:8:r 4096:64:4:r GCC L1sepL2unified 1.078690374 86.875 93.71122622

970 256:64:8:r 8192:64:2:f GCC L1sepL2unified 1.081728899 86.5775 93.65338373

971 256:64:8:r 8192:64:2:l GCC L1sepL2unified 1.079041898 86.58 93.42344754

972 256:64:8:r 8192:64:2:r GCC L1sepL2unified 1.082939836 86.575 93.75551634

973 4096:32:1:f 16384:32:2:f GCC L1sepL2unified 1.171155706 85.53 100.1689475

Page 39: Cache Design for an Alpha Microprocessor

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974 4096:32:1:f 16384:32:2:l GCC L1sepL2unified 1.167061644 85.5325 99.82170006

975 4096:32:1:f 16384:32:2:r GCC L1sepL2unified 1.173816846 85.5275 100.3936203

976 4096:32:1:f 32768:32:1:f GCC L1sepL2unified 1.210253996 85.38 103.3314862

977 4096:32:1:f 32768:32:1:l GCC L1sepL2unified 1.210253996 85.3825 103.3345118

978 4096:32:1:f 32768:32:1:r GCC L1sepL2unified 1.210253996 85.3775 103.3284605

979 4096:32:1:f 4096:32:8:f GCC L1sepL2unified 1.157440599 86.43 100.0375909

980 4096:32:1:f 4096:32:8:l GCC L1sepL2unified 1.149457178 86.4325 99.35045755

981 4096:32:1:f 4096:32:8:r GCC L1sepL2unified 1.162455824 86.4275 100.4681508

982 4096:32:1:f 8192:32:4:f GCC L1sepL2unified 1.162865231 85.83 99.80872274

983 4096:32:1:f 8192:32:4:l GCC L1sepL2unified 1.156314732 85.8325 99.2493842

984 4096:32:1:f 8192:32:4:r GCC L1sepL2unified 1.166549886 85.8275 100.1220604

985 4096:32:1:l 16384:32:2:f GCC L1sepL2unified 1.171155706 85.5325 100.1718754

986 4096:32:1:l 16384:32:2:l GCC L1sepL2unified 1.167061644 85.535 99.82461771

987 4096:32:1:l 16384:32:2:r GCC L1sepL2unified 1.173816846 85.53 100.3965548

988 4096:32:1:l 32768:32:1:f GCC L1sepL2unified 1.210253996 85.3825 103.3345118

989 4096:32:1:l 32768:32:1:l GCC L1sepL2unified 1.210253996 85.385 103.3375374

990 4096:32:1:l 32768:32:1:r GCC L1sepL2unified 1.210253996 85.38 103.3314862

991 4096:32:1:l 4096:32:8:f GCC L1sepL2unified 1.157440599 86.4325 100.0404845

992 4096:32:1:l 4096:32:8:l GCC L1sepL2unified 1.149457178 86.435 99.35333119

993 4096:32:1:l 4096:32:8:r GCC L1sepL2unified 1.162455824 86.43 100.4710569

994 4096:32:1:l 8192:32:4:f GCC L1sepL2unified 1.162865231 85.8325 99.8116299

995 4096:32:1:l 8192:32:4:l GCC L1sepL2unified 1.156314732 85.835 99.25227499

996 4096:32:1:l 8192:32:4:r GCC L1sepL2unified 1.166549886 85.83 100.1249767

997 4096:32:1:r 16384:32:2:f GCC L1sepL2unified 1.171155706 85.5275 100.1660196

998 4096:32:1:r 16384:32:2:l GCC L1sepL2unified 1.167061644 85.53 99.8187824

999 4096:32:1:r 16384:32:2:r GCC L1sepL2unified 1.173816846 85.525 100.3906857

1000 4096:32:1:r 32768:32:1:f GCC L1sepL2unified 1.210253996 85.3775 103.3284605

1001 4096:32:1:r 32768:32:1:l GCC L1sepL2unified 1.210253996 85.38 103.3314862

1002 4096:32:1:r 32768:32:1:r GCC L1sepL2unified 1.210253996 85.375 103.3254349

1003 4096:32:1:r 4096:32:8:f GCC L1sepL2unified 1.157440599 86.4275 100.0346973

1004 4096:32:1:r 4096:32:8:l GCC L1sepL2unified 1.149457178 86.43 99.34758391

1005 4096:32:1:r 4096:32:8:r GCC L1sepL2unified 1.162455824 86.425 100.4652446

1006 4096:32:1:r 8192:32:4:f GCC L1sepL2unified 1.162865231 85.8275 99.80581557

1007 4096:32:1:r 8192:32:4:l GCC L1sepL2unified 1.156314732 85.83 99.24649342

1008 4096:32:1:r 8192:32:4:r GCC L1sepL2unified 1.166549886 85.825 100.119144

1009 512:32:8:f 16384:32:2:f GCC L1sepL2unified 1.116047435 86.58 96.62738691

1010 512:32:8:f 16384:32:2:l GCC L1sepL2unified 1.112227143 86.5825 96.29940659

1011 512:32:8:f 16384:32:2:r GCC L1sepL2unified 1.118541237 86.5775 96.84050391

1012 512:32:8:f 32768:32:1:f GCC L1sepL2unified 1.149315811 86.43 99.33536558

1013 512:32:8:f 32768:32:1:l GCC L1sepL2unified 1.149315811 86.4325 99.33823887

1014 512:32:8:f 32768:32:1:r GCC L1sepL2unified 1.149315811 86.4275 99.33249229

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1015 512:32:8:f 4096:32:8:f GCC L1sepL2unified 1.101880519 87.48 96.39250776

1016 512:32:8:f 4096:32:8:l GCC L1sepL2unified 1.093868517 87.4825 95.69435255

1017 512:32:8:f 4096:32:8:r GCC L1sepL2unified 1.106974241 87.4775 96.83533919

1018 512:32:8:f 8192:32:4:f GCC L1sepL2unified 1.107451778 86.88 96.21541045

1019 512:32:8:f 8192:32:4:l GCC L1sepL2unified 1.100819326 86.8825 95.64193512

1020 512:32:8:f 8192:32:4:r GCC L1sepL2unified 1.11127207 86.8775 96.54453924

1021 512:32:8:l 16384:32:2:f GCC L1sepL2unified 1.108182624 86.5825 95.94922205

1022 512:32:8:l 16384:32:2:l GCC L1sepL2unified 1.104961552 86.585 95.67309602

1023 512:32:8:l 16384:32:2:r GCC L1sepL2unified 1.110516734 86.58 96.14853882

1024 512:32:8:l 32768:32:1:f GCC L1sepL2unified 1.136938857 86.4325 98.26846776

1025 512:32:8:l 32768:32:1:l GCC L1sepL2unified 1.136938857 86.435 98.27131011

1026 512:32:8:l 32768:32:1:r GCC L1sepL2unified 1.136938857 86.43 98.26562542

1027 512:32:8:l 4096:32:8:f GCC L1sepL2unified 1.095064927 87.4825 95.79901746

1028 512:32:8:l 4096:32:8:l GCC L1sepL2unified 1.087549093 87.485 95.14423242

1029 512:32:8:l 4096:32:8:r GCC L1sepL2unified 1.100106604 87.48 96.23732572

1030 512:32:8:l 8192:32:4:f GCC L1sepL2unified 1.100433379 86.8825 95.60840309

1031 512:32:8:l 8192:32:4:l GCC L1sepL2unified 1.09450474 86.885 95.09604438

1032 512:32:8:l 8192:32:4:r GCC L1sepL2unified 1.103981226 86.88 95.91388895

1033 512:32:8:r 16384:32:2:f GCC L1sepL2unified 1.118641083 86.5775 96.84914834

1034 512:32:8:r 16384:32:2:l GCC L1sepL2unified 1.11488035 86.58 96.5263407

1035 512:32:8:r 16384:32:2:r GCC L1sepL2unified 1.1210859 86.575 97.05801181

1036 512:32:8:r 32768:32:1:f GCC L1sepL2unified 1.149175988 86.4275 99.32040769

1037 512:32:8:r 32768:32:1:l GCC L1sepL2unified 1.149175988 86.43 99.32328063

1038 512:32:8:r 32768:32:1:r GCC L1sepL2unified 1.149221405 86.425 99.3214599

1039 512:32:8:r 4096:32:8:f GCC L1sepL2unified 1.10494528 87.4775 96.6578507

1040 512:32:8:r 4096:32:8:l GCC L1sepL2unified 1.097143162 87.48 95.97808384

1041 512:32:8:r 4096:32:8:r GCC L1sepL2unified 1.110394899 87.475 97.1317938

1042 512:32:8:r 8192:32:4:f GCC L1sepL2unified 1.110446053 86.8775 96.47277697

1043 512:32:8:r 8192:32:4:l GCC L1sepL2unified 1.104047194 86.88 95.91962024

1044 512:32:8:r 8192:32:4:r GCC L1sepL2unified 1.114210389 86.875 96.79702753

1045 512:64:4:f 16384:64:1:f GCC L1sepL2unified 1.106487164 85.83 94.96979328

1046 512:64:4:f 16384:64:1:l GCC L1sepL2unified 1.106487164 85.8325 94.9725595

1047 512:64:4:f 16384:64:1:r GCC L1sepL2unified 1.106487164 85.8275 94.96702706

1048 512:64:4:f 2048:64:8:f GCC L1sepL2unified 1.073726184 86.88 93.28533084

1049 512:64:4:f 2048:64:8:l GCC L1sepL2unified 1.068334615 86.8825 92.81958221

1050 512:64:4:f 2048:64:8:r GCC L1sepL2unified 1.076566017 86.8775 93.52936417

1051 512:64:4:f 4096:64:4:f GCC L1sepL2unified 1.077553786 86.28 92.97134062

1052 512:64:4:f 4096:64:4:l GCC L1sepL2unified 1.073026514 86.2825 92.58341024

1053 512:64:4:f 4096:64:4:r GCC L1sepL2unified 1.079611636 86.2775 93.14619294

1054 512:64:4:f 8192:64:2:f GCC L1sepL2unified 1.082821883 85.98 93.1010255

1055 512:64:4:f 8192:64:2:l GCC L1sepL2unified 1.080064363 85.9825 92.86663411

Page 41: Cache Design for an Alpha Microprocessor

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1056 512:64:4:f 8192:64:2:r GCC L1sepL2unified 1.084344692 85.9775 93.22924579

1057 512:64:4:l 16384:64:1:f GCC L1sepL2unified 1.097683309 85.8325 94.2169026

1058 512:64:4:l 16384:64:1:l GCC L1sepL2unified 1.097683309 85.835 94.2196468

1059 512:64:4:l 16384:64:1:r GCC L1sepL2unified 1.097683309 85.83 94.21415839

1060 512:64:4:l 2048:64:8:f GCC L1sepL2unified 1.068253387 86.8825 92.81252493

1061 512:64:4:l 2048:64:8:l GCC L1sepL2unified 1.063178004 86.885 92.37422087

1062 512:64:4:l 2048:64:8:r GCC L1sepL2unified 1.071101444 86.88 93.05729348

1063 512:64:4:l 4096:64:4:f GCC L1sepL2unified 1.072014283 86.2825 92.49607237

1064 512:64:4:l 4096:64:4:l GCC L1sepL2unified 1.067924765 86.285 92.14588838

1065 512:64:4:l 4096:64:4:r GCC L1sepL2unified 1.073839961 86.28 92.65091179

1066 512:64:4:l 8192:64:2:f GCC L1sepL2unified 1.076761045 85.9825 92.58260651

1067 512:64:4:l 8192:64:2:l GCC L1sepL2unified 1.074387664 85.985 92.38122327

1068 512:64:4:l 8192:64:2:r GCC L1sepL2unified 1.078112046 85.98 92.6960737

1069 512:64:4:r 16384:64:1:f GCC L1sepL2unified 1.106427314 85.8275 94.96189029

1070 512:64:4:r 16384:64:1:l GCC L1sepL2unified 1.106427314 85.83 94.96465636

1071 512:64:4:r 16384:64:1:r GCC L1sepL2unified 1.106363191 85.825 94.95362086

1072 512:64:4:r 2048:64:8:f GCC L1sepL2unified 1.075276535 86.8775 93.41733715

1073 512:64:4:r 2048:64:8:l GCC L1sepL2unified 1.069984344 86.88 92.96023984

1074 512:64:4:r 2048:64:8:r GCC L1sepL2unified 1.078257623 86.875 93.67363104

1075 512:64:4:r 4096:64:4:f GCC L1sepL2unified 1.079062817 86.2775 93.09884222

1076 512:64:4:r 4096:64:4:l GCC L1sepL2unified 1.074717198 86.28 92.7265998

1077 512:64:4:r 4096:64:4:r GCC L1sepL2unified 1.081073147 86.275 93.26958572

1078 512:64:4:r 8192:64:2:f GCC L1sepL2unified 1.084182904 85.9775 93.21533562

1079 512:64:4:r 8192:64:2:l GCC L1sepL2unified 1.08147227 85.98 92.98498576

1080 512:64:4:r 8192:64:2:r GCC L1sepL2unified 1.085755305 85.975 93.34781232

1081 1024:32:4:f 16384:32:2:f GCC L1sepL2unified 1.119511657 85.98 96.25561225

1082 1024:32:4:f 16384:32:2:l GCC L1sepL2unified 1.115699421 85.9825 95.93062547

1083 1024:32:4:f 16384:32:2:r GCC L1sepL2unified 1.122146584 85.9775 96.47935797

1084 1024:32:4:f 32768:32:1:f GCC L1sepL2unified 1.152980844 85.83 98.96034587

1085 1024:32:4:f 32768:32:1:l GCC L1sepL2unified 1.152980844 85.8325 98.96322833

1086 1024:32:4:f 32768:32:1:r GCC L1sepL2unified 1.152980844 85.8275 98.95746342

1087 1024:32:4:f 4096:32:8:f GCC L1sepL2unified 1.105496084 86.88 96.04549979

1088 1024:32:4:f 4096:32:8:l GCC L1sepL2unified 1.097535239 86.8825 95.35660539

1089 1024:32:4:f 4096:32:8:r GCC L1sepL2unified 1.110653815 86.8775 96.4908268

1090 1024:32:4:f 8192:32:4:f GCC L1sepL2unified 1.111046251 86.28 95.86107053

1091 1024:32:4:f 8192:32:4:l GCC L1sepL2unified 1.104430901 86.2825 95.29305918

1092 1024:32:4:f 8192:32:4:r GCC L1sepL2unified 1.114858487 86.2775 96.18720309

1093 1024:32:4:l 16384:32:2:f GCC L1sepL2unified 1.112370507 85.9825 95.6443971

1094 1024:32:4:l 16384:32:2:l GCC L1sepL2unified 1.108995032 85.985 95.3569378

1095 1024:32:4:l 16384:32:2:r GCC L1sepL2unified 1.114889518 85.98 95.85820076

1096 1024:32:4:l 32768:32:1:f GCC L1sepL2unified 1.141994079 85.8325 98.02020675

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1097 1024:32:4:l 32768:32:1:l GCC L1sepL2unified 1.141994079 85.835 98.02306174

1098 1024:32:4:l 32768:32:1:r GCC L1sepL2unified 1.141994079 85.83 98.01735177

1099 1024:32:4:l 4096:32:8:f GCC L1sepL2unified 1.099221268 86.8825 95.50309184

1100 1024:32:4:l 4096:32:8:l GCC L1sepL2unified 1.091613854 86.885 94.84486974

1101 1024:32:4:l 4096:32:8:r GCC L1sepL2unified 1.104309671 86.88 95.94242421

1102 1024:32:4:l 8192:32:4:f GCC L1sepL2unified 1.104611952 86.2825 95.30868077

1103 1024:32:4:l 8192:32:4:l GCC L1sepL2unified 1.098515945 86.285 94.78544832

1104 1024:32:4:l 8192:32:4:r GCC L1sepL2unified 1.108239328 86.28 95.61888925

1105 1024:32:4:r 16384:32:2:f GCC L1sepL2unified 1.121608595 85.9775 96.433103

1106 1024:32:4:r 16384:32:2:l GCC L1sepL2unified 1.117848817 85.98 96.11264127

1107 1024:32:4:r 16384:32:2:r GCC L1sepL2unified 1.124407265 85.975 96.67091462

1108 1024:32:4:r 32768:32:1:f GCC L1sepL2unified 1.152744261 85.8275 98.9371581

1109 1024:32:4:r 32768:32:1:l GCC L1sepL2unified 1.152744261 85.83 98.94003996

1110 1024:32:4:r 32768:32:1:r GCC L1sepL2unified 1.15291971 85.825 98.94933415

1111 1024:32:4:r 4096:32:8:f GCC L1sepL2unified 1.108038145 86.8775 96.26358391

1112 1024:32:4:r 4096:32:8:l GCC L1sepL2unified 1.100166108 86.88 95.58243148

1113 1024:32:4:r 4096:32:8:r GCC L1sepL2unified 1.113387862 86.875 96.72557055

1114 1024:32:4:r 8192:32:4:f GCC L1sepL2unified 1.113442826 86.2775 96.06506344

1115 1024:32:4:r 8192:32:4:l GCC L1sepL2unified 1.107039453 86.28 95.51536404

1116 1024:32:4:r 8192:32:4:r GCC L1sepL2unified 1.117293351 86.275 96.39448382

1117 1024:64:2:f 16384:64:1:f GCC L1sepL2unified 1.116309913 85.53 95.47798686

1118 1024:64:2:f 16384:64:1:l GCC L1sepL2unified 1.116309913 85.5325 95.48077763

1119 1024:64:2:f 16384:64:1:r GCC L1sepL2unified 1.116309913 85.5275 95.47519608

1120 1024:64:2:f 2048:64:8:f GCC L1sepL2unified 1.082695502 86.58 93.73977657

1121 1024:64:2:f 2048:64:8:l GCC L1sepL2unified 1.077364582 86.5825 93.28091894

1122 1024:64:2:f 2048:64:8:r GCC L1sepL2unified 1.085607764 86.5775 93.98920617

1123 1024:64:2:f 4096:64:4:f GCC L1sepL2unified 1.08649625 85.98 93.41694761

1124 1024:64:2:f 4096:64:4:l GCC L1sepL2unified 1.082004457 85.9825 93.03344821

1125 1024:64:2:f 4096:64:4:r GCC L1sepL2unified 1.088470665 85.9775 93.58398661

1126 1024:64:2:f 8192:64:2:f GCC L1sepL2unified 1.091728449 85.68 93.53929355

1127 1024:64:2:f 8192:64:2:l GCC L1sepL2unified 1.088964269 85.6825 93.30518096

1128 1024:64:2:f 8192:64:2:r GCC L1sepL2unified 1.093209261 85.6775 93.66343642

1129 1024:64:2:l 16384:64:1:f GCC L1sepL2unified 1.110400165 85.5325 94.97530207

1130 1024:64:2:l 16384:64:1:l GCC L1sepL2unified 1.110400165 85.535 94.97807807

1131 1024:64:2:l 16384:64:1:r GCC L1sepL2unified 1.110400165 85.53 94.97252607

1132 1024:64:2:l 2048:64:8:f GCC L1sepL2unified 1.079211383 86.5825 93.44081958

1133 1024:64:2:l 2048:64:8:l GCC L1sepL2unified 1.074044011 86.585 92.99610069

1134 1024:64:2:l 2048:64:8:r GCC L1sepL2unified 1.08211803 86.58 93.68977903

1135 1024:64:2:l 4096:64:4:f GCC L1sepL2unified 1.082994638 85.9825 93.11858643

1136 1024:64:2:l 4096:64:4:l GCC L1sepL2unified 1.078703873 85.985 92.75235255

1137 1024:64:2:l 4096:64:4:r GCC L1sepL2unified 1.084840128 85.98 93.27455418

Page 43: Cache Design for an Alpha Microprocessor

43

1138 1024:64:2:l 8192:64:2:f GCC L1sepL2unified 1.087839049 85.6825 93.20876931

1139 1024:64:2:l 8192:64:2:l GCC L1sepL2unified 1.085347637 85.685 92.99801231

1140 1024:64:2:l 8192:64:2:r GCC L1sepL2unified 1.089361578 85.68 93.33650002

1141 1024:64:2:r 16384:64:1:f GCC L1sepL2unified 1.11631603 85.5275 95.47571928

1142 1024:64:2:r 16384:64:1:l GCC L1sepL2unified 1.11631603 85.53 95.47851007

1143 1024:64:2:r 16384:64:1:r GCC L1sepL2unified 1.11631798 85.525 95.47309528

1144 1024:64:2:r 2048:64:8:f GCC L1sepL2unified 1.083904684 86.5775 93.84175775

1145 1024:64:2:r 2048:64:8:l GCC L1sepL2unified 1.07863784 86.58 93.38846417

1146 1024:64:2:r 2048:64:8:r GCC L1sepL2unified 1.086786036 86.575 94.08850106

1147 1024:64:2:r 4096:64:4:f GCC L1sepL2unified 1.087702888 85.9775 93.51797508

1148 1024:64:2:r 4096:64:4:l GCC L1sepL2unified 1.083296971 85.98 93.14187356

1149 1024:64:2:r 4096:64:4:r GCC L1sepL2unified 1.089615561 85.975 93.67969786

1150 1024:64:2:r 8192:64:2:f GCC L1sepL2unified 1.092767161 85.6775 93.62555846

1151 1024:64:2:r 8192:64:2:l GCC L1sepL2unified 1.090083097 85.68 93.39831972

1152 1024:64:2:r 8192:64:2:r GCC L1sepL2unified 1.094402703 85.675 93.76295156

1153 2048:32:2:f 16384:32:2:f Anagram L1sepL2unified 1.153938988 85.68 98.86949253

1154 2048:32:2:f 16384:32:2:l Anagram L1sepL2unified 1.153938988 85.6825 98.87237738

1155 2048:32:2:f 16384:32:2:r Anagram L1sepL2unified 1.15418797 85.6775 98.88793983

1156 2048:32:2:f 32768:32:1:f Anagram L1sepL2unified 1.138857797 85.53 97.40650735

1157 2048:32:2:f 32768:32:1:l Anagram L1sepL2unified 1.138857797 85.5325 97.40935449

1158 2048:32:2:f 32768:32:1:r Anagram L1sepL2unified 1.138857797 85.5275 97.40366021

1159 2048:32:2:f 4096:32:8:f Anagram L1sepL2unified 1.187124724 86.58 102.7812586

1160 2048:32:2:f 4096:32:8:l Anagram L1sepL2unified 1.186769036 86.5825 102.75343

1161 2048:32:2:f 4096:32:8:r Anagram L1sepL2unified 1.161123896 86.5775 100.5272041

1162 2048:32:2:f 8192:32:4:f Anagram L1sepL2unified 1.18417251 85.98 101.8151524

1163 2048:32:2:f 8192:32:4:l Anagram L1sepL2unified 1.18417251 85.9825 101.8181128

1164 2048:32:2:f 8192:32:4:r Anagram L1sepL2unified 1.159309885 85.9775 99.6745656

1165 2048:32:2:l 16384:32:2:f Anagram L1sepL2unified 1.153665755 85.6825 98.84896602

1166 2048:32:2:l 16384:32:2:l Anagram L1sepL2unified 1.153665755 85.685 98.85185019

1167 2048:32:2:l 16384:32:2:r Anagram L1sepL2unified 1.15394895 85.68 98.870346

1168 2048:32:2:l 32768:32:1:f Anagram L1sepL2unified 1.138550227 85.5325 97.38304727

1169 2048:32:2:l 32768:32:1:l Anagram L1sepL2unified 1.138550227 85.535 97.38589364

1170 2048:32:2:l 32768:32:1:r Anagram L1sepL2unified 1.138550227 85.53 97.38020089

1171 2048:32:2:l 4096:32:8:f Anagram L1sepL2unified 1.186870357 86.5825 102.7622027

1172 2048:32:2:l 4096:32:8:l Anagram L1sepL2unified 1.186516363 86.585 102.7345193

1173 2048:32:2:l 4096:32:8:r Anagram L1sepL2unified 1.160674829 86.58 100.4912267

1174 2048:32:2:l 8192:32:4:f Anagram L1sepL2unified 1.18393221 85.9825 101.7974512

1175 2048:32:2:l 8192:32:4:l Anagram L1sepL2unified 1.18393221 85.985 101.8004111

1176 2048:32:2:l 8192:32:4:r Anagram L1sepL2unified 1.158763263 85.98 99.63046535

1177 2048:32:2:r 16384:32:2:f Anagram L1sepL2unified 1.153954022 85.6775 98.8678957

1178 2048:32:2:r 16384:32:2:l Anagram L1sepL2unified 1.153954022 85.68 98.87078058

Page 44: Cache Design for an Alpha Microprocessor

44

1179 2048:32:2:r 16384:32:2:r Anagram L1sepL2unified 1.154167045 85.675 98.88326161

1180 2048:32:2:r 32768:32:1:f Anagram L1sepL2unified 1.139011828 85.5275 97.41683412

1181 2048:32:2:r 32768:32:1:l Anagram L1sepL2unified 1.139011828 85.53 97.41968165

1182 2048:32:2:r 32768:32:1:r Anagram L1sepL2unified 1.139014313 85.525 97.4141991

1183 2048:32:2:r 4096:32:8:f Anagram L1sepL2unified 1.187154934 86.5775 102.7809063

1184 2048:32:2:r 4096:32:8:l Anagram L1sepL2unified 1.186406042 86.58 102.7190351

1185 2048:32:2:r 4096:32:8:r Anagram L1sepL2unified 1.161508269 86.575 100.5575784

1186 2048:32:2:r 8192:32:4:f Anagram L1sepL2unified 1.184195025 85.9775 101.8141277

1187 2048:32:2:r 8192:32:4:l Anagram L1sepL2unified 1.184159363 85.98 101.8140221

1188 2048:32:2:r 8192:32:4:r Anagram L1sepL2unified 1.158680283 85.975 99.61753733

1189 2048:64:1:f 16384:64:1:f Anagram L1sepL2unified 1.090363368 85.38 93.09522434

1190 2048:64:1:f 16384:64:1:l Anagram L1sepL2unified 1.090363368 85.3825 93.09795025

1191 2048:64:1:f 16384:64:1:r Anagram L1sepL2unified 1.090363368 85.3775 93.09249844

1192 2048:64:1:f 2048:64:8:f Anagram L1sepL2unified 1.10348602 86.43 95.37429668

1193 2048:64:1:f 2048:64:8:l Anagram L1sepL2unified 1.103324676 86.4325 95.36311002

1194 2048:64:1:f 2048:64:8:r Anagram L1sepL2unified 1.090175133 86.4275 94.22111131

1195 2048:64:1:f 4096:64:4:f Anagram L1sepL2unified 1.102033923 85.83 94.58757161

1196 2048:64:1:f 4096:64:4:l Anagram L1sepL2unified 1.102033923 85.8325 94.59032669

1197 2048:64:1:f 4096:64:4:r Anagram L1sepL2unified 1.08848102 85.8275 93.42160476

1198 2048:64:1:f 8192:64:2:f Anagram L1sepL2unified 1.086921361 85.53 92.96438399

1199 2048:64:1:f 8192:64:2:l Anagram L1sepL2unified 1.086921361 85.5325 92.96710129

1200 2048:64:1:f 8192:64:2:r Anagram L1sepL2unified 1.087163377 85.5275 92.98236572

1201 2048:64:1:l 16384:64:1:f Anagram L1sepL2unified 1.090363368 85.3825 93.09795025

1202 2048:64:1:l 16384:64:1:l Anagram L1sepL2unified 1.090363368 85.385 93.10067616

1203 2048:64:1:l 16384:64:1:r Anagram L1sepL2unified 1.090363368 85.38 93.09522434

1204 2048:64:1:l 2048:64:8:f Anagram L1sepL2unified 1.10348602 86.4325 95.37705539

1205 2048:64:1:l 2048:64:8:l Anagram L1sepL2unified 1.103324676 86.435 95.36586833

1206 2048:64:1:l 2048:64:8:r Anagram L1sepL2unified 1.090175133 86.43 94.22383675

1207 2048:64:1:l 4096:64:4:f Anagram L1sepL2unified 1.102033923 85.8325 94.59032669

1208 2048:64:1:l 4096:64:4:l Anagram L1sepL2unified 1.102033923 85.835 94.59308177

1209 2048:64:1:l 4096:64:4:r Anagram L1sepL2unified 1.08848102 85.83 93.42432597

1210 2048:64:1:l 8192:64:2:f Anagram L1sepL2unified 1.086921361 85.5325 92.96710129

1211 2048:64:1:l 8192:64:2:l Anagram L1sepL2unified 1.086921361 85.535 92.96981859

1212 2048:64:1:l 8192:64:2:r Anagram L1sepL2unified 1.087163377 85.53 92.98508363

1213 2048:64:1:r 16384:64:1:f Anagram L1sepL2unified 1.090363368 85.3775 93.09249844

1214 2048:64:1:r 16384:64:1:l Anagram L1sepL2unified 1.090363368 85.38 93.09522434

1215 2048:64:1:r 16384:64:1:r Anagram L1sepL2unified 1.090363368 85.375 93.08977253

1216 2048:64:1:r 2048:64:8:f Anagram L1sepL2unified 1.10348602 86.4275 95.37153796

1217 2048:64:1:r 2048:64:8:l Anagram L1sepL2unified 1.103324676 86.43 95.36035171

1218 2048:64:1:r 2048:64:8:r Anagram L1sepL2unified 1.090336477 86.425 94.23233004

1219 2048:64:1:r 4096:64:4:f Anagram L1sepL2unified 1.102033923 85.8275 94.58481652

Page 45: Cache Design for an Alpha Microprocessor

45

1220 2048:64:1:r 4096:64:4:l Anagram L1sepL2unified 1.102033923 85.83 94.58757161

1221 2048:64:1:r 4096:64:4:r Anagram L1sepL2unified 1.088776818 85.825 93.44427038

1222 2048:64:1:r 8192:64:2:f Anagram L1sepL2unified 1.086921361 85.5275 92.96166668

1223 2048:64:1:r 8192:64:2:l Anagram L1sepL2unified 1.086921361 85.53 92.96438399

1224 2048:64:1:r 8192:64:2:r Anagram L1sepL2unified 1.086921361 85.525 92.95894938

1225 256:64:8:f 16384:64:1:f Anagram L1sepL2unified 1.069791108 86.43 92.46204544

1226 256:64:8:f 16384:64:1:l Anagram L1sepL2unified 1.069791108 86.4325 92.46471992

1227 256:64:8:f 16384:64:1:r Anagram L1sepL2unified 1.069791108 86.4275 92.45937096

1228 256:64:8:f 2048:64:8:f Anagram L1sepL2unified 1.093841934 87.48 95.68929234

1229 256:64:8:f 2048:64:8:l Anagram L1sepL2unified 1.093663515 87.4825 95.67641845

1230 256:64:8:f 2048:64:8:r Anagram L1sepL2unified 1.080960111 87.4775 94.55968815

1231 256:64:8:f 4096:64:4:f Anagram L1sepL2unified 1.092378901 86.88 94.90587893

1232 256:64:8:f 4096:64:4:l Anagram L1sepL2unified 1.092378901 86.8825 94.90860987

1233 256:64:8:f 4096:64:4:r Anagram L1sepL2unified 1.08008586 86.8775 93.83515933

1234 256:64:8:f 8192:64:2:f Anagram L1sepL2unified 1.077266847 86.58 93.26976358

1235 256:64:8:f 8192:64:2:l Anagram L1sepL2unified 1.077266847 86.5825 93.27245675

1236 256:64:8:f 8192:64:2:r Anagram L1sepL2unified 1.077463107 86.5775 93.28406215

1237 256:64:8:l 16384:64:1:f Anagram L1sepL2unified 1.069727321 86.4325 92.4592067

1238 256:64:8:l 16384:64:1:l Anagram L1sepL2unified 1.069727321 86.435 92.46188102

1239 256:64:8:l 16384:64:1:r Anagram L1sepL2unified 1.069727321 86.43 92.45653238

1240 256:64:8:l 2048:64:8:f Anagram L1sepL2unified 1.093832856 87.4825 95.69123285

1241 256:64:8:l 2048:64:8:l Anagram L1sepL2unified 1.093673452 87.485 95.68002191

1242 256:64:8:l 2048:64:8:r Anagram L1sepL2unified 1.080974209 87.48 94.56362384

1243 256:64:8:l 4096:64:4:f Anagram L1sepL2unified 1.092380502 86.8825 94.90874899

1244 256:64:8:l 4096:64:4:l Anagram L1sepL2unified 1.092380502 86.885 94.91147994

1245 256:64:8:l 4096:64:4:r Anagram L1sepL2unified 1.079805242 86.88 93.81347938

1246 256:64:8:l 8192:64:2:f Anagram L1sepL2unified 1.077272478 86.5825 93.2729443

1247 256:64:8:l 8192:64:2:l Anagram L1sepL2unified 1.077272478 86.585 93.27563748

1248 256:64:8:l 8192:64:2:r Anagram L1sepL2unified 1.077573576 86.58 93.29632017

1249 256:64:8:r 16384:64:1:f Anagram L1sepL2unified 1.070045508 86.4275 92.48135817

1250 256:64:8:r 16384:64:1:l Anagram L1sepL2unified 1.070045508 86.43 92.48403329

1251 256:64:8:r 16384:64:1:r Anagram L1sepL2unified 1.07007193 86.425 92.48096654

1252 256:64:8:r 2048:64:8:f Anagram L1sepL2unified 1.09388672 87.4775 95.69047556

1253 256:64:8:r 2048:64:8:l Anagram L1sepL2unified 1.093242363 87.48 95.63684192

1254 256:64:8:r 2048:64:8:r Anagram L1sepL2unified 1.081776595 87.475 94.62840769

1255 256:64:8:r 4096:64:4:f Anagram L1sepL2unified 1.092419018 86.8775 94.90663323

1256 256:64:8:r 4096:64:4:l Anagram L1sepL2unified 1.092275827 86.88 94.89692389

1257 256:64:8:r 4096:64:4:r Anagram L1sepL2unified 1.080225764 86.875 93.84461329

1258 256:64:8:r 8192:64:2:f Anagram L1sepL2unified 1.077312424 86.5775 93.27101641

1259 256:64:8:r 8192:64:2:l Anagram L1sepL2unified 1.077294525 86.58 93.27216001

1260 256:64:8:r 8192:64:2:r Anagram L1sepL2unified 1.077484357 86.575 93.2832082

Page 46: Cache Design for an Alpha Microprocessor

46

1261 4096:32:1:f 16384:32:2:f Anagram L1sepL2unified 1.16148415 85.53 99.34173934

1262 4096:32:1:f 16384:32:2:l Anagram L1sepL2unified 1.16148415 85.5325 99.34464305

1263 4096:32:1:f 16384:32:2:r Anagram L1sepL2unified 1.16195158 85.5275 99.37881377

1264 4096:32:1:f 32768:32:1:f Anagram L1sepL2unified 1.146483889 85.38 97.88679443

1265 4096:32:1:f 32768:32:1:l Anagram L1sepL2unified 1.146483889 85.3825 97.88966064

1266 4096:32:1:f 32768:32:1:r Anagram L1sepL2unified 1.146483889 85.3775 97.88392822

1267 4096:32:1:f 4096:32:8:f Anagram L1sepL2unified 1.194671696 86.43 103.2554747

1268 4096:32:1:f 4096:32:8:l Anagram L1sepL2unified 1.194331747 86.4325 103.2290787

1269 4096:32:1:f 4096:32:8:r Anagram L1sepL2unified 1.168070667 86.4275 100.9534276

1270 4096:32:1:f 8192:32:4:f Anagram L1sepL2unified 1.191739634 85.83 102.2870128

1271 4096:32:1:f 8192:32:4:l Anagram L1sepL2unified 1.191739634 85.8325 102.2899921

1272 4096:32:1:f 8192:32:4:r Anagram L1sepL2unified 1.165308579 85.8275 100.0155221

1273 4096:32:1:l 16384:32:2:f Anagram L1sepL2unified 1.16148415 85.5325 99.34464305

1274 4096:32:1:l 16384:32:2:l Anagram L1sepL2unified 1.16148415 85.535 99.34754676

1275 4096:32:1:l 16384:32:2:r Anagram L1sepL2unified 1.16195158 85.53 99.38171865

1276 4096:32:1:l 32768:32:1:f Anagram L1sepL2unified 1.146483889 85.3825 97.88966064

1277 4096:32:1:l 32768:32:1:l Anagram L1sepL2unified 1.146483889 85.385 97.89252685

1278 4096:32:1:l 32768:32:1:r Anagram L1sepL2unified 1.146483889 85.38 97.88679443

1279 4096:32:1:l 4096:32:8:f Anagram L1sepL2unified 1.194671696 86.4325 103.2584614

1280 4096:32:1:l 4096:32:8:l Anagram L1sepL2unified 1.194331747 86.435 103.2320646

1281 4096:32:1:l 4096:32:8:r Anagram L1sepL2unified 1.168070667 86.43 100.9563477

1282 4096:32:1:l 8192:32:4:f Anagram L1sepL2unified 1.191739634 85.8325 102.2899921

1283 4096:32:1:l 8192:32:4:l Anagram L1sepL2unified 1.191739634 85.835 102.2929715

1284 4096:32:1:l 8192:32:4:r Anagram L1sepL2unified 1.165308579 85.83 100.0184353

1285 4096:32:1:r 16384:32:2:f Anagram L1sepL2unified 1.16148415 85.5275 99.33883563

1286 4096:32:1:r 16384:32:2:l Anagram L1sepL2unified 1.16148415 85.53 99.34173934

1287 4096:32:1:r 16384:32:2:r Anagram L1sepL2unified 1.16195158 85.525 99.37590889

1288 4096:32:1:r 32768:32:1:f Anagram L1sepL2unified 1.146483889 85.3775 97.88392822

1289 4096:32:1:r 32768:32:1:l Anagram L1sepL2unified 1.146483889 85.38 97.88679443

1290 4096:32:1:r 32768:32:1:r Anagram L1sepL2unified 1.146483889 85.375 97.88106201

1291 4096:32:1:r 4096:32:8:f Anagram L1sepL2unified 1.194671696 86.4275 103.252488

1292 4096:32:1:r 4096:32:8:l Anagram L1sepL2unified 1.194331747 86.43 103.2260929

1293 4096:32:1:r 4096:32:8:r Anagram L1sepL2unified 1.167943186 86.425 100.9394898

1294 4096:32:1:r 8192:32:4:f Anagram L1sepL2unified 1.191739634 85.8275 102.2840334

1295 4096:32:1:r 8192:32:4:l Anagram L1sepL2unified 1.191739634 85.83 102.2870128

1296 4096:32:1:r 8192:32:4:r Anagram L1sepL2unified 1.165223592 85.825 100.0053148

1297 512:32:8:f 16384:32:2:f Anagram L1sepL2unified 1.153680004 86.58 99.88561472

1298 512:32:8:f 16384:32:2:l Anagram L1sepL2unified 1.153644532 86.5825 99.88542771

1299 512:32:8:f 16384:32:2:r Anagram L1sepL2unified 1.153892833 86.5775 99.90115671

1300 512:32:8:f 32768:32:1:f Anagram L1sepL2unified 1.138569157 86.43 98.40653221

1301 512:32:8:f 32768:32:1:l Anagram L1sepL2unified 1.138569157 86.4325 98.40937863

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47

1302 512:32:8:f 32768:32:1:r Anagram L1sepL2unified 1.138569157 86.4275 98.40368578

1303 512:32:8:f 4096:32:8:f Anagram L1sepL2unified 1.18684583 87.48 103.8252732

1304 512:32:8:f 4096:32:8:l Anagram L1sepL2unified 1.186491115 87.4825 103.797209

1305 512:32:8:f 4096:32:8:r Anagram L1sepL2unified 1.160774298 87.4775 101.5416337

1306 512:32:8:f 8192:32:4:f Anagram L1sepL2unified 1.183901698 86.88 102.8573795

1307 512:32:8:f 8192:32:4:l Anagram L1sepL2unified 1.183901698 86.8825 102.8603393

1308 512:32:8:f 8192:32:4:r Anagram L1sepL2unified 1.158823367 86.8775 100.6756771

1309 512:32:8:l 16384:32:2:f Anagram L1sepL2unified 1.15367519 86.5825 99.88808211

1310 512:32:8:l 16384:32:2:l Anagram L1sepL2unified 1.15367519 86.585 99.8909663

1311 512:32:8:l 16384:32:2:r Anagram L1sepL2unified 1.153851618 86.58 99.90047309

1312 512:32:8:l 32768:32:1:f Anagram L1sepL2unified 1.138572927 86.4325 98.40970454

1313 512:32:8:l 32768:32:1:l Anagram L1sepL2unified 1.138572927 86.435 98.41255097

1314 512:32:8:l 32768:32:1:r Anagram L1sepL2unified 1.138572927 86.43 98.40685811

1315 512:32:8:l 4096:32:8:f Anagram L1sepL2unified 1.18684371 87.4825 103.8280549

1316 512:32:8:l 4096:32:8:l Anagram L1sepL2unified 1.186526139 87.485 103.8032393

1317 512:32:8:l 4096:32:8:r Anagram L1sepL2unified 1.161085178 87.48 101.5717314

1318 512:32:8:l 8192:32:4:f Anagram L1sepL2unified 1.183915 86.8825 102.861495

1319 512:32:8:l 8192:32:4:l Anagram L1sepL2unified 1.183915 86.885 102.8644548

1320 512:32:8:l 8192:32:4:r Anagram L1sepL2unified 1.158968039 86.88 100.6911432

1321 512:32:8:r 16384:32:2:f Anagram L1sepL2unified 1.153727203 86.5775 99.88681693

1322 512:32:8:r 16384:32:2:l Anagram L1sepL2unified 1.153656156 86.58 99.88354999

1323 512:32:8:r 16384:32:2:r Anagram L1sepL2unified 1.154068997 86.575 99.91352337

1324 512:32:8:r 32768:32:1:f Anagram L1sepL2unified 1.139020449 86.4275 98.44268982

1325 512:32:8:r 32768:32:1:l Anagram L1sepL2unified 1.139020449 86.43 98.44553737

1326 512:32:8:r 32768:32:1:r Anagram L1sepL2unified 1.139113255 86.425 98.44786305

1327 512:32:8:r 4096:32:8:f Anagram L1sepL2unified 1.18690621 87.4775 103.827588

1328 512:32:8:r 4096:32:8:l Anagram L1sepL2unified 1.185627361 87.48 103.7186816

1329 512:32:8:r 4096:32:8:r Anagram L1sepL2unified 1.162618651 87.475 101.7000665

1330 512:32:8:r 8192:32:4:f Anagram L1sepL2unified 1.183957754 86.8775 102.8592898

1331 512:32:8:r 8192:32:4:l Anagram L1sepL2unified 1.183673566 86.88 102.8375594

1332 512:32:8:r 8192:32:4:r Anagram L1sepL2unified 1.159126784 86.875 100.6991394

1333 512:64:4:f 16384:64:1:f Anagram L1sepL2unified 1.069789718 85.83 91.82005147

1334 512:64:4:f 16384:64:1:l Anagram L1sepL2unified 1.069789718 85.8325 91.82272594

1335 512:64:4:f 16384:64:1:r Anagram L1sepL2unified 1.069789718 85.8275 91.81737699

1336 512:64:4:f 2048:64:8:f Anagram L1sepL2unified 1.093837101 86.88 95.03256734

1337 512:64:4:f 2048:64:8:l Anagram L1sepL2unified 1.093658576 86.8825 95.01979119

1338 512:64:4:f 2048:64:8:r Anagram L1sepL2unified 1.080947561 86.8775 93.91002171

1339 512:64:4:f 4096:64:4:f Anagram L1sepL2unified 1.092373192 86.28 94.24995901

1340 512:64:4:f 4096:64:4:l Anagram L1sepL2unified 1.092373192 86.2825 94.25268994

1341 512:64:4:f 4096:64:4:r Anagram L1sepL2unified 1.079947818 86.2775 93.17519787

1342 512:64:4:f 8192:64:2:f Anagram L1sepL2unified 1.077269936 85.98 92.62366907

Page 48: Cache Design for an Alpha Microprocessor

48

1343 512:64:4:f 8192:64:2:l Anagram L1sepL2unified 1.077269936 85.9825 92.62636224

1344 512:64:4:f 8192:64:2:r Anagram L1sepL2unified 1.077519871 85.9775 92.64246474

1345 512:64:4:l 16384:64:1:f Anagram L1sepL2unified 1.069724523 85.8325 91.81713014

1346 512:64:4:l 16384:64:1:l Anagram L1sepL2unified 1.069724523 85.835 91.81980445

1347 512:64:4:l 16384:64:1:r Anagram L1sepL2unified 1.069724523 85.83 91.81445583

1348 512:64:4:l 2048:64:8:f Anagram L1sepL2unified 1.093843814 86.8825 95.03588515

1349 512:64:4:l 2048:64:8:l Anagram L1sepL2unified 1.093666596 86.885 95.02322223

1350 512:64:4:l 2048:64:8:r Anagram L1sepL2unified 1.080818334 86.88 93.90149682

1351 512:64:4:l 4096:64:4:f Anagram L1sepL2unified 1.092372909 86.2825 94.25266554

1352 512:64:4:l 4096:64:4:l Anagram L1sepL2unified 1.092372909 86.285 94.25539647

1353 512:64:4:l 4096:64:4:r Anagram L1sepL2unified 1.080144907 86.28 93.19490261

1354 512:64:4:l 8192:64:2:f Anagram L1sepL2unified 1.077273985 85.9825 92.62671043

1355 512:64:4:l 8192:64:2:l Anagram L1sepL2unified 1.077273985 85.985 92.62940362

1356 512:64:4:l 8192:64:2:r Anagram L1sepL2unified 1.077592977 85.98 92.65144413

1357 512:64:4:r 16384:64:1:f Anagram L1sepL2unified 1.069943118 85.8275 91.83054293

1358 512:64:4:r 16384:64:1:l Anagram L1sepL2unified 1.069943118 85.83 91.83321779

1359 512:64:4:r 16384:64:1:r Anagram L1sepL2unified 1.069971953 85.825 91.83034285

1360 512:64:4:r 2048:64:8:f Anagram L1sepL2unified 1.093887864 86.8775 95.03424292

1361 512:64:4:r 2048:64:8:l Anagram L1sepL2unified 1.093368105 86.88 94.991821

1362 512:64:4:r 2048:64:8:r Anagram L1sepL2unified 1.081500304 86.875 93.95533891

1363 512:64:4:r 4096:64:4:f Anagram L1sepL2unified 1.092418202 86.2775 94.25111138

1364 512:64:4:r 4096:64:4:l Anagram L1sepL2unified 1.092346511 86.28 94.24765694

1365 512:64:4:r 4096:64:4:r Anagram L1sepL2unified 1.0796192 86.275 93.14414651

1366 512:64:4:r 8192:64:2:f Anagram L1sepL2unified 1.077309353 85.9775 92.62436492

1367 512:64:4:r 8192:64:2:l Anagram L1sepL2unified 1.077309353 85.98 92.6270582

1368 512:64:4:r 8192:64:2:r Anagram L1sepL2unified 1.077691558 85.975 92.65453168

1369 1024:32:4:f 16384:32:2:f Anagram L1sepL2unified 1.153676124 85.98 99.19307316

1370 1024:32:4:f 16384:32:2:l Anagram L1sepL2unified 1.153676124 85.9825 99.19595735

1371 1024:32:4:f 16384:32:2:r Anagram L1sepL2unified 1.154066513 85.9775 99.22375366

1372 1024:32:4:f 32768:32:1:f Anagram L1sepL2unified 1.138592901 85.83 97.7254287

1373 1024:32:4:f 32768:32:1:l Anagram L1sepL2unified 1.138592901 85.8325 97.72827519

1374 1024:32:4:f 32768:32:1:r Anagram L1sepL2unified 1.138592901 85.8275 97.72258222

1375 1024:32:4:f 4096:32:8:f Anagram L1sepL2unified 1.186859215 86.88 103.1143286

1376 1024:32:4:f 4096:32:8:l Anagram L1sepL2unified 1.186504316 86.8825 103.0864612

1377 1024:32:4:f 4096:32:8:r Anagram L1sepL2unified 1.160525682 86.8775 100.8235699

1378 1024:32:4:f 8192:32:4:f Anagram L1sepL2unified 1.18391355 86.28 102.1480611

1379 1024:32:4:f 8192:32:4:l Anagram L1sepL2unified 1.18391355 86.2825 102.1510209

1380 1024:32:4:f 8192:32:4:r Anagram L1sepL2unified 1.158964125 86.2775 99.99252727

1381 1024:32:4:l 16384:32:2:f Anagram L1sepL2unified 1.153679838 85.9825 99.19627671

1382 1024:32:4:l 16384:32:2:l Anagram L1sepL2unified 1.153679838 85.985 99.19916091

1383 1024:32:4:l 16384:32:2:r Anagram L1sepL2unified 1.153926982 85.98 99.21464194

Page 49: Cache Design for an Alpha Microprocessor

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1384 1024:32:4:l 32768:32:1:f Anagram L1sepL2unified 1.138568758 85.8325 97.72620294

1385 1024:32:4:l 32768:32:1:l Anagram L1sepL2unified 1.138568758 85.835 97.72904936

1386 1024:32:4:l 32768:32:1:r Anagram L1sepL2unified 1.138568758 85.83 97.72335651

1387 1024:32:4:l 4096:32:8:f Anagram L1sepL2unified 1.186867725 86.8825 103.1180351

1388 1024:32:4:l 4096:32:8:l Anagram L1sepL2unified 1.186514663 86.885 103.0903265

1389 1024:32:4:l 4096:32:8:r Anagram L1sepL2unified 1.16084701 86.88 100.8543882

1390 1024:32:4:l 8192:32:4:f Anagram L1sepL2unified 1.183901999 86.2825 102.1500242

1391 1024:32:4:l 8192:32:4:l Anagram L1sepL2unified 1.183901999 86.285 102.152984

1392 1024:32:4:l 8192:32:4:r Anagram L1sepL2unified 1.15904639 86.28 100.0025226

1393 1024:32:4:r 16384:32:2:f Anagram L1sepL2unified 1.153719327 85.9775 99.19390341

1394 1024:32:4:r 16384:32:2:l Anagram L1sepL2unified 1.153683776 85.98 99.19373105

1395 1024:32:4:r 16384:32:2:r Anagram L1sepL2unified 1.153783646 85.975 99.19654901

1396 1024:32:4:r 32768:32:1:f Anagram L1sepL2unified 1.138930205 85.8275 97.75153219

1397 1024:32:4:r 32768:32:1:l Anagram L1sepL2unified 1.138930205 85.83 97.75437952

1398 1024:32:4:r 32768:32:1:r Anagram L1sepL2unified 1.138900248 85.825 97.74611381

1399 1024:32:4:r 4096:32:8:f Anagram L1sepL2unified 1.186888198 86.8775 103.1138794

1400 1024:32:4:r 4096:32:8:l Anagram L1sepL2unified 1.185857225 86.88 103.0272757

1401 1024:32:4:r 4096:32:8:r Anagram L1sepL2unified 1.162263757 86.875 100.9716639

1402 1024:32:4:r 8192:32:4:f Anagram L1sepL2unified 1.183973034 86.2775 102.1502335

1403 1024:32:4:r 8192:32:4:l Anagram L1sepL2unified 1.18379528 86.28 102.1378568

1404 1024:32:4:r 8192:32:4:r Anagram L1sepL2unified 1.159139629 86.275 100.0047715

1405 1024:64:2:f 16384:64:1:f Anagram L1sepL2unified 1.069827343 85.53 91.50233267

1406 1024:64:2:f 16384:64:1:l Anagram L1sepL2unified 1.069827343 85.5325 91.50500724

1407 1024:64:2:f 16384:64:1:r Anagram L1sepL2unified 1.069827343 85.5275 91.4996581

1408 1024:64:2:f 2048:64:8:f Anagram L1sepL2unified 1.093839127 86.58 94.70459161

1409 1024:64:2:f 2048:64:8:l Anagram L1sepL2unified 1.093677492 86.5825 94.69333144

1410 1024:64:2:f 2048:64:8:r Anagram L1sepL2unified 1.080980161 86.5775 93.58855991

1411 1024:64:2:f 4096:64:4:f Anagram L1sepL2unified 1.092384412 85.98 93.9232117

1412 1024:64:2:f 4096:64:4:l Anagram L1sepL2unified 1.092384412 85.9825 93.92594266

1413 1024:64:2:f 4096:64:4:r Anagram L1sepL2unified 1.079794838 85.9775 92.83806065

1414 1024:64:2:f 8192:64:2:f Anagram L1sepL2unified 1.077280515 85.68 92.3013945

1415 1024:64:2:f 8192:64:2:l Anagram L1sepL2unified 1.077262555 85.6825 92.30254889

1416 1024:64:2:f 8192:64:2:r Anagram L1sepL2unified 1.077549906 85.6775 92.32178211

1417 1024:64:2:l 16384:64:1:f Anagram L1sepL2unified 1.069731477 85.5325 91.49680756

1418 1024:64:2:l 16384:64:1:l Anagram L1sepL2unified 1.069731477 85.535 91.49948188

1419 1024:64:2:l 16384:64:1:r Anagram L1sepL2unified 1.069731477 85.53 91.49413323

1420 1024:64:2:l 2048:64:8:f Anagram L1sepL2unified 1.093836064 86.5825 94.707061

1421 1024:64:2:l 2048:64:8:l Anagram L1sepL2unified 1.093675604 86.585 94.69590221

1422 1024:64:2:l 2048:64:8:r Anagram L1sepL2unified 1.080945815 86.58 93.58828867

1423 1024:64:2:l 4096:64:4:f Anagram L1sepL2unified 1.092374099 85.9825 93.925056

1424 1024:64:2:l 4096:64:4:l Anagram L1sepL2unified 1.092374099 85.985 93.92778693

Page 50: Cache Design for an Alpha Microprocessor

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1425 1024:64:2:l 4096:64:4:r Anagram L1sepL2unified 1.079876085 85.98 92.84774578

1426 1024:64:2:l 8192:64:2:f Anagram L1sepL2unified 1.077273075 85.6825 92.30345023

1427 1024:64:2:l 8192:64:2:l Anagram L1sepL2unified 1.077273075 85.685 92.30614342

1428 1024:64:2:l 8192:64:2:r Anagram L1sepL2unified 1.077629652 85.68 92.33130855

1429 1024:64:2:r 16384:64:1:f Anagram L1sepL2unified 1.070197289 85.5275 91.53129865

1430 1024:64:2:r 16384:64:1:l Anagram L1sepL2unified 1.070197289 85.53 91.53397414

1431 1024:64:2:r 16384:64:1:r Anagram L1sepL2unified 1.070150081 85.525 91.52458571

1432 1024:64:2:r 2048:64:8:f Anagram L1sepL2unified 1.094131877 86.5775 94.72720261

1433 1024:64:2:r 2048:64:8:l Anagram L1sepL2unified 1.093752823 86.58 94.6971194

1434 1024:64:2:r 2048:64:8:r Anagram L1sepL2unified 1.081179186 86.575 93.60308801

1435 1024:64:2:r 4096:64:4:f Anagram L1sepL2unified 1.09265176 85.9775 93.94346666

1436 1024:64:2:r 4096:64:4:l Anagram L1sepL2unified 1.09265176 85.98 93.94619829

1437 1024:64:2:r 4096:64:4:r Anagram L1sepL2unified 1.079821636 85.975 92.83766515

1438 1024:64:2:r 8192:64:2:f Anagram L1sepL2unified 1.077561778 85.6775 92.32279922

1439 1024:64:2:r 8192:64:2:l Anagram L1sepL2unified 1.077561778 85.68 92.32549313

1440 1024:64:2:r 8192:64:2:r Anagram L1sepL2unified 1.077488245 85.675 92.31380541

1441 2048:32:2:f 16384:32:2:f GO L1sepL2unified 1.023477117 85.68 87.69151941

1442 2048:32:2:f 16384:32:2:l GO L1sepL2unified 1.023492662 85.6825 87.69541

1443 2048:32:2:f 16384:32:2:r GO L1sepL2unified 1.024176621 85.6775 87.74889248

1444 2048:32:2:f 32768:32:1:f GO L1sepL2unified 1.029213051 85.53 88.02859222

1445 2048:32:2:f 32768:32:1:l GO L1sepL2unified 1.029213051 85.5325 88.03116526

1446 2048:32:2:f 32768:32:1:r GO L1sepL2unified 1.029213051 85.5275 88.02601919

1447 2048:32:2:f 4096:32:8:f GO L1sepL2unified 1.024596324 86.58 88.70954971

1448 2048:32:2:f 4096:32:8:l GO L1sepL2unified 1.024596324 86.5825 88.71211121

1449 2048:32:2:f 4096:32:8:r GO L1sepL2unified 1.024036721 86.5775 88.65853917

1450 2048:32:2:f 8192:32:4:f GO L1sepL2unified 1.023648107 85.98 88.01326425

1451 2048:32:2:f 8192:32:4:l GO L1sepL2unified 1.023632563 85.9825 88.01448682

1452 2048:32:2:f 8192:32:4:r GO L1sepL2unified 1.023943453 85.9775 88.03609826

1453 2048:32:2:l 16384:32:2:f GO L1sepL2unified 1.022624359 85.6825 87.62101168

1454 2048:32:2:l 16384:32:2:l GO L1sepL2unified 1.022639101 85.685 87.62483137

1455 2048:32:2:l 16384:32:2:r GO L1sepL2unified 1.023317213 85.68 87.67781885

1456 2048:32:2:l 32768:32:1:f GO L1sepL2unified 1.027474337 85.5325 87.88244876

1457 2048:32:2:l 32768:32:1:l GO L1sepL2unified 1.027474337 85.535 87.88501744

1458 2048:32:2:l 32768:32:1:r GO L1sepL2unified 1.027474337 85.53 87.87988007

1459 2048:32:2:l 4096:32:8:f GO L1sepL2unified 1.023759461 86.5825 88.6396535

1460 2048:32:2:l 4096:32:8:l GO L1sepL2unified 1.023759461 86.585 88.6422129

1461 2048:32:2:l 4096:32:8:r GO L1sepL2unified 1.023199281 86.58 88.58859373

1462 2048:32:2:l 8192:32:4:f GO L1sepL2unified 1.022801258 85.9825 87.94300919

1463 2048:32:2:l 8192:32:4:l GO L1sepL2unified 1.022801258 85.985 87.9455662

1464 2048:32:2:l 8192:32:4:r GO L1sepL2unified 1.02309609 85.98 87.9658018

1465 2048:32:2:r 16384:32:2:f GO L1sepL2unified 1.022832805 85.6775 87.63375761

Page 51: Cache Design for an Alpha Microprocessor

51

1466 2048:32:2:r 16384:32:2:l GO L1sepL2unified 1.022847891 85.68 87.63760729

1467 2048:32:2:r 16384:32:2:r GO L1sepL2unified 1.023552495 85.675 87.69285998

1468 2048:32:2:r 32768:32:1:f GO L1sepL2unified 1.027856567 85.5275 87.91000254

1469 2048:32:2:r 32768:32:1:l GO L1sepL2unified 1.027856567 85.53 87.91257219

1470 2048:32:2:r 32768:32:1:r GO L1sepL2unified 1.027836922 85.525 87.90575275

1471 2048:32:2:r 4096:32:8:f GO L1sepL2unified 1.024009542 86.5775 88.6561861

1472 2048:32:2:r 4096:32:8:l GO L1sepL2unified 1.023964283 86.58 88.65482759

1473 2048:32:2:r 4096:32:8:r GO L1sepL2unified 1.023488101 86.575 88.60848236

1474 2048:32:2:r 8192:32:4:f GO L1sepL2unified 1.023044014 85.9775 87.95876669

1475 2048:32:2:r 8192:32:4:l GO L1sepL2unified 1.023044014 85.98 87.9613243

1476 2048:32:2:r 8192:32:4:r GO L1sepL2unified 1.023359037 85.975 87.98329321

1477 2048:64:1:f 16384:64:1:f GO L1sepL2unified 1.042726607 85.38 89.02799769

1478 2048:64:1:f 16384:64:1:l GO L1sepL2unified 1.042726607 85.3825 89.03060451

1479 2048:64:1:f 16384:64:1:r GO L1sepL2unified 1.042726607 85.3775 89.02539088

1480 2048:64:1:f 2048:64:8:f GO L1sepL2unified 1.035367178 86.43 89.48678517

1481 2048:64:1:f 2048:64:8:l GO L1sepL2unified 1.035334323 86.4325 89.48653389

1482 2048:64:1:f 2048:64:8:r GO L1sepL2unified 1.035038632 86.4275 89.45580135

1483 2048:64:1:f 4096:64:4:f GO L1sepL2unified 1.034874359 85.83 88.82326622

1484 2048:64:1:f 4096:64:4:l GO L1sepL2unified 1.034874359 85.8325 88.82585341

1485 2048:64:1:f 4096:64:4:r GO L1sepL2unified 1.035005777 85.8275 88.83195834

1486 2048:64:1:f 8192:64:2:f GO L1sepL2unified 1.034940068 85.53 88.51842402

1487 2048:64:1:f 8192:64:2:l GO L1sepL2unified 1.034940068 85.5325 88.52101137

1488 2048:64:1:f 8192:64:2:r GO L1sepL2unified 1.035268614 85.5275 88.54393638

1489 2048:64:1:l 16384:64:1:f GO L1sepL2unified 1.042726607 85.3825 89.03060451

1490 2048:64:1:l 16384:64:1:l GO L1sepL2unified 1.042726607 85.385 89.03321133

1491 2048:64:1:l 16384:64:1:r GO L1sepL2unified 1.042726607 85.38 89.02799769

1492 2048:64:1:l 2048:64:8:f GO L1sepL2unified 1.035367178 86.4325 89.48937359

1493 2048:64:1:l 2048:64:8:l GO L1sepL2unified 1.035334323 86.435 89.48912222

1494 2048:64:1:l 2048:64:8:r GO L1sepL2unified 1.035038632 86.43 89.45838895

1495 2048:64:1:l 4096:64:4:f GO L1sepL2unified 1.034874359 85.8325 88.82585341

1496 2048:64:1:l 4096:64:4:l GO L1sepL2unified 1.034874359 85.835 88.82844059

1497 2048:64:1:l 4096:64:4:r GO L1sepL2unified 1.035005777 85.83 88.83454586

1498 2048:64:1:l 8192:64:2:f GO L1sepL2unified 1.034940068 85.5325 88.52101137

1499 2048:64:1:l 8192:64:2:l GO L1sepL2unified 1.034940068 85.535 88.52359872

1500 2048:64:1:l 8192:64:2:r GO L1sepL2unified 1.035268614 85.53 88.54652455

1501 2048:64:1:r 16384:64:1:f GO L1sepL2unified 1.042726607 85.3775 89.02539088

1502 2048:64:1:r 16384:64:1:l GO L1sepL2unified 1.042726607 85.38 89.02799769

1503 2048:64:1:r 16384:64:1:r GO L1sepL2unified 1.042726607 85.375 89.02278406

1504 2048:64:1:r 2048:64:8:f GO L1sepL2unified 1.035367178 86.4275 89.48419676

1505 2048:64:1:r 2048:64:8:l GO L1sepL2unified 1.035334323 86.43 89.48394555

1506 2048:64:1:r 2048:64:8:r GO L1sepL2unified 1.035005777 86.425 89.4503743

Page 52: Cache Design for an Alpha Microprocessor

52

1507 2048:64:1:r 4096:64:4:f GO L1sepL2unified 1.034874359 85.8275 88.82067903

1508 2048:64:1:r 4096:64:4:l GO L1sepL2unified 1.034874359 85.83 88.82326622

1509 2048:64:1:r 4096:64:4:r GO L1sepL2unified 1.035005777 85.825 88.82937083

1510 2048:64:1:r 8192:64:2:f GO L1sepL2unified 1.034940068 85.5275 88.51583667

1511 2048:64:1:r 8192:64:2:l GO L1sepL2unified 1.034940068 85.53 88.51842402

1512 2048:64:1:r 8192:64:2:r GO L1sepL2unified 1.035268614 85.525 88.54134821

1513 256:64:8:f 16384:64:1:f GO L1sepL2unified 1.017235712 86.43 87.91968259

1514 256:64:8:f 16384:64:1:l GO L1sepL2unified 1.017235712 86.4325 87.92222568

1515 256:64:8:f 16384:64:1:r GO L1sepL2unified 1.017235712 86.4275 87.9171395

1516 256:64:8:f 2048:64:8:f GO L1sepL2unified 1.014670607 87.48 88.76338474

1517 256:64:8:f 2048:64:8:l GO L1sepL2unified 1.014670607 87.4825 88.76592141

1518 256:64:8:f 2048:64:8:r GO L1sepL2unified 1.01435231 87.4775 88.73300418

1519 256:64:8:f 4096:64:4:f GO L1sepL2unified 1.014183799 86.88 88.11228848

1520 256:64:8:f 4096:64:4:l GO L1sepL2unified 1.014174438 86.8825 88.11401057

1521 256:64:8:f 4096:64:4:r GO L1sepL2unified 1.014333586 86.8775 88.12276615

1522 256:64:8:f 8192:64:2:f GO L1sepL2unified 1.014202523 86.58 87.80965441

1523 256:64:8:f 8192:64:2:l GO L1sepL2unified 1.014211884 86.5825 87.81300047

1524 256:64:8:f 8192:64:2:r GO L1sepL2unified 1.014539544 86.5775 87.83629734

1525 256:64:8:l 16384:64:1:f GO L1sepL2unified 1.015897478 86.4325 87.80655874

1526 256:64:8:l 16384:64:1:l GO L1sepL2unified 1.015897478 86.435 87.80909849

1527 256:64:8:l 16384:64:1:r GO L1sepL2unified 1.015897478 86.43 87.804019

1528 256:64:8:l 2048:64:8:f GO L1sepL2unified 1.013836039 87.4825 88.69291129

1529 256:64:8:l 2048:64:8:l GO L1sepL2unified 1.01382723 87.485 88.69467518

1530 256:64:8:l 2048:64:8:r GO L1sepL2unified 1.013510085 87.48 88.66186225

1531 256:64:8:l 4096:64:4:f GO L1sepL2unified 1.013342703 86.8825 88.04174743

1532 256:64:8:l 4096:64:4:l GO L1sepL2unified 1.013333894 86.885 88.04351536

1533 256:64:8:l 4096:64:4:r GO L1sepL2unified 1.013483656 86.88 88.05146007

1534 256:64:8:l 8192:64:2:f GO L1sepL2unified 1.013351513 86.5825 87.73850737

1535 256:64:8:l 8192:64:2:l GO L1sepL2unified 1.013369132 86.585 87.7425663

1536 256:64:8:l 8192:64:2:r GO L1sepL2unified 1.013686276 86.58 87.76495782

1537 256:64:8:r 16384:64:1:f GO L1sepL2unified 1.015679138 86.4275 87.78260866

1538 256:64:8:r 16384:64:1:l GO L1sepL2unified 1.015679138 86.43 87.78514786

1539 256:64:8:r 16384:64:1:r GO L1sepL2unified 1.015656384 86.425 87.77810301

1540 256:64:8:r 2048:64:8:f GO L1sepL2unified 1.013475936 87.4775 88.65634118

1541 256:64:8:r 2048:64:8:l GO L1sepL2unified 1.013442554 87.48 88.65595463

1542 256:64:8:r 2048:64:8:r GO L1sepL2unified 1.013201954 87.475 88.6298409

1543 256:64:8:r 4096:64:4:f GO L1sepL2unified 1.012983554 86.8775 88.00547869

1544 256:64:8:r 4096:64:4:l GO L1sepL2unified 1.012983554 86.88 88.00801114

1545 256:64:8:r 4096:64:4:r GO L1sepL2unified 1.01314579 86.875 88.01704047

1546 256:64:8:r 8192:64:2:f GO L1sepL2unified 1.012941826 86.5775 87.69797097

1547 256:64:8:r 8192:64:2:l GO L1sepL2unified 1.012950172 86.58 87.70122588

Page 53: Cache Design for an Alpha Microprocessor

53

1548 256:64:8:r 8192:64:2:r GO L1sepL2unified 1.013308607 86.575 87.72719263

1549 4096:32:1:f 16384:32:2:f GO L1sepL2unified 1.041292494 85.53 89.06174705

1550 4096:32:1:f 16384:32:2:l GO L1sepL2unified 1.041292494 85.5325 89.06435028

1551 4096:32:1:f 16384:32:2:r GO L1sepL2unified 1.041958153 85.5275 89.11607595

1552 4096:32:1:f 32768:32:1:f GO L1sepL2unified 1.051382481 85.38 89.76703623

1553 4096:32:1:f 32768:32:1:l GO L1sepL2unified 1.051382481 85.3825 89.76966468

1554 4096:32:1:f 32768:32:1:r GO L1sepL2unified 1.051382481 85.3775 89.76440777

1555 4096:32:1:f 4096:32:8:f GO L1sepL2unified 1.042378569 86.43 90.09277975

1556 4096:32:1:f 4096:32:8:l GO L1sepL2unified 1.042378569 86.4325 90.0953857

1557 4096:32:1:f 4096:32:8:r GO L1sepL2unified 1.04178298 86.4275 90.03869849

1558 4096:32:1:f 8192:32:4:f GO L1sepL2unified 1.041432633 85.83 89.3861629

1559 4096:32:1:f 8192:32:4:l GO L1sepL2unified 1.041432633 85.8325 89.38876648

1560 4096:32:1:f 8192:32:4:r GO L1sepL2unified 1.041712911 85.8275 89.40761483

1561 4096:32:1:l 16384:32:2:f GO L1sepL2unified 1.041292494 85.5325 89.06435028

1562 4096:32:1:l 16384:32:2:l GO L1sepL2unified 1.041292494 85.535 89.06695351

1563 4096:32:1:l 16384:32:2:r GO L1sepL2unified 1.041958153 85.53 89.11868085

1564 4096:32:1:l 32768:32:1:f GO L1sepL2unified 1.051382481 85.3825 89.76966468

1565 4096:32:1:l 32768:32:1:l GO L1sepL2unified 1.051382481 85.385 89.77229314

1566 4096:32:1:l 32768:32:1:r GO L1sepL2unified 1.051382481 85.38 89.76703623

1567 4096:32:1:l 4096:32:8:f GO L1sepL2unified 1.042378569 86.4325 90.0953857

1568 4096:32:1:l 4096:32:8:l GO L1sepL2unified 1.042378569 86.435 90.09799164

1569 4096:32:1:l 4096:32:8:r GO L1sepL2unified 1.04178298 86.43 90.04130295

1570 4096:32:1:l 8192:32:4:f GO L1sepL2unified 1.041432633 85.8325 89.38876648

1571 4096:32:1:l 8192:32:4:l GO L1sepL2unified 1.041432633 85.835 89.39137006

1572 4096:32:1:l 8192:32:4:r GO L1sepL2unified 1.041712911 85.83 89.41021911

1573 4096:32:1:r 16384:32:2:f GO L1sepL2unified 1.041292494 85.5275 89.05914382

1574 4096:32:1:r 16384:32:2:l GO L1sepL2unified 1.041292494 85.53 89.06174705

1575 4096:32:1:r 16384:32:2:r GO L1sepL2unified 1.041958153 85.525 89.11347106

1576 4096:32:1:r 32768:32:1:f GO L1sepL2unified 1.051382481 85.3775 89.76440777

1577 4096:32:1:r 32768:32:1:l GO L1sepL2unified 1.051382481 85.38 89.76703623

1578 4096:32:1:r 32768:32:1:r GO L1sepL2unified 1.051382481 85.375 89.76177932

1579 4096:32:1:r 4096:32:8:f GO L1sepL2unified 1.042378569 86.4275 90.0901738

1580 4096:32:1:r 4096:32:8:l GO L1sepL2unified 1.042378569 86.43 90.09277975

1581 4096:32:1:r 4096:32:8:r GO L1sepL2unified 1.041818015 86.425 90.03912191

1582 4096:32:1:r 8192:32:4:f GO L1sepL2unified 1.041432633 85.8275 89.38355932

1583 4096:32:1:r 8192:32:4:l GO L1sepL2unified 1.041432633 85.83 89.3861629

1584 4096:32:1:r 8192:32:4:r GO L1sepL2unified 1.041747945 85.825 89.4080174

1585 512:32:8:f 16384:32:2:f GO L1sepL2unified 1.025310151 86.58 88.77135289

1586 512:32:8:f 16384:32:2:l GO L1sepL2unified 1.025326925 86.5825 88.77536849

1587 512:32:8:f 16384:32:2:r GO L1sepL2unified 1.026031427 86.5775 88.83123586

1588 512:32:8:f 32768:32:1:f GO L1sepL2unified 1.029755222 86.43 89.00174382

Page 54: Cache Design for an Alpha Microprocessor

54

1589 512:32:8:f 32768:32:1:l GO L1sepL2unified 1.029755222 86.4325 89.00431821

1590 512:32:8:f 32768:32:1:r GO L1sepL2unified 1.029755222 86.4275 88.99916943

1591 512:32:8:f 4096:32:8:f GO L1sepL2unified 1.026534642 87.48 89.80125051

1592 512:32:8:f 4096:32:8:l GO L1sepL2unified 1.026517869 87.4825 89.80234943

1593 512:32:8:f 4096:32:8:r GO L1sepL2unified 1.025964331 87.4775 89.7487948

1594 512:32:8:f 8192:32:4:f GO L1sepL2unified 1.025578533 86.88 89.10226293

1595 512:32:8:f 8192:32:4:l GO L1sepL2unified 1.025561759 86.8825 89.10336953

1596 512:32:8:f 8192:32:4:r GO L1sepL2unified 1.025880462 86.8775 89.12592985

1597 512:32:8:l 16384:32:2:f GO L1sepL2unified 1.023828426 86.5825 88.6456247

1598 512:32:8:l 16384:32:2:l GO L1sepL2unified 1.023844112 86.585 88.64954244

1599 512:32:8:l 16384:32:2:r GO L1sepL2unified 1.024534296 86.58 88.70417932

1600 512:32:8:l 32768:32:1:f GO L1sepL2unified 1.027357774 86.4325 88.7971008

1601 512:32:8:l 32768:32:1:l GO L1sepL2unified 1.027357774 86.435 88.7996692

1602 512:32:8:l 32768:32:1:r GO L1sepL2unified 1.027357774 86.43 88.79453241

1603 512:32:8:l 4096:32:8:f GO L1sepL2unified 1.025083305 87.4825 89.67685026

1604 512:32:8:l 4096:32:8:l GO L1sepL2unified 1.025083305 87.485 89.67941297

1605 512:32:8:l 4096:32:8:r GO L1sepL2unified 1.024534296 87.48 89.62626019

1606 512:32:8:l 8192:32:4:f GO L1sepL2unified 1.02412646 86.8825 88.97866715

1607 512:32:8:l 8192:32:4:l GO L1sepL2unified 1.024110774 86.885 88.97986459

1608 512:32:8:l 8192:32:4:r GO L1sepL2unified 1.02444018 86.88 89.00336281

1609 512:32:8:r 16384:32:2:f GO L1sepL2unified 1.022632199 86.5775 88.53693922

1610 512:32:8:r 16384:32:2:l GO L1sepL2unified 1.022632199 86.58 88.5394958

1611 512:32:8:r 16384:32:2:r GO L1sepL2unified 1.023384364 86.575 88.59950132

1612 512:32:8:r 32768:32:1:f GO L1sepL2unified 1.025944318 86.4275 88.66980257

1613 512:32:8:r 32768:32:1:l GO L1sepL2unified 1.025944318 86.43 88.67236743

1614 512:32:8:r 32768:32:1:r GO L1sepL2unified 1.025928068 86.425 88.66583324

1615 512:32:8:r 4096:32:8:f GO L1sepL2unified 1.023911558 87.4775 89.56922336

1616 512:32:8:r 4096:32:8:l GO L1sepL2unified 1.023826268 87.48 89.56432191

1617 512:32:8:r 4096:32:8:r GO L1sepL2unified 1.023443954 87.475 89.52575992

1618 512:32:8:r 8192:32:4:f GO L1sepL2unified 1.022944931 86.8775 88.87089828

1619 512:32:8:r 8192:32:4:l GO L1sepL2unified 1.022944931 86.88 88.87345564

1620 512:32:8:r 8192:32:4:r GO L1sepL2unified 1.023296367 86.875 88.89887189

1621 512:64:4:f 16384:64:1:f GO L1sepL2unified 1.017379826 85.83 87.32171045

1622 512:64:4:f 16384:64:1:l GO L1sepL2unified 1.017379826 85.8325 87.3242539

1623 512:64:4:f 16384:64:1:r GO L1sepL2unified 1.017379826 85.8275 87.319167

1624 512:64:4:f 2048:64:8:f GO L1sepL2unified 1.014303586 86.88 88.12269556

1625 512:64:4:f 2048:64:8:l GO L1sepL2unified 1.014303586 86.8825 88.12523132

1626 512:64:4:f 2048:64:8:r GO L1sepL2unified 1.013994086 86.8775 88.09327123

1627 512:64:4:f 4096:64:4:f GO L1sepL2unified 1.01381589 86.28 87.47203495

1628 512:64:4:f 4096:64:4:l GO L1sepL2unified 1.01381589 86.2825 87.47456949

1629 512:64:4:f 4096:64:4:r GO L1sepL2unified 1.01396595 86.2775 87.48244725

Page 55: Cache Design for an Alpha Microprocessor

55

1630 512:64:4:f 8192:64:2:f GO L1sepL2unified 1.013881541 85.98 87.17353489

1631 512:64:4:f 8192:64:2:l GO L1sepL2unified 1.013900299 85.9825 87.17768242

1632 512:64:4:f 8192:64:2:r GO L1sepL2unified 1.014209798 85.9775 87.19922293

1633 512:64:4:l 16384:64:1:f GO L1sepL2unified 1.015874098 85.8325 87.19501354

1634 512:64:4:l 16384:64:1:l GO L1sepL2unified 1.015874098 85.835 87.19755323

1635 512:64:4:l 16384:64:1:r GO L1sepL2unified 1.015874098 85.83 87.19247386

1636 512:64:4:l 2048:64:8:f GO L1sepL2unified 1.013466487 86.8825 88.05250206

1637 512:64:4:l 2048:64:8:l GO L1sepL2unified 1.013466487 86.885 88.05503573

1638 512:64:4:l 2048:64:8:r GO L1sepL2unified 1.013135004 86.88 88.02116917

1639 512:64:4:l 4096:64:4:f GO L1sepL2unified 1.012977986 86.2825 87.40227309

1640 512:64:4:l 4096:64:4:l GO L1sepL2unified 1.012969263 86.285 87.40405285

1641 512:64:4:l 4096:64:4:r GO L1sepL2unified 1.013108835 86.28 87.41103025

1642 512:64:4:l 8192:64:2:f GO L1sepL2unified 1.013030326 85.9825 87.10287997

1643 512:64:4:l 8192:64:2:l GO L1sepL2unified 1.013047772 85.985 87.10691268

1644 512:64:4:l 8192:64:2:r GO L1sepL2unified 1.013353085 85.98 87.12809825

1645 512:64:4:r 16384:64:1:f GO L1sepL2unified 1.015917804 85.8275 87.19368529

1646 512:64:4:r 16384:64:1:l GO L1sepL2unified 1.015917804 85.83 87.19622508

1647 512:64:4:r 16384:64:1:r GO L1sepL2unified 1.015904665 85.825 87.19001788

1648 512:64:4:r 2048:64:8:f GO L1sepL2unified 1.013478806 86.8775 88.04850494

1649 512:64:4:r 2048:64:8:l GO L1sepL2unified 1.013453222 86.88 88.04881591

1650 512:64:4:r 2048:64:8:r GO L1sepL2unified 1.01318939 86.875 88.02082823

1651 512:64:4:r 4096:64:4:f GO L1sepL2unified 1.012984184 86.2775 87.39774291

1652 512:64:4:r 4096:64:4:l GO L1sepL2unified 1.012984184 86.28 87.40027537

1653 512:64:4:r 4096:64:4:r GO L1sepL2unified 1.013135807 86.275 87.40829174

1654 512:64:4:r 8192:64:2:f GO L1sepL2unified 1.012975656 85.9775 87.09311444

1655 512:64:4:r 8192:64:2:l GO L1sepL2unified 1.012984184 85.98 87.09638011

1656 512:64:4:r 8192:64:2:r GO L1sepL2unified 1.01332982 85.975 87.12103129

1657 1024:32:4:f 16384:32:2:f GO L1sepL2unified 1.024794388 85.98 88.11182147

1658 1024:32:4:f 16384:32:2:l GO L1sepL2unified 1.024810587 85.9825 88.1157763

1659 1024:32:4:f 16384:32:2:r GO L1sepL2unified 1.025490953 85.9775 88.16914838

1660 1024:32:4:f 32768:32:1:f GO L1sepL2unified 1.02929776 85.83 88.3446267

1661 1024:32:4:f 32768:32:1:l GO L1sepL2unified 1.02929776 85.8325 88.34719995

1662 1024:32:4:f 32768:32:1:r GO L1sepL2unified 1.02929776 85.8275 88.34205346

1663 1024:32:4:f 4096:32:8:f GO L1sepL2unified 1.02592833 86.88 89.13265335

1664 1024:32:4:f 4096:32:8:l GO L1sepL2unified 1.02592833 86.8825 89.13521817

1665 1024:32:4:f 4096:32:8:r GO L1sepL2unified 1.025377558 86.8775 89.08223882

1666 1024:32:4:f 8192:32:4:f GO L1sepL2unified 1.024972579 86.28 88.4346341

1667 1024:32:4:f 8192:32:4:l GO L1sepL2unified 1.024972579 86.2825 88.43719654

1668 1024:32:4:f 8192:32:4:r GO L1sepL2unified 1.025280363 86.2775 88.45862654

1669 1024:32:4:l 16384:32:2:f GO L1sepL2unified 1.023344539 85.9825 87.9897218

1670 1024:32:4:l 16384:32:2:l GO L1sepL2unified 1.023359629 85.985 87.99357769

Page 56: Cache Design for an Alpha Microprocessor

56

1671 1024:32:4:l 16384:32:2:r GO L1sepL2unified 1.024023599 85.98 88.04554901

1672 1024:32:4:l 32768:32:1:f GO L1sepL2unified 1.02687565 85.8325 88.13930427

1673 1024:32:4:l 32768:32:1:l GO L1sepL2unified 1.02687565 85.835 88.14187146

1674 1024:32:4:l 32768:32:1:r GO L1sepL2unified 1.02687565 85.83 88.13673708

1675 1024:32:4:l 4096:32:8:f GO L1sepL2unified 1.024491395 86.8825 89.01037367

1676 1024:32:4:l 4096:32:8:l GO L1sepL2unified 1.024476305 86.885 89.01162378

1677 1024:32:4:l 4096:32:8:r GO L1sepL2unified 1.023917967 86.88 88.95799298

1678 1024:32:4:l 8192:32:4:f GO L1sepL2unified 1.023525621 86.2825 88.31234942

1679 1024:32:4:l 8192:32:4:l GO L1sepL2unified 1.023525621 86.285 88.31490824

1680 1024:32:4:l 8192:32:4:r GO L1sepL2unified 1.023827426 86.28 88.33583029

1681 1024:32:4:r 16384:32:2:f GO L1sepL2unified 1.022094021 85.9775 87.8770887

1682 1024:32:4:r 16384:32:2:l GO L1sepL2unified 1.022094021 85.98 87.87964394

1683 1024:32:4:r 16384:32:2:r GO L1sepL2unified 1.022809533 85.975 87.9360496

1684 1024:32:4:r 32768:32:1:f GO L1sepL2unified 1.025603282 85.8275 88.02496571

1685 1024:32:4:r 32768:32:1:l GO L1sepL2unified 1.025603282 85.83 88.02752972

1686 1024:32:4:r 32768:32:1:r GO L1sepL2unified 1.025545867 85.825 88.01747403

1687 1024:32:4:r 4096:32:8:f GO L1sepL2unified 1.023302127 86.8775 88.90193058

1688 1024:32:4:r 4096:32:8:l GO L1sepL2unified 1.023244599 86.88 88.89949072

1689 1024:32:4:r 4096:32:8:r GO L1sepL2unified 1.022804541 86.875 88.85614454

1690 1024:32:4:r 8192:32:4:f GO L1sepL2unified 1.022338519 86.2775 88.20481156

1691 1024:32:4:r 8192:32:4:l GO L1sepL2unified 1.022338519 86.28 88.2073674

1692 1024:32:4:r 8192:32:4:r GO L1sepL2unified 1.022697359 86.275 88.23321469

1693 1024:64:2:f 16384:64:1:f GO L1sepL2unified 1.018637107 85.53 87.12403175

1694 1024:64:2:f 16384:64:1:l GO L1sepL2unified 1.018637107 85.5325 87.12657835

1695 1024:64:2:f 16384:64:1:r GO L1sepL2unified 1.018637107 85.5275 87.12148516

1696 1024:64:2:f 2048:64:8:f GO L1sepL2unified 1.014173715 86.58 87.80716023

1697 1024:64:2:f 2048:64:8:l GO L1sepL2unified 1.014173715 86.5825 87.80969566

1698 1024:64:2:f 2048:64:8:r GO L1sepL2unified 1.013836855 86.5775 87.77546032

1699 1024:64:2:f 4096:64:4:f GO L1sepL2unified 1.01368714 85.98 87.15682026

1700 1024:64:2:f 4096:64:4:l GO L1sepL2unified 1.013677782 85.9825 87.15854992

1701 1024:64:2:f 4096:64:4:r GO L1sepL2unified 1.013818141 85.9775 87.16554918

1702 1024:64:2:f 8192:64:2:f GO L1sepL2unified 1.01375264 85.68 86.8583262

1703 1024:64:2:f 8192:64:2:l GO L1sepL2unified 1.013771355 85.6825 86.86246408

1704 1024:64:2:f 8192:64:2:r GO L1sepL2unified 1.014070785 85.6775 86.88304972

1705 1024:64:2:l 16384:64:1:f GO L1sepL2unified 1.017756479 85.5325 87.05125607

1706 1024:64:2:l 16384:64:1:l GO L1sepL2unified 1.017756479 85.535 87.05380046

1707 1024:64:2:l 16384:64:1:r GO L1sepL2unified 1.017756479 85.53 87.04871168

1708 1024:64:2:l 2048:64:8:f GO L1sepL2unified 1.013937454 86.5825 87.7892396

1709 1024:64:2:l 2048:64:8:l GO L1sepL2unified 1.013937454 86.585 87.79177445

1710 1024:64:2:l 2048:64:8:r GO L1sepL2unified 1.013601521 86.58 87.7576197

1711 1024:64:2:l 4096:64:4:f GO L1sepL2unified 1.013451235 85.9825 87.13907085

Page 57: Cache Design for an Alpha Microprocessor

57

1712 1024:64:2:l 4096:64:4:l GO L1sepL2unified 1.013442395 85.985 87.14084434

1713 1024:64:2:l 4096:64:4:r GO L1sepL2unified 1.01358384 85.98 87.1479386

1714 1024:64:2:l 8192:64:2:f GO L1sepL2unified 1.013504277 85.6825 86.83958025

1715 1024:64:2:l 8192:64:2:l GO L1sepL2unified 1.013521958 85.685 86.84362898

1716 1024:64:2:l 8192:64:2:r GO L1sepL2unified 1.01382253 85.68 86.86431433

1717 1024:64:2:r 16384:64:1:f GO L1sepL2unified 1.018069028 85.5275 87.07289881

1718 1024:64:2:r 16384:64:1:l GO L1sepL2unified 1.018069028 85.53 87.07544398

1719 1024:64:2:r 16384:64:1:r GO L1sepL2unified 1.018024355 85.525 87.06653295

1720 1024:64:2:r 2048:64:8:f GO L1sepL2unified 1.01417855 86.5775 87.80504342

1721 1024:64:2:r 2048:64:8:l GO L1sepL2unified 1.014160155 86.58 87.80598626

1722 1024:64:2:r 2048:64:8:r GO L1sepL2unified 1.013867569 86.575 87.77558475

1723 1024:64:2:r 4096:64:4:f GO L1sepL2unified 1.013691091 85.9775 87.15462575

1724 1024:64:2:r 4096:64:4:l GO L1sepL2unified 1.013681893 85.98 87.15636919

1725 1024:64:2:r 4096:64:4:r GO L1sepL2unified 1.013828043 85.975 87.16386602

1726 1024:64:2:r 8192:64:2:f GO L1sepL2unified 1.013718683 85.6775 86.85288244

1727 1024:64:2:r 8192:64:2:l GO L1sepL2unified 1.01372788 85.68 86.85620477

1728 1024:64:2:r 8192:64:2:r GO L1sepL2unified 1.014056427 85.675 86.87928436

1729 2048:32:2:f 16384:32:1:f GCC L1sepL2sep 1.177477232 85.68 100.8862492

1730 2048:32:2:f 16384:32:1:l GCC L1sepL2sep 1.177477232 85.6825 100.8891929

1731 2048:32:2:f 16384:32:1:r GCC L1sepL2sep 1.177477232 85.6775 100.8833055

1732 2048:32:2:f 2048:32:8:f GCC L1sepL2sep 1.116561694 86.73 96.8393957

1733 2048:32:2:f 2048:32:8:l GCC L1sepL2sep 1.110251307 86.7325 96.29487146

1734 2048:32:2:f 2048:32:8:r GCC L1sepL2sep 1.121346176 86.7275 97.2515505

1735 2048:32:2:f 4096:32:4:f GCC L1sepL2sep 1.126677255 86.13 97.04071201

1736 2048:32:2:f 4096:32:4:l GCC L1sepL2sep 1.121307556 86.1325 96.58102305

1737 2048:32:2:f 4096:32:4:r GCC L1sepL2sep 1.128373165 86.1275 97.18395973

1738 2048:32:2:f 8192:32:2:f GCC L1sepL2sep 1.140257525 85.83 97.8683034

1739 2048:32:2:f 8192:32:2:l GCC L1sepL2sep 1.136396413 85.8325 97.53974513

1740 2048:32:2:f 8192:32:2:r GCC L1sepL2sep 1.141228799 85.8275 97.94881473

1741 2048:32:2:l 16384:32:1:f GCC L1sepL2sep 1.167015194 85.6825 99.99277939

1742 2048:32:2:l 16384:32:1:l GCC L1sepL2sep 1.167015194 85.685 99.99569693

1743 2048:32:2:l 16384:32:1:r GCC L1sepL2sep 1.167015194 85.68 99.98986185

1744 2048:32:2:l 2048:32:8:f GCC L1sepL2sep 1.112083276 86.7325 96.45376278

1745 2048:32:2:l 2048:32:8:l GCC L1sepL2sep 1.105939307 86.735 95.92364583

1746 2048:32:2:l 2048:32:8:r GCC L1sepL2sep 1.116824352 86.73 96.86217603

1747 2048:32:2:l 4096:32:4:f GCC L1sepL2sep 1.122112737 86.1325 96.65037536

1748 2048:32:2:l 4096:32:4:l GCC L1sepL2sep 1.117125929 86.135 96.22364187

1749 2048:32:2:l 4096:32:4:r GCC L1sepL2sep 1.123639038 86.13 96.77903037

1750 2048:32:2:l 8192:32:2:f GCC L1sepL2sep 1.135447128 85.8325 97.45826564

1751 2048:32:2:l 8192:32:2:l GCC L1sepL2sep 1.132189013 85.835 97.18144395

1752 2048:32:2:l 8192:32:2:r GCC L1sepL2sep 1.136038683 85.83 97.5062002

Page 58: Cache Design for an Alpha Microprocessor

58

1753 2048:32:2:r 16384:32:1:f GCC L1sepL2sep 1.17585685 85.6775 100.7444753

1754 2048:32:2:r 16384:32:1:l GCC L1sepL2sep 1.17585685 85.68 100.7474149

1755 2048:32:2:r 16384:32:1:r GCC L1sepL2sep 1.17591614 85.675 100.7466153

1756 2048:32:2:r 2048:32:8:f GCC L1sepL2sep 1.118176574 86.7275 96.97665878

1757 2048:32:2:r 2048:32:8:l GCC L1sepL2sep 1.111916183 86.73 96.43649051

1758 2048:32:2:r 2048:32:8:r GCC L1sepL2sep 1.123523022 86.725 97.43753406

1759 2048:32:2:r 4096:32:4:f GCC L1sepL2sep 1.128316194 86.1275 97.17905297

1760 2048:32:2:r 4096:32:4:l GCC L1sepL2sep 1.123053026 86.13 96.72855714

1761 2048:32:2:r 4096:32:4:r GCC L1sepL2sep 1.130116544 86.125 97.33128733

1762 2048:32:2:r 8192:32:2:f GCC L1sepL2sep 1.141733852 85.8275 97.99216221

1763 2048:32:2:r 8192:32:2:l GCC L1sepL2sep 1.137980167 85.83 97.67283774

1764 2048:32:2:r 8192:32:2:r GCC L1sepL2sep 1.142658541 85.825 98.0686693

1765 2048:64:1:f 1024:64:8:f GCC L1sepL2sep 1.114977456 86.58 96.53474817

1766 2048:64:1:f 1024:64:8:l GCC L1sepL2sep 1.11033498 86.5825 96.13557839

1767 2048:64:1:f 1024:64:8:r GCC L1sepL2sep 1.116638014 86.5775 96.67572767

1768 2048:64:1:f 2048:64:4:f GCC L1sepL2sep 1.121101573 85.98 96.39231327

1769 2048:64:1:f 2048:64:4:l GCC L1sepL2sep 1.117045436 85.9825 96.04635924

1770 2048:64:1:f 2048:64:4:r GCC L1sepL2sep 1.121327694 85.9775 96.40895179

1771 2048:64:1:f 4096:64:2:f GCC L1sepL2sep 1.129646915 85.68 96.78814764

1772 2048:64:1:f 4096:64:2:l GCC L1sepL2sep 1.126568513 85.6825 96.52720666

1773 2048:64:1:f 4096:64:2:r GCC L1sepL2sep 1.130562865 85.6775 96.86379983

1774 2048:64:1:f 8192:64:1:f GCC L1sepL2sep 1.185486108 85.53 101.3946269

1775 2048:64:1:f 8192:64:1:l GCC L1sepL2sep 1.185486108 85.5325 101.3975906

1776 2048:64:1:f 8192:64:1:r GCC L1sepL2sep 1.185486108 85.5275 101.3916631

1777 2048:64:1:l 1024:64:8:f GCC L1sepL2sep 1.114977456 86.5825 96.53753562

1778 2048:64:1:l 1024:64:8:l GCC L1sepL2sep 1.11033498 86.585 96.13835423

1779 2048:64:1:l 1024:64:8:r GCC L1sepL2sep 1.116638014 86.58 96.67851927

1780 2048:64:1:l 2048:64:4:f GCC L1sepL2sep 1.121101573 85.9825 96.39511602

1781 2048:64:1:l 2048:64:4:l GCC L1sepL2sep 1.117045436 85.985 96.04915186

1782 2048:64:1:l 2048:64:4:r GCC L1sepL2sep 1.121327694 85.98 96.41175511

1783 2048:64:1:l 4096:64:2:f GCC L1sepL2sep 1.129646915 85.6825 96.79097176

1784 2048:64:1:l 4096:64:2:l GCC L1sepL2sep 1.126568513 85.685 96.53002308

1785 2048:64:1:l 4096:64:2:r GCC L1sepL2sep 1.130562865 85.68 96.86662623

1786 2048:64:1:l 8192:64:1:f GCC L1sepL2sep 1.185486108 85.5325 101.3975906

1787 2048:64:1:l 8192:64:1:l GCC L1sepL2sep 1.185486108 85.535 101.4005543

1788 2048:64:1:l 8192:64:1:r GCC L1sepL2sep 1.185486108 85.53 101.3946269

1789 2048:64:1:r 1024:64:8:f GCC L1sepL2sep 1.114977456 86.5775 96.53196073

1790 2048:64:1:r 1024:64:8:l GCC L1sepL2sep 1.11033498 86.58 96.13280256

1791 2048:64:1:r 1024:64:8:r GCC L1sepL2sep 1.116677204 86.575 96.67632894

1792 2048:64:1:r 2048:64:4:f GCC L1sepL2sep 1.121101573 85.9775 96.38951052

1793 2048:64:1:r 2048:64:4:l GCC L1sepL2sep 1.117045436 85.98 96.04356663

Page 59: Cache Design for an Alpha Microprocessor

59

1794 2048:64:1:r 2048:64:4:r GCC L1sepL2sep 1.121288001 85.975 96.40273588

1795 2048:64:1:r 4096:64:2:f GCC L1sepL2sep 1.129646915 85.6775 96.78532352

1796 2048:64:1:r 4096:64:2:l GCC L1sepL2sep 1.126568513 85.68 96.52439023

1797 2048:64:1:r 4096:64:2:r GCC L1sepL2sep 1.130523675 85.675 96.85761583

1798 2048:64:1:r 8192:64:1:f GCC L1sepL2sep 1.185486108 85.5275 101.3916631

1799 2048:64:1:r 8192:64:1:l GCC L1sepL2sep 1.185486108 85.53 101.3946269

1800 2048:64:1:r 8192:64:1:r GCC L1sepL2sep 1.185486108 85.525 101.3886994

1801 256:64:8:f 1024:64:8:f GCC L1sepL2sep 1.071514909 87.63 93.89685145

1802 256:64:8:f 1024:64:8:l GCC L1sepL2sep 1.067072841 87.6325 93.51026077

1803 256:64:8:f 1024:64:8:r GCC L1sepL2sep 1.073582974 87.6275 94.07539203

1804 256:64:8:f 2048:64:4:f GCC L1sepL2sep 1.077663715 87.03 93.78907316

1805 256:64:8:f 2048:64:4:l GCC L1sepL2sep 1.073810968 87.0325 93.45645304

1806 256:64:8:f 2048:64:4:r GCC L1sepL2sep 1.078002632 87.0275 93.81587404

1807 256:64:8:f 4096:64:2:f GCC L1sepL2sep 1.086063392 86.73 94.19427799

1808 256:64:8:f 4096:64:2:l GCC L1sepL2sep 1.083590035 86.7325 93.98247272

1809 256:64:8:f 4096:64:2:r GCC L1sepL2sep 1.086353828 86.7275 94.21675158

1810 256:64:8:f 8192:64:1:f GCC L1sepL2sep 1.107534829 86.58 95.89036547

1811 256:64:8:f 8192:64:1:l GCC L1sepL2sep 1.107534829 86.5825 95.89313431

1812 256:64:8:f 8192:64:1:r GCC L1sepL2sep 1.107534829 86.5775 95.88759663

1813 256:64:8:l 1024:64:8:f GCC L1sepL2sep 1.065967263 87.6325 93.41337614

1814 256:64:8:l 1024:64:8:l GCC L1sepL2sep 1.061853108 87.635 93.05549714

1815 256:64:8:l 1024:64:8:r GCC L1sepL2sep 1.067751119 87.63 93.56703056

1816 256:64:8:l 2048:64:4:f GCC L1sepL2sep 1.071926281 87.0325 93.29242403

1817 256:64:8:l 2048:64:4:l GCC L1sepL2sep 1.068698193 87.035 93.01414727

1818 256:64:8:l 2048:64:4:r GCC L1sepL2sep 1.072148088 87.03 93.30904813

1819 256:64:8:l 4096:64:2:f GCC L1sepL2sep 1.079813904 86.7325 93.6549594

1820 256:64:8:l 4096:64:2:l GCC L1sepL2sep 1.077866038 86.735 93.4887108

1821 256:64:8:l 4096:64:2:r GCC L1sepL2sep 1.079738588 86.73 93.64572776

1822 256:64:8:l 8192:64:1:f GCC L1sepL2sep 1.096201277 86.5825 94.91184706

1823 256:64:8:l 8192:64:1:l GCC L1sepL2sep 1.096201277 86.585 94.91458757

1824 256:64:8:l 8192:64:1:r GCC L1sepL2sep 1.096201277 86.58 94.90910656

1825 256:64:8:r 1024:64:8:f GCC L1sepL2sep 1.073744114 87.6275 94.08951236

1826 256:64:8:r 1024:64:8:l GCC L1sepL2sep 1.069379585 87.63 93.70973301

1827 256:64:8:r 1024:64:8:r GCC L1sepL2sep 1.075964677 87.625 94.28140481

1828 256:64:8:r 2048:64:4:f GCC L1sepL2sep 1.079808405 87.0275 93.97302598

1829 256:64:8:r 2048:64:4:l GCC L1sepL2sep 1.076147365 87.03 93.65710517

1830 256:64:8:r 2048:64:4:r GCC L1sepL2sep 1.080168204 87.025 94.001638

1831 256:64:8:r 4096:64:2:f GCC L1sepL2sep 1.088005494 86.7275 94.35999644

1832 256:64:8:r 4096:64:2:l GCC L1sepL2sep 1.085569329 86.73 94.15142791

1833 256:64:8:r 4096:64:2:r GCC L1sepL2sep 1.088339837 86.725 94.38627232

1834 256:64:8:r 8192:64:1:f GCC L1sepL2sep 1.106805295 86.5775 95.8244354

Page 60: Cache Design for an Alpha Microprocessor

60

1835 256:64:8:r 8192:64:1:l GCC L1sepL2sep 1.106805295 86.58 95.82720241

1836 256:64:8:r 8192:64:1:r GCC L1sepL2sep 1.106841797 86.575 95.82482861

1837 4096:32:1:f 16384:32:1:f GCC L1sepL2sep 1.251688775 85.53 107.0569409

1838 4096:32:1:f 16384:32:1:l GCC L1sepL2sep 1.251688775 85.5325 107.0600701

1839 4096:32:1:f 16384:32:1:r GCC L1sepL2sep 1.251688775 85.5275 107.0538117

1840 4096:32:1:f 2048:32:8:f GCC L1sepL2sep 1.156352228 86.58 100.1169759

1841 4096:32:1:f 2048:32:8:l GCC L1sepL2sep 1.149890567 86.5825 99.56040003

1842 4096:32:1:f 2048:32:8:r GCC L1sepL2sep 1.160873608 86.5775 100.5055348

1843 4096:32:1:f 4096:32:4:f GCC L1sepL2sep 1.166563604 85.98 100.3011387

1844 4096:32:1:f 4096:32:4:l GCC L1sepL2sep 1.160992517 85.9825 99.82503909

1845 4096:32:1:f 4096:32:4:r GCC L1sepL2sep 1.168018837 85.9775 100.4233396

1846 4096:32:1:f 8192:32:2:f GCC L1sepL2sep 1.180013458 85.68 101.1035531

1847 4096:32:1:f 8192:32:2:l GCC L1sepL2sep 1.17568117 85.6825 100.7353019

1848 4096:32:1:f 8192:32:2:r GCC L1sepL2sep 1.181361941 85.6775 101.2161377

1849 4096:32:1:l 16384:32:1:f GCC L1sepL2sep 1.251688775 85.5325 107.0600701

1850 4096:32:1:l 16384:32:1:l GCC L1sepL2sep 1.251688775 85.535 107.0631993

1851 4096:32:1:l 16384:32:1:r GCC L1sepL2sep 1.251688775 85.53 107.0569409

1852 4096:32:1:l 2048:32:8:f GCC L1sepL2sep 1.156352228 86.5825 100.1198668

1853 4096:32:1:l 2048:32:8:l GCC L1sepL2sep 1.149890567 86.585 99.56327476

1854 4096:32:1:l 2048:32:8:r GCC L1sepL2sep 1.160873608 86.58 100.508437

1855 4096:32:1:l 4096:32:4:f GCC L1sepL2sep 1.166563604 85.9825 100.3040551

1856 4096:32:1:l 4096:32:4:l GCC L1sepL2sep 1.160992517 85.985 99.82794157

1857 4096:32:1:l 4096:32:4:r GCC L1sepL2sep 1.168018837 85.98 100.4262596

1858 4096:32:1:l 8192:32:2:f GCC L1sepL2sep 1.180013458 85.6825 101.1065031

1859 4096:32:1:l 8192:32:2:l GCC L1sepL2sep 1.17568117 85.685 100.7382411

1860 4096:32:1:l 8192:32:2:r GCC L1sepL2sep 1.181361941 85.68 101.2190911

1861 4096:32:1:r 16384:32:1:f GCC L1sepL2sep 1.251688775 85.5275 107.0538117

1862 4096:32:1:r 16384:32:1:l GCC L1sepL2sep 1.251688775 85.53 107.0569409

1863 4096:32:1:r 16384:32:1:r GCC L1sepL2sep 1.251688775 85.525 107.0506824

1864 4096:32:1:r 2048:32:8:f GCC L1sepL2sep 1.156352228 86.5775 100.114085

1865 4096:32:1:r 2048:32:8:l GCC L1sepL2sep 1.149890567 86.58 99.5575253

1866 4096:32:1:r 2048:32:8:r GCC L1sepL2sep 1.160928608 86.575 100.5073942

1867 4096:32:1:r 4096:32:4:f GCC L1sepL2sep 1.166563604 85.9775 100.2982223

1868 4096:32:1:r 4096:32:4:l GCC L1sepL2sep 1.160992517 85.98 99.8221366

1869 4096:32:1:r 4096:32:4:r GCC L1sepL2sep 1.167908838 85.975 100.4109624

1870 4096:32:1:r 8192:32:2:f GCC L1sepL2sep 1.180013458 85.6775 101.1006031

1871 4096:32:1:r 8192:32:2:l GCC L1sepL2sep 1.17568117 85.68 100.7323627

1872 4096:32:1:r 8192:32:2:r GCC L1sepL2sep 1.18141694 85.675 101.2178964

1873 512:32:8:f 16384:32:1:f GCC L1sepL2sep 1.153683859 86.58 99.88594854

1874 512:32:8:f 16384:32:1:l GCC L1sepL2sep 1.153683859 86.5825 99.88883275

1875 512:32:8:f 16384:32:1:r GCC L1sepL2sep 1.153683859 86.5775 99.88306433

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61

1876 512:32:8:f 2048:32:8:f GCC L1sepL2sep 1.100633049 87.63 96.44847406

1877 512:32:8:f 2048:32:8:l GCC L1sepL2sep 1.094408716 87.6325 95.90577182

1878 512:32:8:f 2048:32:8:r GCC L1sepL2sep 1.105603363 87.6275 96.88125866

1879 512:32:8:f 4096:32:4:f GCC L1sepL2sep 1.110755994 87.03 96.66909416

1880 512:32:8:f 4096:32:4:l GCC L1sepL2sep 1.105529855 87.0325 96.21702712

1881 512:32:8:f 4096:32:4:r GCC L1sepL2sep 1.112504037 87.0275 96.81844505

1882 512:32:8:f 8192:32:2:f GCC L1sepL2sep 1.124098907 86.73 97.49309821

1883 512:32:8:f 8192:32:2:l GCC L1sepL2sep 1.12067664 86.7325 97.19908666

1884 512:32:8:f 8192:32:2:r GCC L1sepL2sep 1.124897079 86.7275 97.55951144

1885 512:32:8:l 16384:32:1:f GCC L1sepL2sep 1.140510115 86.5825 98.748217

1886 512:32:8:l 16384:32:1:l GCC L1sepL2sep 1.140510115 86.585 98.75106828

1887 512:32:8:l 16384:32:1:r GCC L1sepL2sep 1.140510115 86.58 98.74536573

1888 512:32:8:l 2048:32:8:f GCC L1sepL2sep 1.09393274 87.6325 95.8640608

1889 512:32:8:l 2048:32:8:l GCC L1sepL2sep 1.088279269 87.635 95.37135378

1890 512:32:8:l 2048:32:8:r GCC L1sepL2sep 1.098814117 87.63 96.28908105

1891 512:32:8:l 4096:32:4:f GCC L1sepL2sep 1.103787369 87.0325 96.06537421

1892 512:32:8:l 4096:32:4:l GCC L1sepL2sep 1.099529838 87.035 95.69757942

1893 512:32:8:l 4096:32:4:r GCC L1sepL2sep 1.105273058 87.03 96.19191427

1894 512:32:8:l 8192:32:2:f GCC L1sepL2sep 1.116537427 86.7325 96.84008236

1895 512:32:8:l 8192:32:2:l GCC L1sepL2sep 1.114006402 86.735 96.62334526

1896 512:32:8:l 8192:32:2:r GCC L1sepL2sep 1.116911003 86.73 96.86969133

1897 512:32:8:r 16384:32:1:f GCC L1sepL2sep 1.153023817 86.5775 99.82591955

1898 512:32:8:r 16384:32:1:l GCC L1sepL2sep 1.153023817 86.58 99.82880211

1899 512:32:8:r 16384:32:1:r GCC L1sepL2sep 1.15308429 86.575 99.82827244

1900 512:32:8:r 2048:32:8:f GCC L1sepL2sep 1.103773957 87.6275 96.72095239

1901 512:32:8:r 2048:32:8:l GCC L1sepL2sep 1.097686109 87.63 96.19023376

1902 512:32:8:r 2048:32:8:r GCC L1sepL2sep 1.109373776 87.625 97.20887716

1903 512:32:8:r 4096:32:4:f GCC L1sepL2sep 1.113825709 87.0275 96.93346691

1904 512:32:8:r 4096:32:4:l GCC L1sepL2sep 1.108901004 87.03 96.50765439

1905 512:32:8:r 4096:32:4:r GCC L1sepL2sep 1.115874375 87.025 97.10896745

1906 512:32:8:r 8192:32:2:f GCC L1sepL2sep 1.126890583 86.7275 97.73240302

1907 512:32:8:r 8192:32:2:l GCC L1sepL2sep 1.123549251 86.73 97.44542656

1908 512:32:8:r 8192:32:2:r GCC L1sepL2sep 1.127648187 86.725 97.79528905

1909 512:64:4:f 1024:64:8:f GCC L1sepL2sep 1.074619622 87.03 93.52414569

1910 512:64:4:f 1024:64:8:l GCC L1sepL2sep 1.070122635 87.0325 93.13544821

1911 512:64:4:f 1024:64:8:r GCC L1sepL2sep 1.076495455 87.0275 93.68470817

1912 512:64:4:f 2048:64:4:f GCC L1sepL2sep 1.080785339 86.43 93.41227687

1913 512:64:4:f 2048:64:4:l GCC L1sepL2sep 1.076826997 86.4325 93.07284939

1914 512:64:4:f 2048:64:4:r GCC L1sepL2sep 1.081109912 86.4275 93.43762689

1915 512:64:4:f 4096:64:2:f GCC L1sepL2sep 1.089246998 86.13 93.8168439

1916 512:64:4:f 4096:64:2:l GCC L1sepL2sep 1.086645129 86.1325 93.59546155

Page 62: Cache Design for an Alpha Microprocessor

62

1917 512:64:4:f 4096:64:2:r GCC L1sepL2sep 1.089592877 86.1275 93.84391049

1918 512:64:4:f 8192:64:1:f GCC L1sepL2sep 1.112464674 85.98 95.6497127

1919 512:64:4:f 8192:64:1:l GCC L1sepL2sep 1.112464674 85.9825 95.65249386

1920 512:64:4:f 8192:64:1:r GCC L1sepL2sep 1.112464674 85.9775 95.64693153

1921 512:64:4:l 1024:64:8:f GCC L1sepL2sep 1.069303828 87.0325 93.06418542

1922 512:64:4:l 1024:64:8:l GCC L1sepL2sep 1.065089948 87.035 92.70010363

1923 512:64:4:l 1024:64:8:r GCC L1sepL2sep 1.071035989 87.03 93.2122621

1924 512:64:4:l 2048:64:4:f GCC L1sepL2sep 1.075365718 86.4325 92.94654743

1925 512:64:4:l 2048:64:4:l GCC L1sepL2sep 1.071928677 86.435 92.65215522

1926 512:64:4:l 2048:64:4:r GCC L1sepL2sep 1.075401591 86.43 92.94695951

1927 512:64:4:l 4096:64:2:f GCC L1sepL2sep 1.083407412 86.1325 93.31658887

1928 512:64:4:l 4096:64:2:l GCC L1sepL2sep 1.081307352 86.135 93.13840873

1929 512:64:4:l 4096:64:2:r GCC L1sepL2sep 1.083366151 86.13 93.31032661

1930 512:64:4:l 8192:64:1:f GCC L1sepL2sep 1.101931679 85.9825 94.74684057

1931 512:64:4:l 8192:64:1:l GCC L1sepL2sep 1.101931679 85.985 94.7495954

1932 512:64:4:l 8192:64:1:r GCC L1sepL2sep 1.101931679 85.98 94.74408574

1933 512:64:4:r 1024:64:8:f GCC L1sepL2sep 1.076287617 87.0275 93.66662058

1934 512:64:4:r 1024:64:8:l GCC L1sepL2sep 1.071817104 87.03 93.28024252

1935 512:64:4:r 1024:64:8:r GCC L1sepL2sep 1.078473465 87.025 93.85415327

1936 512:64:4:r 2048:64:4:f GCC L1sepL2sep 1.082361197 86.4275 93.54577238

1937 512:64:4:r 2048:64:4:l GCC L1sepL2sep 1.078574399 86.43 93.22118526

1938 512:64:4:r 2048:64:4:r GCC L1sepL2sep 1.082691831 86.425 93.57164145

1939 512:64:4:r 4096:64:2:f GCC L1sepL2sep 1.090643821 86.1275 93.93442569

1940 512:64:4:r 4096:64:2:l GCC L1sepL2sep 1.08809558 86.13 93.71767232

1941 512:64:4:r 4096:64:2:r GCC L1sepL2sep 1.090993684 86.125 93.96183102

1942 512:64:4:r 8192:64:1:f GCC L1sepL2sep 1.11132437 85.9775 95.54889104

1943 512:64:4:r 8192:64:1:l GCC L1sepL2sep 1.11132437 85.98 95.55166935

1944 512:64:4:r 8192:64:1:r GCC L1sepL2sep 1.111238243 85.975 95.53870793

1945 1024:32:4:f 16384:32:1:f GCC L1sepL2sep 1.159220383 85.98 99.66976853

1946 1024:32:4:f 16384:32:1:l GCC L1sepL2sep 1.159220383 85.9825 99.67266658

1947 1024:32:4:f 16384:32:1:r GCC L1sepL2sep 1.159220383 85.9775 99.66687048

1948 1024:32:4:f 2048:32:8:f GCC L1sepL2sep 1.104310175 87.03 96.10811457

1949 1024:32:4:f 2048:32:8:l GCC L1sepL2sep 1.098038882 87.0325 95.56506902

1950 1024:32:4:f 2048:32:8:r GCC L1sepL2sep 1.109218363 87.0275 96.53250108

1951 1024:32:4:f 4096:32:4:f GCC L1sepL2sep 1.114419134 86.43 96.31924575

1952 1024:32:4:f 4096:32:4:l GCC L1sepL2sep 1.109165292 86.4325 95.86792906

1953 1024:32:4:f 4096:32:4:r GCC L1sepL2sep 1.116068671 86.4275 96.45902509

1954 1024:32:4:f 8192:32:2:f GCC L1sepL2sep 1.127895196 86.13 97.14561322

1955 1024:32:4:f 8192:32:2:l GCC L1sepL2sep 1.124336039 86.1325 96.84187391

1956 1024:32:4:f 8192:32:2:r GCC L1sepL2sep 1.12865542 86.1275 97.20826968

1957 1024:32:4:l 16384:32:1:f GCC L1sepL2sep 1.146972802 85.9825 98.61958896

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1958 1024:32:4:l 16384:32:1:l GCC L1sepL2sep 1.146972802 85.985 98.6224564

1959 1024:32:4:l 16384:32:1:r GCC L1sepL2sep 1.146972802 85.98 98.61672153

1960 1024:32:4:l 2048:32:8:f GCC L1sepL2sep 1.098103326 87.0325 95.57067776

1961 1024:32:4:l 2048:32:8:l GCC L1sepL2sep 1.092259768 87.035 95.06482894

1962 1024:32:4:l 2048:32:8:r GCC L1sepL2sep 1.102858834 87.03 95.98180431

1963 1024:32:4:l 4096:32:4:f GCC L1sepL2sep 1.108099846 86.4325 95.77583992

1964 1024:32:4:l 4096:32:4:l GCC L1sepL2sep 1.103504497 86.435 95.38141117

1965 1024:32:4:l 4096:32:4:r GCC L1sepL2sep 1.109642951 86.43 95.90644025

1966 1024:32:4:l 8192:32:2:f GCC L1sepL2sep 1.121058959 86.1325 96.55961079

1967 1024:32:4:l 8192:32:2:l GCC L1sepL2sep 1.118263996 86.135 96.3216693

1968 1024:32:4:l 8192:32:2:r GCC L1sepL2sep 1.121425919 86.13 96.58841443

1969 1024:32:4:r 16384:32:1:f GCC L1sepL2sep 1.158253991 85.9775 99.58378252

1970 1024:32:4:r 16384:32:1:l GCC L1sepL2sep 1.158253991 85.98 99.58667815

1971 1024:32:4:r 16384:32:1:r GCC L1sepL2sep 1.158219754 85.975 99.57794338

1972 1024:32:4:r 2048:32:8:f GCC L1sepL2sep 1.106893518 87.0275 96.33017567

1973 1024:32:4:r 2048:32:8:l GCC L1sepL2sep 1.10073499 87.03 95.79696617

1974 1024:32:4:r 2048:32:8:r GCC L1sepL2sep 1.112427502 87.025 96.80900333

1975 1024:32:4:r 4096:32:4:f GCC L1sepL2sep 1.116964791 86.4275 96.5364745

1976 1024:32:4:r 4096:32:4:l GCC L1sepL2sep 1.111922447 86.43 96.1034571

1977 1024:32:4:r 4096:32:4:r GCC L1sepL2sep 1.118998385 86.425 96.70943544

1978 1024:32:4:r 8192:32:2:f GCC L1sepL2sep 1.1301405 86.1275 97.33617588

1979 1024:32:4:r 8192:32:2:l GCC L1sepL2sep 1.126657646 86.13 97.03902304

1980 1024:32:4:r 8192:32:2:r GCC L1sepL2sep 1.13114368 86.125 97.41974948

1981 1024:64:2:f 1024:64:8:f GCC L1sepL2sep 1.083661068 86.73 93.98592445

1982 1024:64:2:f 1024:64:8:l GCC L1sepL2sep 1.079156731 86.7325 93.59796121

1983 1024:64:2:f 1024:64:8:r GCC L1sepL2sep 1.085518154 86.7275 94.14427568

1984 1024:64:2:f 2048:64:4:f GCC L1sepL2sep 1.089794091 86.13 93.86396504

1985 1024:64:2:f 2048:64:4:l GCC L1sepL2sep 1.085820648 86.1325 93.52444695

1986 1024:64:2:f 2048:64:4:r GCC L1sepL2sep 1.090152497 86.1275 93.89210915

1987 1024:64:2:f 4096:64:2:f GCC L1sepL2sep 1.09841516 85.83 94.27697317

1988 1024:64:2:f 4096:64:2:l GCC L1sepL2sep 1.095583277 85.8325 94.03665162

1989 1024:64:2:f 4096:64:2:r GCC L1sepL2sep 1.09873061 85.8275 94.30130145

1990 1024:64:2:f 8192:64:1:f GCC L1sepL2sep 1.126453669 85.68 96.51455033

1991 1024:64:2:f 8192:64:1:l GCC L1sepL2sep 1.126453669 85.6825 96.51736647

1992 1024:64:2:f 8192:64:1:r GCC L1sepL2sep 1.126453669 85.6775 96.5117342

1993 1024:64:2:l 1024:64:8:f GCC L1sepL2sep 1.080272785 86.7325 93.69475937

1994 1024:64:2:l 1024:64:8:l GCC L1sepL2sep 1.075858201 86.735 93.31456105

1995 1024:64:2:l 1024:64:8:r GCC L1sepL2sep 1.082101567 86.73 93.85066888

1996 1024:64:2:l 2048:64:4:f GCC L1sepL2sep 1.086355338 86.1325 93.57050117

1997 1024:64:2:l 2048:64:4:l GCC L1sepL2sep 1.08261928 86.135 93.25141165

1998 1024:64:2:l 2048:64:4:r GCC L1sepL2sep 1.086563056 86.13 93.58567599

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1999 1024:64:2:l 4096:64:2:f GCC L1sepL2sep 1.094705889 85.8325 93.96134322

2000 1024:64:2:l 4096:64:2:l GCC L1sepL2sep 1.092289414 85.835 93.75666185

2001 1024:64:2:l 4096:64:2:r GCC L1sepL2sep 1.094979537 85.83 93.98209362

2002 1024:64:2:l 8192:64:1:f GCC L1sepL2sep 1.118207809 85.6825 95.81084056

2003 1024:64:2:l 8192:64:1:l GCC L1sepL2sep 1.118207809 85.685 95.81363608

2004 1024:64:2:l 8192:64:1:r GCC L1sepL2sep 1.118207809 85.68 95.80804504

2005 1024:64:2:r 1024:64:8:f GCC L1sepL2sep 1.084951618 86.7275 94.09514141

2006 1024:64:2:r 1024:64:8:l GCC L1sepL2sep 1.080406217 86.73 93.70363118

2007 1024:64:2:r 1024:64:8:r GCC L1sepL2sep 1.087056183 86.725 94.27494745

2008 1024:64:2:r 2048:64:4:f GCC L1sepL2sep 1.091057773 86.1275 93.97007836

2009 1024:64:2:r 2048:64:4:l GCC L1sepL2sep 1.087156616 86.13 93.63679932

2010 1024:64:2:r 2048:64:4:r GCC L1sepL2sep 1.091424506 86.125 93.99893554

2011 1024:64:2:r 4096:64:2:f GCC L1sepL2sep 1.099540822 85.8275 94.37083993

2012 1024:64:2:r 4096:64:2:l GCC L1sepL2sep 1.096839321 85.83 94.14171893

2013 1024:64:2:r 4096:64:2:r GCC L1sepL2sep 1.100002725 85.825 94.40773388

2014 1024:64:2:r 8192:64:1:f GCC L1sepL2sep 1.125258189 85.6775 96.40930846

2015 1024:64:2:r 8192:64:1:l GCC L1sepL2sep 1.125258189 85.68 96.4121216

2016 1024:64:2:r 8192:64:1:r GCC L1sepL2sep 1.125180602 85.675 96.39984804

2017 2048:32:2:f 16384:32:1:f Anagram L1sepL2sep 1.187648994 85.68 101.7577658

2018 2048:32:2:f 16384:32:1:l Anagram L1sepL2sep 1.187648994 85.6825 101.7607349

2019 2048:32:2:f 16384:32:1:r Anagram L1sepL2sep 1.187648994 85.6775 101.7547967

2020 2048:32:2:f 2048:32:8:f Anagram L1sepL2sep 1.187118 86.73 102.9587442

2021 2048:32:2:f 2048:32:8:l Anagram L1sepL2sep 1.187118 86.7325 102.961712

2022 2048:32:2:f 2048:32:8:r Anagram L1sepL2sep 1.190303961 86.7275 103.2320867

2023 2048:32:2:f 4096:32:4:f Anagram L1sepL2sep 1.1871534 86.13 102.2495223

2024 2048:32:2:f 4096:32:4:l Anagram L1sepL2sep 1.1871534 86.1325 102.2524902

2025 2048:32:2:f 4096:32:4:r Anagram L1sepL2sep 1.189949965 86.1275 102.4874156

2026 2048:32:2:f 8192:32:2:f Anagram L1sepL2sep 1.187224199 85.83 101.899453

2027 2048:32:2:f 8192:32:2:l Anagram L1sepL2sep 1.1871888 85.8325 101.8993826

2028 2048:32:2:f 8192:32:2:r Anagram L1sepL2sep 1.188923378 85.8275 102.0423212

2029 2048:32:2:l 16384:32:1:f Anagram L1sepL2sep 1.187324901 85.6825 101.7329658

2030 2048:32:2:l 16384:32:1:l Anagram L1sepL2sep 1.187324901 85.685 101.7359341

2031 2048:32:2:l 16384:32:1:r Anagram L1sepL2sep 1.187324901 85.68 101.7299975

2032 2048:32:2:l 2048:32:8:f Anagram L1sepL2sep 1.186866902 86.7325 102.9399336

2033 2048:32:2:l 2048:32:8:l Anagram L1sepL2sep 1.186866902 86.735 102.9429008

2034 2048:32:2:l 2048:32:8:r Anagram L1sepL2sep 1.190178584 86.73 103.2241886

2035 2048:32:2:l 4096:32:4:f Anagram L1sepL2sep 1.186866902 86.1325 102.2278135

2036 2048:32:2:l 4096:32:4:l Anagram L1sepL2sep 1.186902133 86.135 102.2338152

2037 2048:32:2:l 4096:32:4:r Anagram L1sepL2sep 1.189227356 86.13 102.4281522

2038 2048:32:2:l 8192:32:2:f Anagram L1sepL2sep 1.186902133 85.8325 101.8747773

2039 2048:32:2:l 8192:32:2:l Anagram L1sepL2sep 1.186937364 85.835 101.8807686

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2040 2048:32:2:l 8192:32:2:r Anagram L1sepL2sep 1.188487513 85.83 102.0078832

2041 2048:32:2:r 16384:32:1:f Anagram L1sepL2sep 1.187805534 85.6775 101.7682086

2042 2048:32:2:r 16384:32:1:l Anagram L1sepL2sep 1.187805534 85.68 101.7711782

2043 2048:32:2:r 16384:32:1:r Anagram L1sepL2sep 1.187754644 85.675 101.7608791

2044 2048:32:2:r 2048:32:8:f Anagram L1sepL2sep 1.187131399 86.7275 102.9569384

2045 2048:32:2:r 2048:32:8:l Anagram L1sepL2sep 1.187131399 86.73 102.9599062

2046 2048:32:2:r 2048:32:8:r Anagram L1sepL2sep 1.195663631 86.725 103.6939284

2047 2048:32:2:r 4096:32:4:f Anagram L1sepL2sep 1.187131399 86.1275 102.2446595

2048 2048:32:2:r 4096:32:4:l Anagram L1sepL2sep 1.187131399 86.13 102.2476274

2049 2048:32:2:r 4096:32:4:r Anagram L1sepL2sep 1.191467884 86.125 102.6151715

2050 2048:32:2:r 8192:32:2:f Anagram L1sepL2sep 1.187237841 85.8275 101.8976558

2051 2048:32:2:r 8192:32:2:l Anagram L1sepL2sep 1.187344284 85.83 101.9097599

2052 2048:32:2:r 8192:32:2:r Anagram L1sepL2sep 1.186985314 85.825 101.8730145

2053 2048:64:1:f 1024:64:8:f Anagram L1sepL2sep 1.103483424 86.58 95.53959488

2054 2048:64:1:f 1024:64:8:l Anagram L1sepL2sep 1.103483424 86.5825 95.54235359

2055 2048:64:1:f 1024:64:8:r Anagram L1sepL2sep 1.104589213 86.5775 95.63257262

2056 2048:64:1:f 2048:64:4:f Anagram L1sepL2sep 1.103510206 85.98 94.87980751

2057 2048:64:1:f 2048:64:4:l Anagram L1sepL2sep 1.103483424 85.9825 94.88026353

2058 2048:64:1:f 2048:64:4:r Anagram L1sepL2sep 1.103885149 85.9775 94.90928539

2059 2048:64:1:f 4096:64:2:f Anagram L1sepL2sep 1.103590551 85.68 94.5556384

2060 2048:64:1:f 4096:64:2:l Anagram L1sepL2sep 1.103536988 85.6825 94.55380794

2061 2048:64:1:f 4096:64:2:r Anagram L1sepL2sep 1.101635491 85.6775 94.38537478

2062 2048:64:1:f 8192:64:1:f Anagram L1sepL2sep 1.115802979 85.53 95.43462883

2063 2048:64:1:f 8192:64:1:l Anagram L1sepL2sep 1.115802979 85.5325 95.43741834

2064 2048:64:1:f 8192:64:1:r Anagram L1sepL2sep 1.115802979 85.5275 95.43183933

2065 2048:64:1:l 1024:64:8:f Anagram L1sepL2sep 1.103483424 86.5825 95.54235359

2066 2048:64:1:l 1024:64:8:l Anagram L1sepL2sep 1.103483424 86.585 95.54511229

2067 2048:64:1:l 1024:64:8:r Anagram L1sepL2sep 1.104589213 86.58 95.63533409

2068 2048:64:1:l 2048:64:4:f Anagram L1sepL2sep 1.103510206 85.9825 94.88256628

2069 2048:64:1:l 2048:64:4:l Anagram L1sepL2sep 1.103483424 85.985 94.88302224

2070 2048:64:1:l 2048:64:4:r Anagram L1sepL2sep 1.103885149 85.98 94.91204511

2071 2048:64:1:l 4096:64:2:f Anagram L1sepL2sep 1.103590551 85.6825 94.55839738

2072 2048:64:1:l 4096:64:2:l Anagram L1sepL2sep 1.103536988 85.685 94.55656678

2073 2048:64:1:l 4096:64:2:r Anagram L1sepL2sep 1.101635491 85.68 94.38812887

2074 2048:64:1:l 8192:64:1:f Anagram L1sepL2sep 1.115802979 85.5325 95.43741834

2075 2048:64:1:l 8192:64:1:l Anagram L1sepL2sep 1.115802979 85.535 95.44020785

2076 2048:64:1:l 8192:64:1:r Anagram L1sepL2sep 1.115802979 85.53 95.43462883

2077 2048:64:1:r 1024:64:8:f Anagram L1sepL2sep 1.103483424 86.5775 95.53683617

2078 2048:64:1:r 1024:64:8:l Anagram L1sepL2sep 1.103483424 86.58 95.53959488

2079 2048:64:1:r 1024:64:8:r Anagram L1sepL2sep 1.104883811 86.575 95.65531597

2080 2048:64:1:r 2048:64:4:f Anagram L1sepL2sep 1.103510206 85.9775 94.87704873

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2081 2048:64:1:r 2048:64:4:l Anagram L1sepL2sep 1.103483424 85.98 94.87750482

2082 2048:64:1:r 2048:64:4:r Anagram L1sepL2sep 1.103804804 85.975 94.89961802

2083 2048:64:1:r 4096:64:2:f Anagram L1sepL2sep 1.103590551 85.6775 94.55287942

2084 2048:64:1:r 4096:64:2:l Anagram L1sepL2sep 1.103536988 85.68 94.5510491

2085 2048:64:1:r 4096:64:2:r Anagram L1sepL2sep 1.101635491 85.675 94.38262069

2086 2048:64:1:r 8192:64:1:f Anagram L1sepL2sep 1.115802979 85.5275 95.43183933

2087 2048:64:1:r 8192:64:1:l Anagram L1sepL2sep 1.115802979 85.53 95.43462883

2088 2048:64:1:r 8192:64:1:r Anagram L1sepL2sep 1.115802979 85.525 95.42904982

2089 256:64:8:f 1024:64:8:f Anagram L1sepL2sep 1.093837395 87.63 95.8529709

2090 256:64:8:f 1024:64:8:l Anagram L1sepL2sep 1.093837395 87.6325 95.85570549

2091 256:64:8:f 1024:64:8:r Anagram L1sepL2sep 1.095540902 87.6275 95.99951042

2092 256:64:8:f 2048:64:4:f Anagram L1sepL2sep 1.09385514 87.03 95.1982128

2093 256:64:8:f 2048:64:4:l Anagram L1sepL2sep 1.093872884 87.0325 95.20249182

2094 256:64:8:f 2048:64:4:r Anagram L1sepL2sep 1.095292474 87.0275 95.3205658

2095 256:64:8:f 4096:64:2:f Anagram L1sepL2sep 1.093926119 86.73 94.87621231

2096 256:64:8:f 4096:64:2:l Anagram L1sepL2sep 1.093908374 86.7325 94.87740807

2097 256:64:8:f 4096:64:2:r Anagram L1sepL2sep 1.095008556 86.7275 94.96735456

2098 256:64:8:f 8192:64:1:f Anagram L1sepL2sep 1.094210037 86.58 94.73670501

2099 256:64:8:f 8192:64:1:l Anagram L1sepL2sep 1.094210037 86.5825 94.73944053

2100 256:64:8:f 8192:64:1:r Anagram L1sepL2sep 1.094210037 86.5775 94.73396948

2101 256:64:8:l 1024:64:8:f Anagram L1sepL2sep 1.093846638 87.6325 95.85651553

2102 256:64:8:l 1024:64:8:l Anagram L1sepL2sep 1.093846638 87.635 95.85925015

2103 256:64:8:l 1024:64:8:r Anagram L1sepL2sep 1.09552003 87.63 96.00042021

2104 256:64:8:l 2048:64:4:f Anagram L1sepL2sep 1.093846638 87.0325 95.20020755

2105 256:64:8:l 2048:64:4:l Anagram L1sepL2sep 1.093864253 87.035 95.20447526

2106 256:64:8:l 2048:64:4:r Anagram L1sepL2sep 1.095114893 87.03 95.30784913

2107 256:64:8:l 4096:64:2:f Anagram L1sepL2sep 1.093881868 86.7325 94.87510908

2108 256:64:8:l 4096:64:2:l Anagram L1sepL2sep 1.093917097 86.735 94.8808994

2109 256:64:8:l 4096:64:2:r Anagram L1sepL2sep 1.094727371 86.73 94.94570486

2110 256:64:8:l 8192:64:1:f Anagram L1sepL2sep 1.094110858 86.5825 94.73085336

2111 256:64:8:l 8192:64:1:l Anagram L1sepL2sep 1.094110858 86.585 94.73358864

2112 256:64:8:l 8192:64:1:r Anagram L1sepL2sep 1.094110858 86.58 94.72811809

2113 256:64:8:r 1024:64:8:f Anagram L1sepL2sep 1.093867206 87.6275 95.85284859

2114 256:64:8:r 1024:64:8:l Anagram L1sepL2sep 1.093884997 87.63 95.85714226

2115 256:64:8:r 1024:64:8:r Anagram L1sepL2sep 1.09994895 87.625 96.38302671

2116 256:64:8:r 2048:64:4:f Anagram L1sepL2sep 1.093867206 87.0275 95.19652826

2117 256:64:8:r 2048:64:4:l Anagram L1sepL2sep 1.09397395 87.03 95.2085529

2118 256:64:8:r 2048:64:4:r Anagram L1sepL2sep 1.097232234 87.025 95.48663517

2119 256:64:8:r 4096:64:2:f Anagram L1sepL2sep 1.09397395 86.7275 94.87762578

2120 256:64:8:r 4096:64:2:l Anagram L1sepL2sep 1.094098486 86.73 94.89116165

2121 256:64:8:r 4096:64:2:r Anagram L1sepL2sep 1.095066125 86.725 94.96960972

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2122 256:64:8:r 8192:64:1:f Anagram L1sepL2sep 1.094418719 86.5775 94.75203664

2123 256:64:8:r 8192:64:1:l Anagram L1sepL2sep 1.094418719 86.58 94.75477268

2124 256:64:8:r 8192:64:1:r Anagram L1sepL2sep 1.094420075 86.575 94.74941797

2125 4096:32:1:f 16384:32:1:f Anagram L1sepL2sep 1.195867126 85.53 102.2825153

2126 4096:32:1:f 16384:32:1:l Anagram L1sepL2sep 1.195867126 85.5325 102.2855049

2127 4096:32:1:f 16384:32:1:r Anagram L1sepL2sep 1.195867126 85.5275 102.2795256

2128 4096:32:1:f 2048:32:8:f Anagram L1sepL2sep 1.194682452 86.58 103.4356067

2129 4096:32:1:f 2048:32:8:l Anagram L1sepL2sep 1.194682452 86.5825 103.4385934

2130 4096:32:1:f 2048:32:8:r Anagram L1sepL2sep 1.197099994 86.5775 103.6419247

2131 4096:32:1:f 4096:32:4:f Anagram L1sepL2sep 1.194724762 85.98 102.722435

2132 4096:32:1:f 4096:32:4:l Anagram L1sepL2sep 1.194682452 85.9825 102.7217839

2133 4096:32:1:f 4096:32:4:r Anagram L1sepL2sep 1.19506324 85.9775 102.7485497

2134 4096:32:1:f 8192:32:2:f Anagram L1sepL2sep 1.194767071 85.68 102.3676427

2135 4096:32:1:f 8192:32:2:l Anagram L1sepL2sep 1.194724762 85.6825 102.3670044

2136 4096:32:1:f 8192:32:2:r Anagram L1sepL2sep 1.190832261 85.6775 102.027531

2137 4096:32:1:l 16384:32:1:f Anagram L1sepL2sep 1.195867126 85.5325 102.2855049

2138 4096:32:1:l 16384:32:1:l Anagram L1sepL2sep 1.195867126 85.535 102.2884946

2139 4096:32:1:l 16384:32:1:r Anagram L1sepL2sep 1.195867126 85.53 102.2825153

2140 4096:32:1:l 2048:32:8:f Anagram L1sepL2sep 1.194682452 86.5825 103.4385934

2141 4096:32:1:l 2048:32:8:l Anagram L1sepL2sep 1.194682452 86.585 103.4415801

2142 4096:32:1:l 2048:32:8:r Anagram L1sepL2sep 1.197099994 86.58 103.6449174

2143 4096:32:1:l 4096:32:4:f Anagram L1sepL2sep 1.194724762 85.9825 102.7254218

2144 4096:32:1:l 4096:32:4:l Anagram L1sepL2sep 1.194682452 85.985 102.7247706

2145 4096:32:1:l 4096:32:4:r Anagram L1sepL2sep 1.19506324 85.98 102.7515374

2146 4096:32:1:l 8192:32:2:f Anagram L1sepL2sep 1.194767071 85.6825 102.3706296

2147 4096:32:1:l 8192:32:2:l Anagram L1sepL2sep 1.194724762 85.685 102.3699912

2148 4096:32:1:l 8192:32:2:r Anagram L1sepL2sep 1.190832261 85.68 102.0305081

2149 4096:32:1:r 16384:32:1:f Anagram L1sepL2sep 1.195867126 85.5275 102.2795256

2150 4096:32:1:r 16384:32:1:l Anagram L1sepL2sep 1.195867126 85.53 102.2825153

2151 4096:32:1:r 16384:32:1:r Anagram L1sepL2sep 1.195867126 85.525 102.2765359

2152 4096:32:1:r 2048:32:8:f Anagram L1sepL2sep 1.194682452 86.5775 103.43262

2153 4096:32:1:r 2048:32:8:l Anagram L1sepL2sep 1.194682452 86.58 103.4356067

2154 4096:32:1:r 2048:32:8:r Anagram L1sepL2sep 1.196811548 86.575 103.6139597

2155 4096:32:1:r 4096:32:4:f Anagram L1sepL2sep 1.194724762 85.9775 102.7194482

2156 4096:32:1:r 4096:32:4:l Anagram L1sepL2sep 1.194682452 85.98 102.7187972

2157 4096:32:1:r 4096:32:4:r Anagram L1sepL2sep 1.194809381 85.975 102.7237365

2158 4096:32:1:r 8192:32:2:f Anagram L1sepL2sep 1.194767071 85.6775 102.3646558

2159 4096:32:1:r 8192:32:2:l Anagram L1sepL2sep 1.194724762 85.68 102.3640176

2160 4096:32:1:r 8192:32:2:r Anagram L1sepL2sep 1.190663022 85.675 102.0100544

2161 512:32:8:f 16384:32:1:f Anagram L1sepL2sep 1.187372696 86.58 102.802728

2162 512:32:8:f 16384:32:1:l Anagram L1sepL2sep 1.187372696 86.5825 102.8056964

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2163 512:32:8:f 16384:32:1:r Anagram L1sepL2sep 1.187372696 86.5775 102.7997596

2164 512:32:8:f 2048:32:8:f Anagram L1sepL2sep 1.186843152 87.63 104.0030654

2165 512:32:8:f 2048:32:8:l Anagram L1sepL2sep 1.186878454 87.6325 104.0091262

2166 512:32:8:f 2048:32:8:r Anagram L1sepL2sep 1.189985115 87.6275 104.2754206

2167 512:32:8:f 4096:32:4:f Anagram L1sepL2sep 1.186878454 87.03 103.2940319

2168 512:32:8:f 4096:32:4:l Anagram L1sepL2sep 1.186913757 87.0325 103.3000716

2169 512:32:8:f 4096:32:4:r Anagram L1sepL2sep 1.189173147 87.0275 103.490766

2170 512:32:8:f 8192:32:2:f Anagram L1sepL2sep 1.18694906 86.73 102.944092

2171 512:32:8:f 8192:32:2:l Anagram L1sepL2sep 1.18694906 86.7325 102.9470594

2172 512:32:8:f 8192:32:2:r Anagram L1sepL2sep 1.188749511 86.7275 103.0972732

2173 512:32:8:l 16384:32:1:f Anagram L1sepL2sep 1.187298341 86.5825 102.7992586

2174 512:32:8:l 16384:32:1:l Anagram L1sepL2sep 1.187298341 86.585 102.8022269

2175 512:32:8:l 16384:32:1:r Anagram L1sepL2sep 1.187298341 86.58 102.7962904

2176 512:32:8:l 2048:32:8:f Anagram L1sepL2sep 1.186841818 87.6325 104.0059156

2177 512:32:8:l 2048:32:8:l Anagram L1sepL2sep 1.186876935 87.635 104.0119602

2178 512:32:8:l 2048:32:8:r Anagram L1sepL2sep 1.190107713 87.63 104.2891389

2179 512:32:8:l 4096:32:4:f Anagram L1sepL2sep 1.186876935 87.0325 103.2968669

2180 512:32:8:l 4096:32:4:l Anagram L1sepL2sep 1.186876935 87.035 103.2998341

2181 512:32:8:l 4096:32:4:r Anagram L1sepL2sep 1.18915955 87.03 103.4925556

2182 512:32:8:l 8192:32:2:f Anagram L1sepL2sep 1.186912052 86.7325 102.9438496

2183 512:32:8:l 8192:32:2:l Anagram L1sepL2sep 1.18694717 86.735 102.9498628

2184 512:32:8:l 8192:32:2:r Anagram L1sepL2sep 1.188562558 86.73 103.0840307

2185 512:32:8:r 16384:32:1:f Anagram L1sepL2sep 1.187773226 86.5775 102.8344365

2186 512:32:8:r 16384:32:1:l Anagram L1sepL2sep 1.187773226 86.58 102.8374059

2187 512:32:8:r 16384:32:1:r Anagram L1sepL2sep 1.18777844 86.575 102.8319185

2188 512:32:8:r 2048:32:8:f Anagram L1sepL2sep 1.186889812 87.6275 104.004187

2189 512:32:8:r 2048:32:8:l Anagram L1sepL2sep 1.186960485 87.63 104.0133473

2190 512:32:8:r 2048:32:8:r Anagram L1sepL2sep 1.198852701 87.625 105.0494679

2191 512:32:8:r 4096:32:4:f Anagram L1sepL2sep 1.186925148 87.0275 103.2951283

2192 512:32:8:r 4096:32:4:l Anagram L1sepL2sep 1.187137168 87.03 103.3165477

2193 512:32:8:r 4096:32:4:r Anagram L1sepL2sep 1.193626229 87.025 103.8753226

2194 512:32:8:r 8192:32:2:f Anagram L1sepL2sep 1.187031158 86.7275 102.9482447

2195 512:32:8:r 8192:32:2:l Anagram L1sepL2sep 1.187313851 86.73 102.9757303

2196 512:32:8:r 8192:32:2:r Anagram L1sepL2sep 1.188466071 86.725 103.06972

2197 512:64:4:f 1024:64:8:f Anagram L1sepL2sep 1.093832533 87.03 95.1962453

2198 512:64:4:f 1024:64:8:l Anagram L1sepL2sep 1.093850288 87.0325 95.2005252

2199 512:64:4:f 1024:64:8:r Anagram L1sepL2sep 1.095377266 87.0275 95.32794505

2200 512:64:4:f 2048:64:4:f Anagram L1sepL2sep 1.093850288 86.43 94.5414804

2201 512:64:4:f 2048:64:4:l Anagram L1sepL2sep 1.093850288 86.4325 94.54421502

2202 512:64:4:f 2048:64:4:r Anagram L1sepL2sep 1.095181955 86.4275 94.65383843

2203 512:64:4:f 4096:64:2:f Anagram L1sepL2sep 1.093939066 86.13 94.22097174

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2204 512:64:4:f 4096:64:2:l Anagram L1sepL2sep 1.09392131 86.1325 94.22217726

2205 512:64:4:f 4096:64:2:r Anagram L1sepL2sep 1.094613777 86.1275 94.2763481

2206 512:64:4:f 8192:64:1:f Anagram L1sepL2sep 1.094223155 85.98 94.08130685

2207 512:64:4:f 8192:64:1:l Anagram L1sepL2sep 1.094223155 85.9825 94.08404241

2208 512:64:4:f 8192:64:1:r Anagram L1sepL2sep 1.094223155 85.9775 94.0785713

2209 512:64:4:l 1024:64:8:f Anagram L1sepL2sep 1.093839872 87.0325 95.19961865

2210 512:64:4:l 1024:64:8:l Anagram L1sepL2sep 1.093839872 87.035 95.20235325

2211 512:64:4:l 1024:64:8:r Anagram L1sepL2sep 1.095672846 87.03 95.35640782

2212 512:64:4:l 2048:64:4:f Anagram L1sepL2sep 1.093839872 86.4325 94.54331473

2213 512:64:4:l 2048:64:4:l Anagram L1sepL2sep 1.093857497 86.435 94.54757272

2214 512:64:4:l 2048:64:4:r Anagram L1sepL2sep 1.095144104 86.43 94.65330488

2215 512:64:4:l 4096:64:2:f Anagram L1sepL2sep 1.093892746 86.1325 94.21971696

2216 512:64:4:l 4096:64:2:l Anagram L1sepL2sep 1.093910371 86.135 94.2239698

2217 512:64:4:l 4096:64:2:r Anagram L1sepL2sep 1.094738734 86.13 94.28984719

2218 512:64:4:l 8192:64:1:f Anagram L1sepL2sep 1.094104243 85.9825 94.07381809

2219 512:64:4:l 8192:64:1:l Anagram L1sepL2sep 1.094104243 85.985 94.07655335

2220 512:64:4:l 8192:64:1:r Anagram L1sepL2sep 1.094104243 85.98 94.07108283

2221 512:64:4:r 1024:64:8:f Anagram L1sepL2sep 1.093869187 87.0275 95.19670071

2222 512:64:4:r 1024:64:8:l Anagram L1sepL2sep 1.093887002 87.03 95.20098581

2223 512:64:4:r 1024:64:8:r Anagram L1sepL2sep 1.09932527 87.025 95.66878165

2224 512:64:4:r 2048:64:4:f Anagram L1sepL2sep 1.093869187 86.4275 94.5403792

2225 512:64:4:r 2048:64:4:l Anagram L1sepL2sep 1.093940447 86.43 94.54927282

2226 512:64:4:r 2048:64:4:r Anagram L1sepL2sep 1.096805049 86.425 94.79137638

2227 512:64:4:r 4096:64:2:f Anagram L1sepL2sep 1.093958262 86.1275 94.21989018

2228 512:64:4:r 4096:64:2:l Anagram L1sepL2sep 1.094065151 86.13 94.23183143

2229 512:64:4:r 4096:64:2:r Anagram L1sepL2sep 1.09449893 86.125 94.26372034

2230 512:64:4:r 8192:64:1:f Anagram L1sepL2sep 1.094332373 85.9775 94.08796163

2231 512:64:4:r 8192:64:1:l Anagram L1sepL2sep 1.094332373 85.98 94.09069746

2232 512:64:4:r 8192:64:1:r Anagram L1sepL2sep 1.094343347 85.975 94.08616929

2233 1024:32:4:f 16384:32:1:f Anagram L1sepL2sep 1.187421536 85.98 102.0945037

2234 1024:32:4:f 16384:32:1:l Anagram L1sepL2sep 1.187421536 85.9825 102.0974722

2235 1024:32:4:f 16384:32:1:r Anagram L1sepL2sep 1.187421536 85.9775 102.0915351

2236 1024:32:4:f 2048:32:8:f Anagram L1sepL2sep 1.186856393 87.03 103.2921119

2237 1024:32:4:f 2048:32:8:l Anagram L1sepL2sep 1.186856393 87.0325 103.2950791

2238 1024:32:4:f 2048:32:8:r Anagram L1sepL2sep 1.19 87.0275 103.562725

2239 1024:32:4:f 4096:32:4:f Anagram L1sepL2sep 1.186891715 86.43 102.5830509

2240 1024:32:4:f 4096:32:4:l Anagram L1sepL2sep 1.186891715 86.4325 102.5860181

2241 1024:32:4:f 4096:32:4:r Anagram L1sepL2sep 1.189364214 86.4275 102.7937756

2242 1024:32:4:f 8192:32:2:f Anagram L1sepL2sep 1.186962358 86.13 102.2330679

2243 1024:32:4:f 8192:32:2:l Anagram L1sepL2sep 1.186927036 86.1325 102.2329929

2244 1024:32:4:f 8192:32:2:r Anagram L1sepL2sep 1.188799072 86.1275 102.388292

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2246 1024:32:4:l 16384:32:1:l Anagram L1sepL2sep 1.187322426 85.985 102.0919188

2247 1024:32:4:l 16384:32:1:r Anagram L1sepL2sep 1.187322426 85.98 102.0859821

2248 1024:32:4:l 2048:32:8:f Anagram L1sepL2sep 1.186865635 87.0325 103.2958834

2249 1024:32:4:l 2048:32:8:l Anagram L1sepL2sep 1.186865635 87.035 103.2988505

2250 1024:32:4:l 2048:32:8:r Anagram L1sepL2sep 1.190098308 87.03 103.5742557

2251 1024:32:4:l 4096:32:4:f Anagram L1sepL2sep 1.186865635 86.4325 102.583764

2252 1024:32:4:l 4096:32:4:l Anagram L1sepL2sep 1.186900773 86.435 102.5897683

2253 1024:32:4:l 4096:32:4:r Anagram L1sepL2sep 1.189219864 86.43 102.7842728

2254 1024:32:4:l 8192:32:2:f Anagram L1sepL2sep 1.18693591 86.1325 102.2337573

2255 1024:32:4:l 8192:32:2:l Anagram L1sepL2sep 1.186971048 86.135 102.2397512

2256 1024:32:4:l 8192:32:2:r Anagram L1sepL2sep 1.18865766 86.13 102.3790843

2257 1024:32:4:r 16384:32:1:f Anagram L1sepL2sep 1.187661516 85.9775 102.112168

2258 1024:32:4:r 16384:32:1:l Anagram L1sepL2sep 1.187661516 85.98 102.1151371

2259 1024:32:4:r 16384:32:1:r Anagram L1sepL2sep 1.187673843 85.975 102.1102587

2260 1024:32:4:r 2048:32:8:f Anagram L1sepL2sep 1.186883457 87.0275 103.2915

2261 1024:32:4:r 2048:32:8:l Anagram L1sepL2sep 1.186918823 87.03 103.2975452

2262 1024:32:4:r 2048:32:8:r Anagram L1sepL2sep 1.197643841 87.025 104.2249553

2263 1024:32:4:r 4096:32:4:f Anagram L1sepL2sep 1.186883457 86.4275 102.5793699

2264 1024:32:4:r 4096:32:4:l Anagram L1sepL2sep 1.187060288 86.43 102.5976207

2265 1024:32:4:r 4096:32:4:r Anagram L1sepL2sep 1.192723119 86.425 103.0810956

2266 1024:32:4:r 8192:32:2:f Anagram L1sepL2sep 1.187024922 86.1275 102.235489

2267 1024:32:4:r 8192:32:2:l Anagram L1sepL2sep 1.18723712 86.13 102.2567331

2268 1024:32:4:r 8192:32:2:r Anagram L1sepL2sep 1.188268897 86.125 102.3396587

2269 1024:64:2:f 1024:64:8:f Anagram L1sepL2sep 1.09384748 86.73 94.86939198

2270 1024:64:2:f 1024:64:8:l Anagram L1sepL2sep 1.09384748 86.7325 94.8721266

2271 1024:64:2:f 1024:64:8:r Anagram L1sepL2sep 1.095455015 86.7275 95.00607477

2272 1024:64:2:f 2048:64:4:f Anagram L1sepL2sep 1.093865342 86.13 94.2146219

2273 1024:64:2:f 2048:64:4:l Anagram L1sepL2sep 1.09384748 86.1325 94.21581811

2274 1024:64:2:f 2048:64:4:r Anagram L1sepL2sep 1.0952764 86.1275 94.33341811

2275 1024:64:2:f 4096:64:2:f Anagram L1sepL2sep 1.093936788 85.83 93.89259451

2276 1024:64:2:f 4096:64:2:l Anagram L1sepL2sep 1.093918926 85.8325 93.89379625

2277 1024:64:2:f 4096:64:2:r Anagram L1sepL2sep 1.094883447 85.8275 93.97110904

2278 1024:64:2:f 8192:64:1:f Anagram L1sepL2sep 1.094258295 85.68 93.75605069

2279 1024:64:2:f 8192:64:1:l Anagram L1sepL2sep 1.094258295 85.6825 93.75878634

2280 1024:64:2:f 8192:64:1:r Anagram L1sepL2sep 1.094258295 85.6775 93.75331505

2281 1024:64:2:l 1024:64:8:f Anagram L1sepL2sep 1.093847587 86.7325 94.87213586

2282 1024:64:2:l 1024:64:8:l Anagram L1sepL2sep 1.093847587 86.735 94.87487047

2283 1024:64:2:l 1024:64:8:r Anagram L1sepL2sep 1.095390224 86.73 95.00319415

2284 1024:64:2:l 2048:64:4:f Anagram L1sepL2sep 1.093847587 86.1325 94.2158273

2285 1024:64:2:l 2048:64:4:l Anagram L1sepL2sep 1.093847587 86.135 94.21856192

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71

2286 1024:64:2:l 2048:64:4:r Anagram L1sepL2sep 1.095195178 86.13 94.32916069

2287 1024:64:2:l 4096:64:2:f Anagram L1sepL2sep 1.09388305 85.8325 93.8907169

2288 1024:64:2:l 4096:64:2:l Anagram L1sepL2sep 1.093900782 85.835 93.89497359

2289 1024:64:2:l 4096:64:2:r Anagram L1sepL2sep 1.09473416 85.83 93.96103297

2290 1024:64:2:l 8192:64:1:f Anagram L1sepL2sep 1.094113559 85.6825 93.74638503

2291 1024:64:2:l 8192:64:1:l Anagram L1sepL2sep 1.094113559 85.685 93.74912031

2292 1024:64:2:l 8192:64:1:r Anagram L1sepL2sep 1.094113559 85.68 93.74364974

2293 1024:64:2:r 1024:64:8:f Anagram L1sepL2sep 1.094110615 86.7275 94.8894784

2294 1024:64:2:r 1024:64:8:l Anagram L1sepL2sep 1.094110615 86.73 94.89221368

2295 1024:64:2:r 1024:64:8:r Anagram L1sepL2sep 1.098171634 86.725 95.23893493

2296 1024:64:2:r 2048:64:4:f Anagram L1sepL2sep 1.094128557 86.1275 94.23455731

2297 1024:64:2:r 2048:64:4:l Anagram L1sepL2sep 1.094110615 86.13 94.23574731

2298 1024:64:2:r 2048:64:4:r Anagram L1sepL2sep 1.096265543 86.125 94.41586992

2299 1024:64:2:r 4096:64:2:f Anagram L1sepL2sep 1.094200324 85.8275 93.91247833

2300 1024:64:2:r 4096:64:2:l Anagram L1sepL2sep 1.09425415 85.83 93.91983366

2301 1024:64:2:r 4096:64:2:r Anagram L1sepL2sep 1.094241818 85.825 93.91330401

2302 1024:64:2:r 8192:64:1:f Anagram L1sepL2sep 1.094577101 85.6775 93.7806296

2303 1024:64:2:r 8192:64:1:l Anagram L1sepL2sep 1.094577101 85.68 93.78336604

2304 1024:64:2:r 8192:64:1:r Anagram L1sepL2sep 1.094533711 85.675 93.77417566

2305 2048:32:2:f 16384:32:1:f GO L1sepL2sep 1.026291273 85.68 87.93263627

2306 2048:32:2:f 16384:32:1:l GO L1sepL2sep 1.026291273 85.6825 87.935202

2307 2048:32:2:f 16384:32:1:r GO L1sepL2sep 1.026291273 85.6775 87.93007054

2308 2048:32:2:f 2048:32:8:f GO L1sepL2sep 1.025175196 86.73 88.91344472

2309 2048:32:2:f 2048:32:8:l GO L1sepL2sep 1.025175196 86.7325 88.91600766

2310 2048:32:2:f 2048:32:8:r GO L1sepL2sep 1.02499894 86.7275 88.89559554

2311 2048:32:2:f 4096:32:4:f GO L1sepL2sep 1.025175196 86.13 88.2983396

2312 2048:32:2:f 4096:32:4:l GO L1sepL2sep 1.025175196 86.1325 88.30090254

2313 2048:32:2:f 4096:32:4:r GO L1sepL2sep 1.024979688 86.1275 88.27893804

2314 2048:32:2:f 8192:32:2:f GO L1sepL2sep 1.025233731 85.83 87.99581115

2315 2048:32:2:f 8192:32:2:l GO L1sepL2sep 1.025225926 85.8325 87.99770433

2316 2048:32:2:f 8192:32:2:r GO L1sepL2sep 1.025061962 85.8275 87.97850555

2317 2048:32:2:l 16384:32:1:f GO L1sepL2sep 1.025415653 85.6825 87.86017673

2318 2048:32:2:l 16384:32:1:l GO L1sepL2sep 1.025415653 85.685 87.86274027

2319 2048:32:2:l 16384:32:1:r GO L1sepL2sep 1.025415653 85.68 87.85761319

2320 2048:32:2:l 2048:32:8:f GO L1sepL2sep 1.024344587 86.7325 88.84396689

2321 2048:32:2:l 2048:32:8:l GO L1sepL2sep 1.024344587 86.735 88.84652775

2322 2048:32:2:l 2048:32:8:r GO L1sepL2sep 1.024168526 86.73 88.82613628

2323 2048:32:2:l 4096:32:4:f GO L1sepL2sep 1.024344587 86.1325 88.22936014

2324 2048:32:2:l 4096:32:4:l GO L1sepL2sep 1.024344587 86.135 88.231921

2325 2048:32:2:l 4096:32:4:r GO L1sepL2sep 1.024138313 86.13 88.20903294

2326 2048:32:2:l 8192:32:2:f GO L1sepL2sep 1.024402094 85.8325 87.92699273

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72

2327 2048:32:2:l 8192:32:2:l GO L1sepL2sep 1.024394906 85.835 87.92893672

2328 2048:32:2:l 8192:32:2:r GO L1sepL2sep 1.024219155 85.83 87.90873011

2329 2048:32:2:r 16384:32:1:f GO L1sepL2sep 1.025575647 85.6775 87.86875753

2330 2048:32:2:r 16384:32:1:l GO L1sepL2sep 1.025575647 85.68 87.87132147

2331 2048:32:2:r 16384:32:1:r GO L1sepL2sep 1.025563553 85.675 87.86515738

2332 2048:32:2:r 2048:32:8:f GO L1sepL2sep 1.024573134 86.7275 88.85866644

2333 2048:32:2:r 2048:32:8:l GO L1sepL2sep 1.024573134 86.73 88.86122788

2334 2048:32:2:r 2048:32:8:r GO L1sepL2sep 1.024665896 86.725 88.86414982

2335 2048:32:2:r 4096:32:4:f GO L1sepL2sep 1.024573134 86.1275 88.24392256

2336 2048:32:2:r 4096:32:4:l GO L1sepL2sep 1.024573134 86.13 88.246484

2337 2048:32:2:r 4096:32:4:r GO L1sepL2sep 1.024508342 86.125 88.23578096

2338 2048:32:2:r 8192:32:2:f GO L1sepL2sep 1.024635065 85.8275 87.94186604

2339 2048:32:2:r 8192:32:2:l GO L1sepL2sep 1.024638936 85.83 87.94475985

2340 2048:32:2:r 8192:32:2:r GO L1sepL2sep 1.024497811 85.825 87.92752467

2341 2048:64:1:f 1024:64:8:f GO L1sepL2sep 1.035576669 86.58 89.66022799

2342 2048:64:1:f 1024:64:8:l GO L1sepL2sep 1.035576669 86.5825 89.66281694

2343 2048:64:1:f 1024:64:8:r GO L1sepL2sep 1.035484412 86.5775 89.64965167

2344 2048:64:1:f 2048:64:4:f GO L1sepL2sep 1.035576669 85.98 89.03888199

2345 2048:64:1:f 2048:64:4:l GO L1sepL2sep 1.035576669 85.9825 89.04147093

2346 2048:64:1:f 2048:64:4:r GO L1sepL2sep 1.035494794 85.9775 89.02925367

2347 2048:64:1:f 4096:64:2:f GO L1sepL2sep 1.03565276 85.68 88.73472851

2348 2048:64:1:f 4096:64:2:l GO L1sepL2sep 1.035627397 85.6825 88.73514441

2349 2048:64:1:f 4096:64:2:r GO L1sepL2sep 1.03558416 85.6775 88.72626184

2350 2048:64:1:f 8192:64:1:f GO L1sepL2sep 1.036692678 85.53 88.66832474

2351 2048:64:1:f 8192:64:1:l GO L1sepL2sep 1.036692678 85.5325 88.67091648

2352 2048:64:1:f 8192:64:1:r GO L1sepL2sep 1.036692678 85.5275 88.66573301

2353 2048:64:1:l 1024:64:8:f GO L1sepL2sep 1.035576669 86.5825 89.66281694

2354 2048:64:1:l 1024:64:8:l GO L1sepL2sep 1.035576669 86.585 89.66540588

2355 2048:64:1:l 1024:64:8:r GO L1sepL2sep 1.035484412 86.58 89.65224038

2356 2048:64:1:l 2048:64:4:f GO L1sepL2sep 1.035576669 85.9825 89.04147093

2357 2048:64:1:l 2048:64:4:l GO L1sepL2sep 1.035576669 85.985 89.04405988

2358 2048:64:1:l 2048:64:4:r GO L1sepL2sep 1.035494794 85.98 89.03184241

2359 2048:64:1:l 4096:64:2:f GO L1sepL2sep 1.03565276 85.6825 88.73731765

2360 2048:64:1:l 4096:64:2:l GO L1sepL2sep 1.035627397 85.685 88.73773348

2361 2048:64:1:l 4096:64:2:r GO L1sepL2sep 1.03558416 85.68 88.7288508

2362 2048:64:1:l 8192:64:1:f GO L1sepL2sep 1.036692678 85.5325 88.67091648

2363 2048:64:1:l 8192:64:1:l GO L1sepL2sep 1.036692678 85.535 88.67350821

2364 2048:64:1:l 8192:64:1:r GO L1sepL2sep 1.036692678 85.53 88.66832474

2365 2048:64:1:r 1024:64:8:f GO L1sepL2sep 1.035576669 86.5775 89.65763905

2366 2048:64:1:r 1024:64:8:l GO L1sepL2sep 1.035576669 86.58 89.66022799

2367 2048:64:1:r 1024:64:8:r GO L1sepL2sep 1.035491903 86.575 89.64771147

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73

2368 2048:64:1:r 2048:64:4:f GO L1sepL2sep 1.035576669 85.9775 89.03629305

2369 2048:64:1:r 2048:64:4:l GO L1sepL2sep 1.035576669 85.98 89.03888199

2370 2048:64:1:r 2048:64:4:r GO L1sepL2sep 1.035494794 85.975 89.02666493

2371 2048:64:1:r 4096:64:2:f GO L1sepL2sep 1.03565276 85.6775 88.73213938

2372 2048:64:1:r 4096:64:2:l GO L1sepL2sep 1.035627397 85.68 88.73255534

2373 2048:64:1:r 4096:64:2:r GO L1sepL2sep 1.03558416 85.675 88.72367288

2374 2048:64:1:r 8192:64:1:f GO L1sepL2sep 1.036692678 85.5275 88.66573301

2375 2048:64:1:r 8192:64:1:l GO L1sepL2sep 1.036692678 85.53 88.66832474

2376 2048:64:1:r 8192:64:1:r GO L1sepL2sep 1.036692678 85.525 88.66314128

2377 256:64:8:f 1024:64:8:f GO L1sepL2sep 1.01488071 87.63 88.9339966

2378 256:64:8:f 1024:64:8:l GO L1sepL2sep 1.01488071 87.6325 88.9365338

2379 256:64:8:f 1024:64:8:r GO L1sepL2sep 1.014852483 87.6275 88.92898596

2380 256:64:8:f 2048:64:4:f GO L1sepL2sep 1.01488071 87.03 88.32506817

2381 256:64:8:f 2048:64:4:l GO L1sepL2sep 1.01488071 87.0325 88.32760537

2382 256:64:8:f 2048:64:4:r GO L1sepL2sep 1.014828612 87.0275 88.317997

2383 256:64:8:f 4096:64:2:f GO L1sepL2sep 1.014950526 86.73 88.02665913

2384 256:64:8:f 4096:64:2:l GO L1sepL2sep 1.014954405 86.7325 88.02953292

2385 256:64:8:f 4096:64:2:r GO L1sepL2sep 1.014890071 86.7275 88.01887867

2386 256:64:8:f 8192:64:1:f GO L1sepL2sep 1.015844564 86.58 87.95182234

2387 256:64:8:f 8192:64:1:l GO L1sepL2sep 1.015844564 86.5825 87.95436195

2388 256:64:8:f 8192:64:1:r GO L1sepL2sep 1.015844564 86.5775 87.94928273

2389 256:64:8:l 1024:64:8:f GO L1sepL2sep 1.014045961 87.6325 88.86338266

2390 256:64:8:l 1024:64:8:l GO L1sepL2sep 1.014045961 87.635 88.86591777

2391 256:64:8:l 1024:64:8:r GO L1sepL2sep 1.014009801 87.63 88.85767884

2392 256:64:8:l 2048:64:4:f GO L1sepL2sep 1.014045961 87.0325 88.25495508

2393 256:64:8:l 2048:64:4:l GO L1sepL2sep 1.014045961 87.035 88.25749019

2394 256:64:8:l 2048:64:4:r GO L1sepL2sep 1.013994367 87.03 88.24792975

2395 256:64:8:l 4096:64:2:f GO L1sepL2sep 1.014113762 86.7325 87.9566219

2396 256:64:8:l 4096:64:2:l GO L1sepL2sep 1.014121092 86.735 87.95979295

2397 256:64:8:l 4096:64:2:r GO L1sepL2sep 1.014056603 86.73 87.94912916

2398 256:64:8:l 8192:64:1:f GO L1sepL2sep 1.01499152 86.5825 87.88050324

2399 256:64:8:l 8192:64:1:l GO L1sepL2sep 1.01499152 86.585 87.88304072

2400 256:64:8:l 8192:64:1:r GO L1sepL2sep 1.01499152 86.58 87.87796576

2401 256:64:8:r 1024:64:8:f GO L1sepL2sep 1.013686979 87.6275 88.82685572

2402 256:64:8:r 1024:64:8:l GO L1sepL2sep 1.013686979 87.63 88.82938993

2403 256:64:8:r 1024:64:8:r GO L1sepL2sep 1.013845492 87.625 88.83821126

2404 256:64:8:r 2048:64:4:f GO L1sepL2sep 1.013686979 87.0275 88.21864353

2405 256:64:8:r 2048:64:4:l GO L1sepL2sep 1.013686979 87.03 88.22117775

2406 256:64:8:r 2048:64:4:r GO L1sepL2sep 1.01374918 87.025 88.22152243

2407 256:64:8:r 4096:64:2:f GO L1sepL2sep 1.013754749 86.7275 87.92041496

2408 256:64:8:r 4096:64:2:l GO L1sepL2sep 1.013758621 86.73 87.92328521

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74

2409 256:64:8:r 4096:64:2:r GO L1sepL2sep 1.013734641 86.725 87.91613676

2410 256:64:8:r 8192:64:1:f GO L1sepL2sep 1.014521517 86.5775 87.83473666

2411 256:64:8:r 8192:64:1:l GO L1sepL2sep 1.014521517 86.58 87.83727297

2412 256:64:8:r 8192:64:1:r GO L1sepL2sep 1.014519687 86.575 87.83204191

2413 4096:32:1:f 16384:32:1:f GO L1sepL2sep 1.044168218 85.53 89.30770771

2414 4096:32:1:f 16384:32:1:l GO L1sepL2sep 1.044168218 85.5325 89.31031813

2415 4096:32:1:f 16384:32:1:r GO L1sepL2sep 1.044168218 85.5275 89.30509728

2416 4096:32:1:f 2048:32:8:f GO L1sepL2sep 1.042947735 86.58 90.29841493

2417 4096:32:1:f 2048:32:8:l GO L1sepL2sep 1.042947735 86.5825 90.3010223

2418 4096:32:1:f 2048:32:8:r GO L1sepL2sep 1.042739983 86.5775 90.27782091

2419 4096:32:1:f 4096:32:4:f GO L1sepL2sep 1.042947735 85.98 89.67264629

2420 4096:32:1:f 4096:32:4:l GO L1sepL2sep 1.042947735 85.9825 89.67525365

2421 4096:32:1:f 4096:32:4:r GO L1sepL2sep 1.042730611 85.9775 89.65137108

2422 4096:32:1:f 8192:32:2:f GO L1sepL2sep 1.043013118 85.68 89.36536398

2423 4096:32:1:f 8192:32:2:l GO L1sepL2sep 1.043013118 85.6825 89.36797151

2424 4096:32:1:f 8192:32:2:r GO L1sepL2sep 1.04283021 85.6775 89.34708529

2425 4096:32:1:l 16384:32:1:f GO L1sepL2sep 1.044168218 85.5325 89.31031813

2426 4096:32:1:l 16384:32:1:l GO L1sepL2sep 1.044168218 85.535 89.31292855

2427 4096:32:1:l 16384:32:1:r GO L1sepL2sep 1.044168218 85.53 89.30770771

2428 4096:32:1:l 2048:32:8:f GO L1sepL2sep 1.042947735 86.5825 90.3010223

2429 4096:32:1:l 2048:32:8:l GO L1sepL2sep 1.042947735 86.585 90.30362967

2430 4096:32:1:l 2048:32:8:r GO L1sepL2sep 1.042739983 86.58 90.28042776

2431 4096:32:1:l 4096:32:4:f GO L1sepL2sep 1.042947735 85.9825 89.67525365

2432 4096:32:1:l 4096:32:4:l GO L1sepL2sep 1.042947735 85.985 89.67786102

2433 4096:32:1:l 4096:32:4:r GO L1sepL2sep 1.042730611 85.98 89.6539779

2434 4096:32:1:l 8192:32:2:f GO L1sepL2sep 1.043013118 85.6825 89.36797151

2435 4096:32:1:l 8192:32:2:l GO L1sepL2sep 1.043013118 85.685 89.37057905

2436 4096:32:1:l 8192:32:2:r GO L1sepL2sep 1.04283021 85.68 89.34969236

2437 4096:32:1:r 16384:32:1:f GO L1sepL2sep 1.044168218 85.5275 89.30509728

2438 4096:32:1:r 16384:32:1:l GO L1sepL2sep 1.044168218 85.53 89.30770771

2439 4096:32:1:r 16384:32:1:r GO L1sepL2sep 1.044168218 85.525 89.30248686

2440 4096:32:1:r 2048:32:8:f GO L1sepL2sep 1.042947735 86.5775 90.29580756

2441 4096:32:1:r 2048:32:8:l GO L1sepL2sep 1.042947735 86.58 90.29841493

2442 4096:32:1:r 2048:32:8:r GO L1sepL2sep 1.042761778 86.575 90.2771009

2443 4096:32:1:r 4096:32:4:f GO L1sepL2sep 1.042947735 85.9775 89.67003892

2444 4096:32:1:r 4096:32:4:l GO L1sepL2sep 1.042947735 85.98 89.67264629

2445 4096:32:1:r 4096:32:4:r GO L1sepL2sep 1.042743851 85.975 89.64990259

2446 4096:32:1:r 8192:32:2:f GO L1sepL2sep 1.043013118 85.6775 89.36275645

2447 4096:32:1:r 8192:32:2:l GO L1sepL2sep 1.043013118 85.68 89.36536398

2448 4096:32:1:r 8192:32:2:r GO L1sepL2sep 1.04283021 85.675 89.34447821

2449 512:32:8:f 16384:32:1:f GO L1sepL2sep 1.028108331 86.58 89.01361928

Page 75: Cache Design for an Alpha Microprocessor

75

2450 512:32:8:f 16384:32:1:l GO L1sepL2sep 1.028108331 86.5825 89.01618955

2451 512:32:8:f 16384:32:1:r GO L1sepL2sep 1.028108331 86.5775 89.01104901

2452 512:32:8:f 2048:32:8:f GO L1sepL2sep 1.027106678 87.63 90.00535819

2453 512:32:8:f 2048:32:8:l GO L1sepL2sep 1.027106678 87.6325 90.00792596

2454 512:32:8:f 2048:32:8:r GO L1sepL2sep 1.026969721 87.6275 89.9907892

2455 512:32:8:f 4096:32:4:f GO L1sepL2sep 1.027106678 87.03 89.38909418

2456 512:32:8:f 4096:32:4:l GO L1sepL2sep 1.027106678 87.0325 89.39166195

2457 512:32:8:f 4096:32:4:r GO L1sepL2sep 1.026951299 87.0275 89.37300417

2458 512:32:8:f 8192:32:2:f GO L1sepL2sep 1.027164098 86.73 89.08594218

2459 512:32:8:f 8192:32:2:l GO L1sepL2sep 1.027167288 86.7325 89.08878677

2460 512:32:8:f 8192:32:2:r GO L1sepL2sep 1.026995853 86.7275 89.06878282

2461 512:32:8:l 16384:32:1:f GO L1sepL2sep 1.02662502 86.5825 88.88776083

2462 512:32:8:l 16384:32:1:l GO L1sepL2sep 1.02662502 86.585 88.89032739

2463 512:32:8:l 16384:32:1:r GO L1sepL2sep 1.02662502 86.58 88.88519426

2464 512:32:8:l 2048:32:8:f GO L1sepL2sep 1.025666526 87.6325 89.88172182

2465 512:32:8:l 2048:32:8:l GO L1sepL2sep 1.025666526 87.635 89.88428599

2466 512:32:8:l 2048:32:8:r GO L1sepL2sep 1.025538963 87.63 89.86797932

2467 512:32:8:l 4096:32:4:f GO L1sepL2sep 1.025666526 87.0325 89.26632191

2468 512:32:8:l 4096:32:4:l GO L1sepL2sep 1.025666526 87.035 89.26888607

2469 512:32:8:l 4096:32:4:r GO L1sepL2sep 1.025521765 87.03 89.25115917

2470 512:32:8:l 8192:32:2:f GO L1sepL2sep 1.025723259 86.7325 88.96354257

2471 512:32:8:l 8192:32:2:l GO L1sepL2sep 1.025726245 86.735 88.96636587

2472 512:32:8:l 8192:32:2:r GO L1sepL2sep 1.0255359 86.73 88.94472857

2473 512:32:8:r 16384:32:1:f GO L1sepL2sep 1.025303479 86.5775 88.76821199

2474 512:32:8:r 16384:32:1:l GO L1sepL2sep 1.025303479 86.58 88.77077525

2475 512:32:8:r 16384:32:1:r GO L1sepL2sep 1.025306624 86.575 88.76592099

2476 512:32:8:r 2048:32:8:f GO L1sepL2sep 1.024472597 87.6275 89.77197249

2477 512:32:8:r 2048:32:8:l GO L1sepL2sep 1.024472597 87.63 89.77453367

2478 512:32:8:r 2048:32:8:r GO L1sepL2sep 1.024748954 87.625 89.79362709

2479 512:32:8:r 4096:32:4:f GO L1sepL2sep 1.024472597 87.0275 89.15728893

2480 512:32:8:r 4096:32:4:l GO L1sepL2sep 1.024475523 87.03 89.16010473

2481 512:32:8:r 4096:32:4:r GO L1sepL2sep 1.024536907 87.025 89.16032432

2482 512:32:8:r 8192:32:2:f GO L1sepL2sep 1.024528184 86.7275 88.85476809

2483 512:32:8:r 8192:32:2:l GO L1sepL2sep 1.024539887 86.73 88.85834437

2484 512:32:8:r 8192:32:2:r GO L1sepL2sep 1.024448213 86.725 88.84527131

2485 512:64:4:f 1024:64:8:f GO L1sepL2sep 1.014523486 87.03 88.29397902

2486 512:64:4:f 1024:64:8:l GO L1sepL2sep 1.014523486 87.0325 88.29651533

2487 512:64:4:f 1024:64:8:r GO L1sepL2sep 1.014475798 87.0275 88.28729248

2488 512:64:4:f 2048:64:4:f GO L1sepL2sep 1.014523486 86.43 87.68526493

2489 512:64:4:f 2048:64:4:l GO L1sepL2sep 1.014523486 86.4325 87.68780124

2490 512:64:4:f 2048:64:4:r GO L1sepL2sep 1.014468114 86.4275 87.67794296

Page 76: Cache Design for an Alpha Microprocessor

76

2491 512:64:4:f 4096:64:2:f GO L1sepL2sep 1.014591664 86.13 87.38677999

2492 512:64:4:f 4096:64:2:l GO L1sepL2sep 1.014598481 86.1325 87.3899037

2493 512:64:4:f 4096:64:2:r GO L1sepL2sep 1.014530593 86.1275 87.37898362

2494 512:64:4:f 8192:64:1:f GO L1sepL2sep 1.015521147 85.98 87.31450819

2495 512:64:4:f 8192:64:1:l GO L1sepL2sep 1.015521147 85.9825 87.31704699

2496 512:64:4:f 8192:64:1:r GO L1sepL2sep 1.015521147 85.9775 87.31196939

2497 512:64:4:l 1024:64:8:f GO L1sepL2sep 1.013682384 87.0325 88.22331206

2498 512:64:4:l 1024:64:8:l GO L1sepL2sep 1.013682384 87.035 88.22584627

2499 512:64:4:l 1024:64:8:r GO L1sepL2sep 1.013633941 87.03 88.21656192

2500 512:64:4:l 2048:64:4:f GO L1sepL2sep 1.013682384 86.4325 87.61510263

2501 512:64:4:l 2048:64:4:l GO L1sepL2sep 1.013682384 86.435 87.61763684

2502 512:64:4:l 2048:64:4:r GO L1sepL2sep 1.013631953 86.43 87.60820969

2503 512:64:4:l 4096:64:2:f GO L1sepL2sep 1.013746867 86.1325 87.31655202

2504 512:64:4:l 4096:64:2:l GO L1sepL2sep 1.013754927 86.135 87.31978067

2505 512:64:4:l 4096:64:2:r GO L1sepL2sep 1.013705875 86.13 87.31048706

2506 512:64:4:l 8192:64:1:f GO L1sepL2sep 1.014645602 85.9825 87.24176549

2507 512:64:4:l 8192:64:1:l GO L1sepL2sep 1.014645602 85.985 87.2443021

2508 512:64:4:l 8192:64:1:r GO L1sepL2sep 1.014645602 85.98 87.23922887

2509 512:64:4:r 1024:64:8:f GO L1sepL2sep 1.013681861 87.0275 88.2181982

2510 512:64:4:r 1024:64:8:l GO L1sepL2sep 1.013681861 87.03 88.2207324

2511 512:64:4:r 1024:64:8:r GO L1sepL2sep 1.013811687 87.025 88.22696206

2512 512:64:4:r 2048:64:4:f GO L1sepL2sep 1.013681861 86.4275 87.60998908

2513 512:64:4:r 2048:64:4:l GO L1sepL2sep 1.013681861 86.43 87.61252329

2514 512:64:4:r 2048:64:4:r GO L1sepL2sep 1.013734544 86.425 87.61200798

2515 512:64:4:r 4096:64:2:f GO L1sepL2sep 1.013747727 86.1275 87.31155733

2516 512:64:4:r 4096:64:2:l GO L1sepL2sep 1.013752118 86.13 87.3144699

2517 512:64:4:r 4096:64:2:r GO L1sepL2sep 1.013729689 86.125 87.30746949

2518 512:64:4:r 8192:64:1:f GO L1sepL2sep 1.014538109 85.9775 87.2274503

2519 512:64:4:r 8192:64:1:l GO L1sepL2sep 1.014538109 85.98 87.22998665

2520 512:64:4:r 8192:64:1:r GO L1sepL2sep 1.014545333 85.975 87.22553498

2521 1024:32:4:f 16384:32:1:f GO L1sepL2sep 1.027574875 85.98 88.35088778

2522 1024:32:4:f 16384:32:1:l GO L1sepL2sep 1.027574875 85.9825 88.35345672

2523 1024:32:4:f 16384:32:1:r GO L1sepL2sep 1.027574875 85.9775 88.34831884

2524 1024:32:4:f 2048:32:8:f GO L1sepL2sep 1.026505605 87.03 89.3367828

2525 1024:32:4:f 2048:32:8:l GO L1sepL2sep 1.026505605 87.0325 89.33934907

2526 1024:32:4:f 2048:32:8:r GO L1sepL2sep 1.026367881 87.0275 89.32223075

2527 1024:32:4:f 4096:32:4:f GO L1sepL2sep 1.026505605 86.43 88.72087944

2528 1024:32:4:f 4096:32:4:l GO L1sepL2sep 1.026505605 86.4325 88.7234457

2529 1024:32:4:f 4096:32:4:r GO L1sepL2sep 1.02634297 86.4275 88.70425701

2530 1024:32:4:f 8192:32:2:f GO L1sepL2sep 1.026563129 86.13 88.4178823

2531 1024:32:4:f 8192:32:2:l GO L1sepL2sep 1.026566513 86.1325 88.42074016

Page 77: Cache Design for an Alpha Microprocessor

77

2532 1024:32:4:f 8192:32:2:r GO L1sepL2sep 1.026386453 86.1275 88.40009927

2533 1024:32:4:l 16384:32:1:f GO L1sepL2sep 1.026080913 85.9825 88.22500209

2534 1024:32:4:l 16384:32:1:l GO L1sepL2sep 1.026080913 85.985 88.22756729

2535 1024:32:4:l 16384:32:1:r GO L1sepL2sep 1.026080913 85.98 88.22243689

2536 1024:32:4:l 2048:32:8:f GO L1sepL2sep 1.025068763 87.0325 89.21429708

2537 1024:32:4:l 2048:32:8:l GO L1sepL2sep 1.025068763 87.035 89.21685976

2538 1024:32:4:l 2048:32:8:r GO L1sepL2sep 1.024932425 87.03 89.19986899

2539 1024:32:4:l 4096:32:4:f GO L1sepL2sep 1.025068763 86.4325 88.59925583

2540 1024:32:4:l 4096:32:4:l GO L1sepL2sep 1.025068763 86.435 88.6018185

2541 1024:32:4:l 4096:32:4:r GO L1sepL2sep 1.024905502 86.43 88.58258253

2542 1024:32:4:l 8192:32:2:f GO L1sepL2sep 1.025120746 86.1325 88.29621267

2543 1024:32:4:l 8192:32:2:l GO L1sepL2sep 1.025123804 86.135 88.29903886

2544 1024:32:4:l 8192:32:2:r GO L1sepL2sep 1.024934018 86.13 88.27756696

2545 1024:32:4:r 16384:32:1:f GO L1sepL2sep 1.024755654 85.9775 88.10592925

2546 1024:32:4:r 16384:32:1:l GO L1sepL2sep 1.024755654 85.98 88.10849114

2547 1024:32:4:r 16384:32:1:r GO L1sepL2sep 1.024755959 85.975 88.10339362

2548 1024:32:4:r 2048:32:8:f GO L1sepL2sep 1.023866275 87.0275 89.10452221

2549 1024:32:4:r 2048:32:8:l GO L1sepL2sep 1.023869451 87.03 89.10735831

2550 1024:32:4:r 2048:32:8:r GO L1sepL2sep 1.024071791 87.025 89.11984765

2551 1024:32:4:r 4096:32:4:f GO L1sepL2sep 1.023869451 86.4275 88.49047697

2552 1024:32:4:r 4096:32:4:l GO L1sepL2sep 1.023869451 86.43 88.49303664

2553 1024:32:4:r 4096:32:4:r GO L1sepL2sep 1.023891411 86.425 88.48981522

2554 1024:32:4:r 8192:32:2:f GO L1sepL2sep 1.023923449 86.1275 88.18796685

2555 1024:32:4:r 8192:32:2:l GO L1sepL2sep 1.023932978 86.13 88.19134739

2556 1024:32:4:r 8192:32:2:r GO L1sepL2sep 1.023808909 86.125 88.17554232

2557 1024:64:2:f 1024:64:8:f GO L1sepL2sep 1.014392321 86.73 87.97824601

2558 1024:64:2:f 1024:64:8:l GO L1sepL2sep 1.014392321 86.7325 87.98078199

2559 1024:64:2:f 1024:64:8:r GO L1sepL2sep 1.014333954 86.7275 87.97064798

2560 1024:64:2:f 2048:64:4:f GO L1sepL2sep 1.014392321 86.13 87.36961061

2561 1024:64:2:f 2048:64:4:l GO L1sepL2sep 1.014392321 86.1325 87.37214659

2562 1024:64:2:f 2048:64:4:r GO L1sepL2sep 1.014319861 86.1275 87.36083381

2563 1024:64:2:f 4096:64:2:f GO L1sepL2sep 1.014470601 85.83 87.07201172

2564 1024:64:2:f 4096:64:2:l GO L1sepL2sep 1.014459419 85.8325 87.07358804

2565 1024:64:2:f 4096:64:2:r GO L1sepL2sep 1.014410065 85.8275 87.06427989

2566 1024:64:2:f 8192:64:1:f GO L1sepL2sep 1.015465881 85.68 87.00511668

2567 1024:64:2:f 8192:64:1:l GO L1sepL2sep 1.015465881 85.6825 87.00765535

2568 1024:64:2:f 8192:64:1:r GO L1sepL2sep 1.015465881 85.6775 87.00257802

2569 1024:64:2:l 1024:64:8:f GO L1sepL2sep 1.014156842 86.7325 87.9603583

2570 1024:64:2:l 1024:64:8:l GO L1sepL2sep 1.014156842 86.735 87.96289369

2571 1024:64:2:l 1024:64:8:r GO L1sepL2sep 1.014085776 86.73 87.95165932

2572 1024:64:2:l 2048:64:4:f GO L1sepL2sep 1.014156842 86.1325 87.35186419

Page 78: Cache Design for an Alpha Microprocessor

78

2573 1024:64:2:l 2048:64:4:l GO L1sepL2sep 1.014156842 86.135 87.35439958

2574 1024:64:2:l 2048:64:4:r GO L1sepL2sep 1.014087338 86.13 87.34334243

2575 1024:64:2:l 4096:64:2:f GO L1sepL2sep 1.014228327 85.8325 87.05375289

2576 1024:64:2:l 4096:64:2:l GO L1sepL2sep 1.014225774 85.835 87.05606932

2577 1024:64:2:l 4096:64:2:r GO L1sepL2sep 1.014173341 85.83 87.0464979

2578 1024:64:2:l 8192:64:1:f GO L1sepL2sep 1.015201036 85.6825 86.98496273

2579 1024:64:2:l 8192:64:1:l GO L1sepL2sep 1.015201036 85.685 86.98750074

2580 1024:64:2:l 8192:64:1:r GO L1sepL2sep 1.015201036 85.68 86.98242473

2581 1024:64:2:r 1024:64:8:f GO L1sepL2sep 1.014387958 86.7275 87.97533162

2582 1024:64:2:r 1024:64:8:l GO L1sepL2sep 1.014387958 86.73 87.97786759

2583 1024:64:2:r 1024:64:8:r GO L1sepL2sep 1.014460441 86.725 87.97908173

2584 1024:64:2:r 2048:64:4:f GO L1sepL2sep 1.014387958 86.1275 87.36669884

2585 1024:64:2:r 2048:64:4:l GO L1sepL2sep 1.014387958 86.13 87.36923481

2586 1024:64:2:r 2048:64:4:r GO L1sepL2sep 1.014389375 86.125 87.36428495

2587 1024:64:2:r 4096:64:2:f GO L1sepL2sep 1.014467377 85.8275 87.06919877

2588 1024:64:2:r 4096:64:2:l GO L1sepL2sep 1.01446454 85.83 87.07149149

2589 1024:64:2:r 4096:64:2:r GO L1sepL2sep 1.014427179 85.825 87.06321264

2590 1024:64:2:r 8192:64:1:f GO L1sepL2sep 1.015338146 85.6775 86.99163402

2591 1024:64:2:r 8192:64:1:l GO L1sepL2sep 1.015338146 85.68 86.99417237

2592 1024:64:2:r 8192:64:1:r GO L1sepL2sep 1.015351371 85.675 86.99022871