cache memory

Cache memory

Prof. Sin-Min Lee

Department of Computer Science

Problem

Implement the following state diagram using T Flip-Flop(s) and J-K Flip-Flop(s)

Number Of Flip-Flops Needed

Need 2 Flip-Flops 1 T Flip-Flop 2 JK Flip-Flop

Steps To Solve The Problem

Step 1 – Create state tableStep 2 – K-Maps for QA

+ and QB+

Step 3 – K-Maps for T and JK Flip-FlopsStep 4 – Draw Flip-Flop diagram

State Table

Derived directly from the state diagram:

K-Maps for QA+ and QB

+

QA+

QB+

JK Truth Table

Let’s revisit JK Flip-Flops:

T Truth Table

Let’s revisit T Flip-Flops:

K-Map for T

T = QA’QB

K-Map for J and K

J

KJ = XQA’+ X’ QA

K = X

Draw Flip-Flop Diagram

Two Basic Types of Memory

RAM (Random Access Memory) Used to store programs and

data that computer needs when executing programs

Volatile and loses information once power is turned off

2 Basic Types of MemoryROM (Read-Only Memory)

Stores critical information necessary to operate the system, such as program necessary to boot computer

Not volatile and always retains its data

Also embedded in systems where programming does not need to change

Memory Hierarchy

Hierarchal Memory Approach in which computer systems use

combination of memory types to provide best performance at best cost

Basic types that constitute hierarchal memory system include registers, cache, main memory and secondary memory

Memory Hierarchy

Today’s computers each have small amount of very high-speed memory, called cache where data from frequently used memory locations may be temporarily stored

Cache is connected to main memory, which is typically medium-speed memory

Main memory is complemented by secondary memory, composed of hard disk and various removable media

The Memory Hierarchy

Cache Memory

Physical memory is slow (more than 30 times slower than processor)

Cache memory uses SRAM chips. Much faster Much expensive Situated closest to the processor

Can be arranged hierarchically L1 cache is incorporated into processor L2 cache is outside

Cache Memory- Three LevelsArchitecture

Address Pointer

MemoryMulti-

Gigabytes

Large and Slow160 X

16XL3 CacheMemory

Cache ControlLogic

L2 CacheMemory

L1 CacheMemory

2X 8X

16 Megabytes128 Kilobytes32 Kilobytes

2 Gigahertz Clock

Featuring Really Non-Deterministic Execution

Cache (2) Every address reference goes first to the cache;

if the desired address is not here, then we have a cache miss; The contents are fetched from main memory into the indicated CPU register and the

content is also saved into the cache memory If the desired data is in the cache, then we have a cache hit

The desired data is brought from the cache, at very high speed (low access time)

Most software exhibits temporal locality of access, meaning that it is likely that same address will be used again soon, and if so, the address will be found in the cache

Transfers between main memory and cache occur at granularity of cache lines or cache blocks, around 32 or 64 bytes (rather than bytes or processor words). Burst transfers of this kind receive hardware support and exploit spatial locality of access to the cache (future access are often to address near to the previous one)

Where can a block be placed in Cache? (1)

Our cache has eight block frames and the main memory has 32 blocks

Current CPUs

Cache Performance

Cache hits and cache misses.

Hit ratio is the percentage of memory accesses that are served from the cache

Average memory access time

TM = h TC + (1- h)TP Tc = 10 ns

Tp = 60 ns

Associative Cache Access order

A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 V0 G3 C2 H7 I6 A0 B0

Tc = 10 ns

Tp = 60 ns

FIFO

h = 0.389

TM = 40.56 ns

Direct-Mapped Cache Access order


Tc = 10 ns

Tp = 60 ns

h = 0.167

TM = 50.67 ns

2-Way Set Associative Cache Access order


Tc = 10 ns

Tp = 60 ns

LRU

h = 0.31389

TM = 40.56 ns

Associative Cache(FIFO Replacement Policy)

Data A B C A D B E F A C D B G C H I A B

CACHE

A A A A A A A A A A A A A A A I I I

B B B B B B B B B B B B B B B A A

C C C C C C C C C C C C C C C B

D D D D D D D D D D D D D D

E E E E E E E E E E E E

F F F F F F F F F F F

G G G G G G

H H H H

Hit? * * * * * * *

Hit ratio = 7/18Hit ratio = 7/18

A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0 G3 C2 H7 I6 A0 B0

Two-way set associative cache(LRU Replacement Policy)




C

A

C

H

E

0 A-0 A-1 A-1 A-0 A-0 A-1 E-0 E-0 E-1 E-1 E-1 B-0 B-0 B-0 B-0 B-0 B-1 B-0

0 B-0 B-0 B-1 B-1 B-0 B-1 B-1 A-0 A-0 A-0 A-1 A-1 A-1 A-1 A-1 A-0 A-1

1 D-0 D-0 D-0 D-1 D-1 D-1 D-0 D-0 D-0 D-0 D-0 D-0 D-0 D-0

1 F-0 F-0 F-0 F-1 F-1 F-1 F-1 F-1 F-1 F-1 F-1

2 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-1 C-1 C-1

2 I-0 I-0 I-0

3 G-0 G-0 G-1 G-1 G-1 G-1

3 H-0 H-0 H-0 H-0

Hit? * * * * * * *

Associative Cache with 2 byte line size (FIFO Replacement Policy)



A and J; B and D; C and G; E and F; and I and HA and J; B and D; C and G; E and F; and I and H


C

A

C

H

E

A A A A A A A A A A A A A A I I I I

J J J J J J J J J J J J J J H H H H

B B B B B B B B B B B B B B B A A

D D D D D D D D D D D D D D D J J

C C C C C C C C C C C C C C C B

G G G G G G G G G G G G G G G D

E E E E E E E E E E E E

F F F F F F F F F F F F

Hit? * * * * * * * * * * *

Direct-mapped Cachewith line size of 2 bytes

Hit ratio 7/18Hit ratio 7/18


CACHE

0 A B B A B B B B A A B B B B B B A B

1 J D D J D D D D J J D D D D D D J D

2 C C C C C C C C C C C C C C C C

3 G G G G G G G G G G G G G G G G

4 E E E E E E E E E E E E

5 F F F F F F F F F F F F

6 I I I I

7 H H H H

Hit? * * * * * * *



Two-way set Associative Cachewith line size of 2 bytes



C

A

C

H

E

0 A-0 A-1 A-1 A-0 A-1 A-1 E-0 E-0 E-1 B-0 B-0 B-0 B-0 B-0 B-0 B-0 B-1 B-0

1 J-0 J-1 J-1 J-0 J-1 J-1 F-0 F-0 F-1 D-0 D-0 D-0 D-0 D-0 D-0 D-0 D-1 D-0

0 B-0 B-0 B-1 B-0 B-0 B-1 B-1 A-0 A-0 A-1 A-1 A-1 A-1 A-1 A-1 A-0 A-1

1 D-0 D-0 D-1 D-0 D-0 D-1 D-1 J-0 J-0 J-1 J-1 J-1 J-1 J-1 J-1 J-0 J-1

2 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-0 C-1 C-1 C-1 C-1

3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 G-0 G-0 G-0 G-0 G-0 G-1 G-1 G-1 G-1

2 I-0 I-0 I-0 I-0

3 H-0 H-0 H-0 H-0

Hit? * * * * * * * * * * * *



cache memory

Documents