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DESCRIPTION
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EXPERIMENT NO. 1
OBJECTIVE: Simulate AND Gate using VHDL.
APPARATUS USED : Active-HDL 8.1 software
THEORY:
S.N
O
INP
UT
(x)
INP
UT
(y)
OUTP
UT (z)
1. 0 0 0
2. 0 1 0
3. 1 0 0
4. 1 1 1
VHDL CODE:
library ieee; use ieee.std_logic_1164.all;entity ANDB4 is
port(x:in std_logic ; y:in std_logic ;z:out std_logic );
end ANDB4; architecture groupB4 of ANDB4 is begin
process(x,y)begin if(x='1' and y='1')then
z<='1'; else z<='0';
end if; end process; end groupB4;
RESULT:
EXPERIMENT -2
OBJECTIVE: Simulate OR Gate using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.
NO
INP
UT
(x)
INP
UT
(y)
OUTP
UT (z)
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 1
VHDL CODE:
library ieee; use ieee.std_logic_1164.all; entity or2 is
port(x:in std_logic ; y:in std_logic ; z:out std_logic );
end or2; architecture groupb4 of or2 is begin
process(x,y) begin
if(x='0' or y='0')then z<='0';
else z<='1';
end if; end process; end groupb4;
RESULT:
EXPERIMENT 3
OBJECTIVE: Simulate NOT Gate using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.NO INPUT (x) OUTPUT(z)
1. 0 1
2. 1 0
VHDL CODE:
library ieee; use ieee.std_logic_1164.all; entity not2 is
port(x:in std_logic ;
z:out std_logic ); end not2; architecture groupb4 of not2 is begin
process(x) begin
if(x='0')then z<='1';
else z<='0';
end if; end process; end groupb4;
RESULT:
EXPERIMENT 4
OBJECTIVE: Simulate NAND Gate using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.N
O
INP
UT
(x)
INP
UT
(y)
OUTP
UT (z)
1. 0 0 1
2. 0 1 1
3. 1 0 1
4. 1 1 0
VHDL CODE:
library ieee; use ieee.std_logic_1164.all; entity nand2 is
port(x:in std_logic ; y:in std_logic ; z:out std_logic );
end nand2; architecture groupb4 of nand2 is begin
process(x,y) begin
if(x='1' and y='1')then z<='0';
else z<='1';
end if; end process; end groupb4;
RESULT:
EXPERIMENT 5
OBJECTIVE: Simulate NOR Gate using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.N
O
INPU
T (x)
INPU
T (y)
OUTPU
T (z)
1. 0 0 1
2. 0 1 0
3. 1 0 0
4. 1 1 0
VHDL CODE:
library ieee; use ieee.std_logic_1164.all; entity nor2 is
port(x:in std_logic ; y:in std_logic ; z:out std_logic );
end nor2; architecture groupb4 of nor2 is begin
process(x,y) begin
if(x='0' and y='0')then z<='1';
else z<='0';
end if; end process; end groupb4;
RESULT:
EXPERIMENT 6
OBJECTIVE: Simulate Ex-OR Gate using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.NO INPUT
(x)
INPUT
(y)
OUTPUT
(z)
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 0
VHDL CODE:
library ieee; use ieee.std_logic_1164.all; entity xor2 is
port(x:in std_logic ; y:in std_logic ; z:out std_logic );
end xor2; architecture groupb4 of xor2 is begin
process(x,y) begin
if(x=y)then z<='0';
else z<='1';
end if; end process; end groupb4;
RESULT:
EXPERIMENT 7
OBJECTIVE: Simulate Ex-NOR Gate using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.N
O
INPU
T (x)
INPU
T (y)
OUTPU
T (z)
1. 0 0 1
2. 0 1 0
3. 1 0 0
4. 1 1 1
VHDL CODE:
library ieee; use ieee.std_logic_1164.all; entity xnor2 is
port(x:in std_logic ; y:in std_logic ; z:out std_logic );
end xnor2; architecture groupb4 of xnor2 is begin
process(x,y) begin
if(x=y)then z<='1';
else z<='0';
end if; end process; end groupb4;
RESULT:
EXPERIMENT 8
OBJECTIVE: Simulate Half Adder Gate using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.N
O
INPUT(a
)
INPUT(b
)
SUM(s
)
CARRY(C
)
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 0 1
VHDL CODE:
library ieee; use ieee.std_logic_1164.all; entity ha2 is
port(x:in std_logic ; y:in std_logic ; z:out std_logic );
end ha2; architecture groupb4 of ha2 is begin
process(x,y) begin
if(x=y)then z<='0';
else z<='1';
end if; end process; end groupb4;
RESULT:
EXPERIMENT 9
OBJECTIVE: Simulate Full Adder Gate using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.N
O
INPUT(a) INPUT(b) INPUT(Cin) OUTPUT(S) OUTPUT(Cout)
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
VHDL CODE:
library ieee; use ieee.std_logic_1164.all; entity fa2 is
port(a:in std_logic ; b:in std_logic ; cin:in std_logic ; s:out std_logic ; cout:out std_logic);
end fa2; architecture groupb4 of fa2 is begin
s<= a xor b xor cin; cout<= (a and b) or (b and cin) or (cin and a);
end groupb4;`
RESULT:
EXPERIMENT 10
OBJECTIVE: Simulate Multiplexer using VHDL.
APPARATUS USED: Active-HDL 8.1 software
THEORY:
S.N
O
i1 i0 S OUTPUT
1. 0 0 0 0
2. 0 0 1 0
3. 0 1 0 1
4. 0 1 1 1
5 1 0 0 0
6 1 0 1 1
7 1 1 0 0
8 1 1 1 1
VHDL CODE:
library ieee;use ieee.std_logic_1164.all;entity mux is
port(i0: in STD_logic ;i1: in STD_logic ;s: in STD_logic ;o: out STD_logic ) ;
end mux;--}} End of automatically maintained sectionarchitecture mux of mux isbegin
o<=(i0 and(not s)) or (i1 and s);end mux;
RESULT:
