cadence’s solution for high-speed design

Cadence Design Systems, Inc.

Cadence’s Solution for High-Speed Design

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Agenda

What is High-Speed Design?Ideal High-Speed Design ProcessIntroduction to SPECCTRAQuest Power IntegritySPECCTRAQuest Demonstration

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R

The Day of “High-Speed” Has Come

“Pc-board designers, meanwhile, were retooling in 1999 for high-speed design. Signal integrity, once confined to high-end boards, has become everybody’s problem…”

Richard Goering, commenting on why the PCB layout market grew 20%while the IC layout market shrunk 30%, in EETimes 4/10/2000 page 70

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Welcome Networking!

HammerheadNetworks

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Agenda

What is High-Speed Design?Ideal High-Speed Design ProcessSPECCTRAQuest DemonstrationIntroduction to SPECCTRAQuest Power Integrity

NOWNOW

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What is “High-Speed” ?

Over 50 MHz

is “High-Speed”

“High-Speed” isn’t related

to frequency, it’s a function

of rise timesA net is “High-Speed” when itsround-trip delay is greaterthan twice its edge-speed

A signal is “High-Speed”

when it is faster than

anything you’ve designed before

“ High-S

peed”

occurs

when

skin e

ffect

and di

electr

ic

loss e

ffects

becom

e impo

rtant

Huh?

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Question: Which is a “High-Speed” Problem?

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Answer: They BOTH Are !!

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Definition of High-Speed

A net can be considered ‘High-Speed’ when you have to do something other

than simply connect it.

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High-Speed Design Involves 2 Things

Nets that are understood, and must be constrained

Nets that must be analyzed to be understood, and then

constrained

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Nets that are understood, and must be constrained

Nets that must be analyzed to be understood, and then constrained

SDRAM DIMM Layout

MODELS

DatasheetsFront-side Bus Simulation

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Most Tools Force You to Choose

Great

Simulator!

Analyze Constrain

GreatLayoutSystem!

Hmm...

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But for High-Speed You Need BOTH

All in ONE integrated & interactive

environment !

Analyze &ConstrainLet’s Go!

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SPECCTRAQuest: Integrated Constraint & Analysis

Model Development & Verification

Topology Entry &

Floorplanning

Constraint Driven Layout

Analyze

Constrain

SPECCTRAQuest helps you manage the process of High-Speed PCB development through both

Simulation Analysis & Constraint-Driven Layout tasks

A Complete Solution!

Pre-Route Sol’n-Space

Analysis Post Route Analysis

VerificationVerification

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Expanding Existing Process

PhysicalModel

Creation

Outline/Floorplan/Room Def/

SchematicModel

Creation

SchematicCreation

SCHEMATIC LAYOUT

To Final Verification

netlist

SI CleanRoute

constraints

Back-Annotate

Re-useTopology

FilesTopology

FilesTopology

Files

DeriveConstraints

ElectricalModel

Creation

HIGH-SPEED

yes

no

Post-RouteAnalysis

rules/criticals/

placement/ ACs

OK?

“IP” Library

PCBRouting

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Agenda

What is High-Speed Design?Ideal High-Speed Design ProcessSPECCTRAQuest DemonstrationIntroduction to SPECCTRAQuest Power Integrity

NOWNOW

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Ideal High-Speed Design Flow


Topology Entry &

Floorplanning


Analyze

Constrain

Development Process Flow






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Need Flexible Device Modeling Language (DML)

Today’s models come in many styles and formatsCadence DML can model all formats AND advanced behaviors

(for example, Merced / Itanium)

QuadModels

Version 2.1Version 3.2

IBIS

Package,Transmission Line,Connector, Cable

Models

SPICEModels

EBDModels

CadenceDML

can’t do “M” element today

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Topology Entry &

Floorplanning


Analyze

Constrain






Analysis


Analysis

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Pre-Route Solution Space Analysis Exhaustive “pre-layout” analysis of

manufacturing and design variances Used to define topologies, routing

rules and termination strategies Crosstalk and data pattern

dependencies may be taken into consideration

Swept-parameter analysis is used extensively to cover all combinations of conditions

Need flexibility to define any kind of simulation and any kind of measurement criteria

P1P1 P2P2

CS

P3P3 P4P4

Given:l Driver Strength = {F, T, S}l er = ernom +/- ertoll Z0 = Z0nom +/- Z0tol

What values of trace lengthallow the design to functionwithin limits?

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Output of pre-layout process is an electronic constraint file that can be used to guide the layout process

Analyze

Topology

Template

s

Derive and Save “Solution Space”Constrain

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Topology Entry &

Floorplanning


Analyze

Constrain




VerificationVerificationTopology Entry &

Floorplanning

Topology Entry &

Floorplanning

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High-Speed PCB Design Now Requires Both Electronic Inputs to Floorplanning & Routing

TopologyFiles

FinalNetlist

PCB Routing

PHYSICAL

TopologyFiles

FinalNetlist

PCB Routing

PCB Routing

PHYSICAL

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Topology Entry and Floorplanning

Design rules derived from solution space analysis guide the placement process

Constraint Manager spreadsheets plays a key role in guiding / evaluating component placement

Margin columns show difference between constraint and design value

– Fast feedback– Color-coded status

Topology

Templates

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Topology Entry &

Floorplanning


Analyze

Constrain




VerificationVerificationConstraint Driven Layout


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ConceptHDLCapture

ConceptHDLCapture

SPECCTRAQuestExploration

SPECCTRAQuestExploration

SPECCTRAQuestFloorplanning

SPECCTRAQuestFloorplanning

Allegro/APDLayout

Allegro/APDLayout

Constraint ManagerConstraint Manager

CaptureCaptureExplorationExploration FloorplanningFloorplanning LayoutLayout

GUIGUI GUIGUI GUIGUI GUIGUI

ConstraintsConstraints ConstraintsConstraints ConstraintsConstraints ConstraintsConstraints

? ??ePlanner/QUADSPICE

HyperLynx

ViewDraw ICX

DesignBoard Station

PADS

VeriBestArchitect ePlanner

Constraint Management Today

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PSD 14.0 Constraint Manager

Common, powerful environment for constraint entry / editing / management and verification

Single mechanism for managing constraints throughout the design process

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Constraint Manager – Key Features

Spreadsheet-based graphical interface

– No cryptic formats or cumbersome updating

Provides unsurpassed Integration across the entire design flow

– Consistent Front to Back solution– No messy translations with static

constraint data – Directly integrated with

schematic and PCB databases– Analysis engines can update

spreadsheet data interactively

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Constraint Manager – Hierarchy

Allows constraints to be managed hierarchically– Groups of rules are maintained as Electrical Constraint Sets

(ECSets)– Provides single point for updating rules or assigning to nets– ECSets can be applied to groups of nets (buses) with individual

overrides

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Constraint Manager – Systems

Support for system level constraints– Constraints can span PCB

boundaries

Chipset

Termination RIMM

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Topology

Templa

tes


Guides:FloorplanningHand LayoutAuto-Route

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Constraint Driven Layout Design rule violations during

interactive routing are identified in real-time

Autorouter follows design rules - powerful integration with SPECCTRA!

Because solution space analysis has defined a set of conditions under which the nets are known to work, chance of first-pass success is high.

– Nets can be ripped up and rerouted, as long as they still adhere to the design rules

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Topology Entry &

Floorplanning


Analyze

Constrain





Post Route Analysis

Verification

Post Route Analysis


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Agenda

What is High-Speed Design?Ideal High-Speed Design ProcessIntroduction to SPECCTRAQuest Power IntegritySPECCTRAQuest Demonstration

NOWNOW


SPECCTRAQuest Power Integrity Module

The Future of Power Delivery System Design

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SPECCTRAQuest Power Integrity

Innovative technology developed and proven by Sun Microsystems, now commercialized by Cadence Design Systems, Inc. to address Power Delivery issues in high-speed PCB System Designs.

A design tool / methodology used to design and optimize the frequency-dependent characteristics of Power Delivery Systems in high-speed system designs

An integrated solution to allow many quick iterations of “change-simulate-analyze”

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Power Delivery Requirements TrendYear Voltage Power Current Zta rge t Frequency

(Volts) (Watts) (Amps) (m-Ohms) (MHz)1990 5 5 1 250 161993 3.3 10 3 54 661996 2.5 30 12 10 2001999 1.8 90 50 1.8 6002002 1.2 180 150 0.4 1200

Power dissipation and longer battery life fueling decreasing chip power supply voltages

– Maximum allowable supply ripple decreases accordingly SoC, SiP fueling trend towards devices with large number of devices

– The instantaneous switching current required is enormous The maximum acceptable power supply ripple voltage determines the

target impedance which must be maintained across the PCB– Maximum supply impedance must be less than 0.002 Ohms

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Power Delivery System Design Challenges

Power supply droop– Alters system timing and can cause Setup failures– Can cause sampling errors that results in a system crash

Unreliable power delivery system design can cause increased common-mode EMI preventing product shipment due to compliance problems

Power delivery system impedance is frequency-dependent– Must be controlled for all frequency range of all transient currents

Increases Development Costs and Time to Market is LOST!Increases Development Costs and Time to Market is LOST!

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Power Delivery System Design -How it is done today

Standalone analysis tools– Design data translation is left up to the user– Changes to the design resulting from simulation is manual

Use Time Domain simulation– Power delivery system impedance is frequency-dependent!– With only time domain simulation, it is like searching for needle in

a haystackOver design - add more de-coupling capacitors than necessary

– Expensive solution that may not work

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The Cadence approach

Allow users to determine the needs of the power delivery system– Target impedance– Decoupling capacitor requirements

Provide frequency domain analysis to find problem areasProvide an integrated PCB design editor to optimize capacitor

placement

Develop reliable power delivery systemwhile shortening design cycle timeDevelop reliable power delivery systemwhile shortening design cycle time

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SPECCTRAQuest Power Integrity -Software Components

Frequency-domain analysis engine Integrated PCB editor that includes

Decoupling capacitor placement environment

Impedance requirements calculator Decoupling requirements wizard High speed capacitor library / library

editor

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Isolating Decoupling Problem Areas

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Device Placement – Decoupling Capacitors Capacitors can be selected from

the decoupling “menu” and placed into the design

The effective decoupling radius is automatically displayed as the capacitor is positioned

Designers continue to adjust capacitor selection & placement until performance of the PDS is acceptable

Allows many “change-simulate-analyze” cycles in a short time

Allows many “change-simulate-analyze” cycles in a short time

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Release

Available with PSD release version 14.1– Scheduled for late Q2, 2001

First release available on Sun Solaris (7 / 8) only– Other platforms to follow with next major release

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SPECCTRAQuest Power Integrity - Summary Innovative technology developed

and proven by Sun Microsystems, commercialized by Cadence

Combined toolset and methodology for the design and analysis of high performance power delivery systems

Offered as an option to SPECCTRAQuest, integrated with Allegro

Part of Cadence’s complete family of Signal Integrity / Power Delivery / EMI solutions

Shortens Development Cycle and Time to Market!Shortens Development Cycle and Time to Market!

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Agenda

What is High-Speed Design?Ideal High-Speed Design ProcessIntroduction to SPECCTRAQuest Power IntegritySPECCTRAQuest Demonstration NOWNOW


SPECCTRAQuest Demonstration

(please ask questions as we proceed!)

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What You Will See

Intel PIII / BX Reference Design–100 MHz Front-Side Bus

Analysis & Constraint Process–Board Level–Electrical Level–Constraint Integration–Advanced Processing

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Post-Route DRC Verification

DRC checks identify areas which do not comply with design rules

– Net is marked visually– Identifies which constraint was

violated DRC provides a “first pass” check

faster than simulation Design rules can also be applied

without ripping up etch, to pinpoint problems in boards routed before design rules were available

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Post-Route Analysis Verification

Post-layout simulation now becomes a “verification” process

Chances of first-time success are high if a thorough solution-space analysis was performed

Nets can be extracted individually and analyzed in-depth if problems are found

SQ has the only optimized spice analysis engine that is integrated with PCB layout and field solvers

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SPECCTRAQuest: Integrated Constraint & Analysis


Topology Entry &

Floorplanning


Analyze

Constrain





cadence’s solution for high-speed design

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