Camera Auto Focus

Group W1Tom Goff

Dave HwangKate Killfoile

Greg Look

Design Manager: Bowei Gai

Final Presentation, April 30th, 2007

Project Objective: Design a low-power, small autofocus chip for use in camera or other hand-held device

1. Market

2. Algorithm

3. Architecture

4. Verification

5. Layout

6. Conclusion and questions

Agenda

The Market

Target market

• Camera manufacturers– Digital– Video– Security

82 million cameras expected to be sold in 2007

$18 billion industry

Autofocus methods

Active Passive

Analyze image

Focus

Passive vs. active

Pros Cons

Active • Able to focus in the dark

• Focus with little contrast

• High power

• Fooled by reflection and interference

• Limited range

Passive • Faster and more accurate

• Bigger range

• Less power

• Hard to fool

• Cannot focus in the dark

• High contrast needed

Where our chip fits in

Our Chip18-525 Implementation

Why hardware?

• Software solutions are slow• Software rule logic uses memory

– Less room for pictures!

• Software computation draws power– Shorter battery life

Why our chip?

• Adaptability to any camera and lens• No calibration methods needed• Large market

– Most commercial digital cameras use passive focus

• Customizable– Rule values can be adjusted

Current industry

• Size– 10 mm x 10mm x 5 mm dimensions

• Power– 5 mW minimum industry standard

• Speed– Only need to be faster than motor– High end digital cameras: 60 fps– High end video camera: 3000 fps– Speed floor at 3 kHz

Design goals

Size Goal 100,000 um2

Power Goal < 5 mW

Speed Goal 100 kHz

Our Algorithm

Our algorithm

2 main inputs to our chip :

di – % change in “sharpness” ag – Average grey level

0.4 0.7 1

Z S M B

0di

1

64 127 255

NB

0ag

1

191

NS NPZ PS PB

Range ofdi and ag

Rule 1

Rule 2

Rule 6

+ Motor Output

% match

weighted constant

x

% match

weighted constant

x

% match

weighted constant

x

ag

di

Our algorithm

0.4 0.7 1

Z S M B

0di

1

64 127 255

NB

0ag

1

191

NS NPZ PS PB

Translation to hardware

• Floating point multiplier and adder– Series of summed products– Internal floating point format

• Only used 1 multiplier and adder– Benefit: reduced size– Cost: reduced speed

• Low power components– Low power full adder– Pass logic

Architecture

System architecture

Floorplan evolution

Input Registers

Delta-I Preprocessor

AG Preprocessor

Rule Logic

Integer to FloatingPoint Units

Data Staging Registers

Rule SelectionMuxesThree-Input Floating

Point MultiplierFloating Point Adder

Accumulation andOutput RegistersPower Logic

Signal flow

SERF full adder

• 10 transistors• Proven low-power design• Weak output in some cases

Carry-save multiplier

• Fewer full adders• Compact design (0.437 density)• Speed not an issue

Floating point adder

• Handles de-normalized numbers• Does not round• Determines leading zeroes with combinational logic

Floating Point Compare

Swap MuxesExponent Comparison

Exponent Normalization

Greg

Adjust B Significand

Add Significands

Significand Normalization

Floating point adder

Floating point multiplier

• Reuses some submodules from the adder• Three inputs means savings on exponent

combination and normalization logic

Floating point multiplier

Norm 1

Integer multiplier

Combine exponents

Integer multiplier

Norm 2

Verification

C implementation Verilog

Verification procedure

Exhaustive testing

Compared C implementation with Verilog :

0.000724 error rate!

Layout verification

• Hierarchical testing of modules• Compared against expected schematic output

– Edge cases– Generic cases

di

0.4 0.7 1

Z S M B

0di

1

64 127 255

NB

0ag

1

191

NS NPZ PS PB

ag

Layout

Layer masks

Specifications

Inputs

di 10 bit

ag 8 bit

enable 1 bit

reset 1 bit

clk 1 bit

Outputs

motor_out

10 bit

33 pins total

Area 206 x 187 = 38,689 μm2

# of transistors

pmos: 4,948

nmos: 5,846

Total: 10,794

Density 0.279

Aspect ratio 1.099

Clock speed 666 MHz

Throughput 10 MHz (max speed)

Power 0.977 mW

Conclusion

• Advise caution with shared libraries

• Floor planning is super important

• Test, test, and more test at every stage

• Solve problems early

Questions?

Global simulation

ag simulation

di simulation