canon iwlpc canon paper - canon global

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Canon Solutions for Advanced Heterogeneous Integration and Fan-Out Processes Doug Shelton 1 , Ken-Ichiro Mori 2 , Yoshio Goto 2 , Hiromi Suda 2 1 Industrial Products Division, Canon U.S.A., Inc., San Jose, USA 2 Semiconductor Production Equipment PLM Center 1, Canon Inc., Utsunomiya, Japan [email protected] ABSTRACT High-Performance Computing systems can employ leading- edge Heterogeneous Integration (HI) technology including Fan-Out Wafer Level Packaging (FOWLP) and high-density Redistribution Layers (RDL) to maximize system bandwidth and performance. These More-than-Moore strategies are growing in importance and present unique challenges that must be overcome to enable mainstream adoption. FOWLP roadmaps for interconnections between SoC (System on Chip) and DRAM (Dynamic Random Access Memory), split-die FPGA (Field-Programmable Gate Array) and image sensors and SoC are driving RDL scaling and aggressive FOWLP processes are targeting 0.8 μm design rules. High-resolution lithography is required for high- density, fine-RDL applications and the main lithography challenge is to provide a large Depth-of-Focus (DoF) to reliably pattern sub-micron RDL traces across a large exposure field. This paper details an analysis of candidate optical conditions for sub-micron imaging including data demonstrating the DoF performance of an optimized lithography system (stepper). To meet the high-resolution requirements of fine-RDL processes, Canon developed the FPA-5520iV-HR [20iV-HR] i-line stepper that employs a new projection optical system featuring a maximum 0.24 Numerical Aperture (NA) and a 52 x 34 mm field size. We will present data illustrating that 0.24 NA steppers can provide excellent resolution and pattern fidelity throughout each exposure field across the entire wafer. High-density FOWLP wafers can also display extreme die- shift, warpage and topography that must be addressed to enable high-yield and high-productivity processes. Die placement error in FOWLP wafers creates orders of magnitude more alignment error versus traditional silicon wafers and advanced alignment compensation is required to improve overlay matching. Alignment solutions for processing distorted FOWLP wafers include the Grid-PA system that automatically corrects the wafer loading position based on die-grid sampling, and Enhanced Advanced Global Alignment (EAGA) that allows the stepper to measure and compensate for shift, rotation and intra-field magnification errors on a die-by-die basis. FOWLP reconstituted wafers can also experience large warpage that can decrease productivity and DoF and to combat these challenges, our steppers have been designed to handle wafers with over 5 mm of warpage and are also based on a Front-End-Of-the-Line (FEOL) stepper platform that offers die-by-die tilt and focus measurement and compensation to maximize focus accuracy and DoF. This paper provides an analysis of key lithography challenges facing aggressive FOWLP and fine-RDL processes details of stepper technology that helps enable high-density integration in mass-production. We remain committed to enabling innovation through lithography system performance upgrades and development of original options supporting current and future FOWLP and fine- RDL processes. Keywords: Fan-Out Wafer Level Packaging, Fan-Out Panel Level Packaging, High-Bandwidth Memory, lithography, Heterogeneous Integration INTRODUCTION High-Performance Computing systems can employ leading- edge Heterogeneous Integration (HI) technology including Fan-Out Wafer Level Packaging (FOWLP) and high-density Redistribution Layers (RDL) to maximize system bandwidth and performance [1]. These More-than-Moore strategies are growing in importance and offer unique challenges that must be overcome to enable mainstream adoptio requiring high-yield; low-cost processes. Key lithography process requirements for 3D and 2.5D More-than-Moore applications are provided in Figure 1 and include accurate processing of severely warped and distorted bonded wafer stacks and reconstituted wafers. . Figure 1: Key lithography process requirements for 3D and 2.5D applications

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Page 1: Canon IWLPC Canon Paper - Canon Global

Canon Solutions for Advanced Heterogeneous Integration and Fan-Out Processes

Doug Shelton1, Ken-Ichiro Mori2, Yoshio Goto2, Hiromi Suda2

1Industrial Products Division, Canon U.S.A., Inc., San Jose, USA

2Semiconductor Production Equipment PLM Center 1, Canon Inc., Utsunomiya, Japan

[email protected]

ABSTRACT

High-Performance Computing systems can employ leading-

edge Heterogeneous Integration (HI) technology including

Fan-Out Wafer Level Packaging (FOWLP) and high-density

Redistribution Layers (RDL) to maximize system

bandwidth and performance. These More-than-Moore

strategies are growing in importance and present unique

challenges that must be overcome to enable mainstream

adoption.

FOWLP roadmaps for interconnections between SoC

(System on Chip) and DRAM (Dynamic Random Access

Memory), split-die FPGA (Field-Programmable Gate Array)

and image sensors and SoC are driving RDL scaling and

aggressive FOWLP processes are targeting 0.8 µm design

rules. High-resolution lithography is required for high-

density, fine-RDL applications and the main lithography

challenge is to provide a large Depth-of-Focus (DoF) to

reliably pattern sub-micron RDL traces across a large

exposure field.

This paper details an analysis of candidate optical

conditions for sub-micron imaging including data

demonstrating the DoF performance of an optimized

lithography system (stepper). To meet the high-resolution

requirements of fine-RDL processes, Canon developed the

FPA-5520iV-HR [20iV-HR] i-line stepper that employs a

new projection optical system featuring a maximum 0.24

Numerical Aperture (NA) and a 52 x 34 mm field size. We

will present data illustrating that 0.24 NA steppers can

provide excellent resolution and pattern fidelity throughout

each exposure field across the entire wafer.

High-density FOWLP wafers can also display extreme die-

shift, warpage and topography that must be addressed to

enable high-yield and high-productivity processes.

Die placement error in FOWLP wafers creates orders of

magnitude more alignment error versus traditional silicon

wafers and advanced alignment compensation is required to

improve overlay matching. Alignment solutions for

processing distorted FOWLP wafers include the Grid-PA

system that automatically corrects the wafer loading

position based on die-grid sampling, and Enhanced

Advanced Global Alignment (EAGA) that allows the

stepper to measure and compensate for shift, rotation and

intra-field magnification errors on a die-by-die basis.

FOWLP reconstituted wafers can also experience large

warpage that can decrease productivity and DoF and to

combat these challenges, our steppers have been designed to

handle wafers with over 5 mm of warpage and are also

based on a Front-End-Of-the-Line (FEOL) stepper platform

that offers die-by-die tilt and focus measurement and

compensation to maximize focus accuracy and DoF.

This paper provides an analysis of key lithography

challenges facing aggressive FOWLP and fine-RDL

processes details of stepper technology that helps enable

high-density integration in mass-production. We remain

committed to enabling innovation through lithography

system performance upgrades and development of original

options supporting current and future FOWLP and fine-

RDL processes.

Keywords: Fan-Out Wafer Level Packaging, Fan-Out Panel

Level Packaging, High-Bandwidth Memory, lithography,

Heterogeneous Integration

INTRODUCTION

High-Performance Computing systems can employ leading-

edge Heterogeneous Integration (HI) technology including

Fan-Out Wafer Level Packaging (FOWLP) and high-density

Redistribution Layers (RDL) to maximize system

bandwidth and performance [1]. These More-than-Moore

strategies are growing in importance and offer unique

challenges that must be overcome to enable mainstream

adoptio requiring high-yield; low-cost processes.

Key lithography process requirements for 3D and 2.5D

More-than-Moore applications are provided in Figure 1 and

include accurate processing of severely warped and

distorted bonded wafer stacks and reconstituted wafers. .

Figure 1: Key lithography process requirements

for 3D and 2.5D applications

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More-than-Moore strategies have been a hot topic for more

than a decade, starting with 3D integration using Through

Silicon Vias (TSVs) and evolving into today’s promising

technology of Heterogeneous Integration using interposers

and fine-RDL.

Because advanced GPUs and FPGAs used in autonomous

driving require wideband interconnection with memories,

RDL layers in next generation interposers will require sub-

micron patterning [2] as is illustrated in Table 1.

Lithography process optimization plays a role in reducing

costs as uniform imaging performance is required to fully

exploit the benefits of HI, FOWLP and Fan-Out Panel Level

Packaging (FOPLP). we previously reported lithography

challenges for with aggressive processes[3], and Table 2

includes an updated list of challenges including demands for

high-resolution lithography and accurate overlay

compensation to increase interconnect density and

ultimately electronic system bandwidth, Updates

highlighted in bold will be reviewed in detail in this paper.

Table 2: Heterogeneous Integration Lithography

Challenges

Category Issues Solutions

Imaging

< 1 micron resolution 0.24 NA Lens

Vertical thick resist patterning Large DOF lens

Large topography Multi-channel optical Auto-Focus

Wafer

Processing Yield / Productivity

Wafer Warpage > 5 mm

Wafer Edge Shield(WES)

Wafer Edge Exposure(WEE)

Alignment

Flexibility

Back-side alignment “TSA-Scope” with IR

Mark deterioration New alignment mark

Overlay

Accuracy Die grid error

Grid Pre-Alignment

Global alignment

Die-by-die alignment

To meet this demand, we have developed steppers that can

now provide new projection optics offering a 0.24

Numerical Aperture (NA) and a large 52 x 34 mm exposure

field. 20iV steppers (Figure 2) equipped with the High-

Resolution 0.24 NA Option can provide stable 0.8 µm

imaging across throughout the entire exposure area.

This paper reports on a study of photolithography

challenges related to patterning of sub-micron RDL for

chip-to-chip wide bandwidth interconnections. We will also

provide details optional systems available for the steppers

that can help enable aggressive advanced packaging

processes.

High-Resolution Advanced Packaging Process

Challenges

RDL scaling is a key requirement to enable multi-chip

interconnection market expansion using FOWLP or

interposers. Advanced packaging roadmaps already require

1.0 µm RDL for interconnecting SoC and DRAM, SoC and

image sensors and split-die FPGA with future applications

target 0.8 µm RDL.

A key lithography challenge for fine-RDL is providing a

sufficient Depth of Focus (DoF) to accurately resolve sub-

micron features. Front-End-of-Line (FEOL) lithography

tools feature large NA optical systems that do not provide

enough DoF to resolve sub-micron patterns over large

interposer topography. On the other hand, traditional Back-

End-of-Line (BEOL) lithography tools struggle to resolve

very fine patterning due to their extremely low NA and

leveling systems that can’t reliably position wafers in tight

DoF range during exposure.

We have a unique position in the lithography tool market. In

addition to our many years of experience in the FEOL

lithography tool business, we have enjoyed strong growth in

the BEOL stepper market since 2011 and we has continued

to develop solutions that add functionality and improve

productivity and yields.

Our steppers feature a variable NA (Numerical Aperture)

Optical System that can be optimized to improve imaging

performance across a large exposure field. NA directly

affects imaging performance and it is important to choose

Figure 2: Canon Stepper Illustration

Table 1: Comparison of die-size, bandwidth and RDL

size requirement for high-bandwidth memory

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the optimum NA for each process. Large NA conditions

typically deliver resolution below 1 µm for fine-line

Redistribution Layer (RDL) processes, while the stepper

NA can be reduced through recipe parameters to increase

Depth of Focus (DoF) for imaging through thick resists used

for plating and etch masks.

Figure 3 shows the relationship between NA and imaging

performance with respect to resolution and DoF. The

simulation results plot the expected DoF for corresponding

resolution targets, for NA values of 0.18, 0.24, 0.37, 0.45

and 0.57. The data shows that the largest NA values

provide the best overall resolution, although the DoF for a

0.8 µm L/S pattern is less than 5 µm which is not ideal. The

simulations predict that 0.24 NA exposure conditions are

optimum for fine RDL processes, providing the largest

process window with >7 µm of DoF for 0.8 µm imaging.

Because of this background, we have a responsibility to

contribute to fine RDL interposer technology by developing

a lithography tool that is optimized for sub-micron

processes. To meet these requirements, we developed new

projection optics offering 0.24 NA imaging and 52 x34 mm

exposure field.

New Projection Optics For Fine-RDL Patterning

To support sub-micron RDL patterning, we developed a

new projection optical system and lens that features a large

NA and large exposure field. The new High-Resolution

(HR) projection optics are an option offering an 0.24 NA

and a 52 x 34 mm exposure field and standard and optional

specifications are summarized in Table 3.

Table 3: i-line Stepper Specifications

Advanced Packaging Stepper Specifications

Wafer Size 300 mm

365 x 306.7 mm (option)

Resolution ≤ 1.5 µm

≤ 0.8 µm (option)

NA 0.15 - 0.18

0.24 Max (option)

Reduction Ratio 2:1

Exposure Field 52 x 34 mm

52 x 68 mm (option)

Exposure 365 nm (i-line)

Single Machine

Overlay Accuracy

Front ≤ 0.15 µm

Back ≤ 0.5 µm (option)

Wave-Front Engineering In Optics Manufacturing

Imaging performance and resolution must be maintained

throughout the entire wafer and within each exposure field

to maximize process yield. our steppers apply proprietary

manufacturing methods and wave-front engineering

technology to minimize lens aberrations that can reduce

resolution, while also employing and on-axis optical tilt

focus sensor to compensate for wafer topography on a shot-

by-shot basis.

Resist profiles are affected by lens aberration and it is

important to control lens aberration for sub-micron

resolution. Figure 4 illustrates the relationship between

coma aberration and pattern size and the simulation shows

that that 0.8 µm pattern resist profiles are sensitive to lens

aberration.

Figure 4: Impact of Coma aberration (simulation)

We employs high-precision design and manufacturing

technology developed over many years of FEOL experience

in wave-front engineering and manufacturing to produce a

stable, supply of low-aberration lenses capable of achieving

sub-micron resolution.

Figure 5 provides an outline of the Phase Measurement

interferometer (PMi) system that we use to quickly and

accurately collect lens aberration measurement data. PMi

obtains the interference pattern of a reference light wave and

Figure 3: NA 0.24 is an optimum condition for 0.8 µm

imaging

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a light wave passed that has passed through the lens to

enable high precision lens aberration analysis and high

quality lens assembly.

Figure 5: Outline of Phase Measurement interferometer

(PMi) used for aberration analysis

Photoresist Patterning Study

Key to lithography performance is the ability to deliver

high-resolution and high-image fidelity uniformly across a

large exposure field and we have collaborated with

photoresist and electronic materials companies to

characterize imaging of 0.8 µm features in a variety of

materials.

Figure 6 demonstrates high-resolution imaging performance

of a 0.24 NA stepper and displays a plot of printed feature

size (Critical Dimension, CD) vs. Focus position for 0.8 µm

Line & Space (L/S) patterns. The test was conducted using

1.095 µm thick PFi-38 A7 i-line photoresist and a DoF

evaluation examined 15 image heights across a 52 x 34 mm

field. Results showed that under an NA 0.24 condition for

0.8 µm L/S imaging and given a +/- 10% CD budget (- 80

nm, + 80 nm) yielded a DoF of > 8 µm which should

provide sufficient focus margin for fine RDL processes.

Figure 6: NA 0.24 resolution testing demonstrates

> 8 µm DoF for 0.8 µm Line/Space imaging Figure 7 shows examples of cross-sectional photoresist

profiles for 0.8 µm L/S patterns using 1.48 µm thick

TDMR®-AR1100 LB (Tokyo Ohka Kyogyo Co. Ltd.) i-line

photoresist. The data shows that 0.24 NA exposure yields a

larger 8 µm DoF and is superior to 0.18 NA for 0.8 µm

processes.

Figure 7: 0.24 NA & 0.18 NA imaging results for 0.8 µm

Line/Space patterns

Resist profile examples 2.5 µm thick i-line photoresist from

JSR are provided in Figure 8. The examples demonstrate

that 0.8 µm features patterned using 0.24 NA on a copper

seed wafer showed stable resist profiles suitable for high-

resolution RDL plating processes.

Figure 8: 0.8 µm Copper seed layer resist profiles using

0.24 NA (2.5 µm thick resist)

This data demonstrates that our lithography systems can

meet the fine-RDL imaging requirements to enable

aggressive Heterogeneous Integration applications. The

large exposure field and high-resolution of the new 0.24 NA

HR projection optics can help speed the development of

large size FOWLP and interposers manufacturing and

performance improvements of FPGA and GPU devices.

Die-By-Die Optical Tilt & Focus System

FOWLP requires RDL layer formation on substrates that are

warped due to molding and material stresses. Wafer

warpage can reduce the usable depth of focus in sub-micron

RDL processes that have a small focus margin. To help

provide high-precision focusing across warped wafers, Our

steppers are equipped with an Optical Tilt & Focus (OPTF)

0.80 µm

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System (Figure 9) that enables die-by-de die tilt & focus

compensation.

Figure 9: Stepper Optical Tilt Focus System

The optical tilt focus system is adapted from FEOL stepper

designs and offers die-by-die tilt and focus measurement

and compensation to maximize focus accuracy and DoF.

Prior to exposure of each shot, the optical tilt focus system

projects multiple beams of LED measurement light onto

each shot and directs the reflected beams to focus sensors.

The focus and tilt position of each shot can be calculated

and compensated in real-time prior to exposure, avoiding

pre-exposure topography measurements that can negatively

affect throughput.

Die-by-die focus compensation in a sample FOWLP wafer

is shown in Figure 10 with as much as 20 µm chip-to-mold

topography across a wafer. By applying die-by-die focus

compensation, the stepper can reduce the residual focus

error to < 10 µm across the wafer (Figure 11) to incresase

the usaable DoF within each field [3].

The dioptric lens design also allows steppers to enjoy a > 20

mm gap between the bottom of the projection lens and

wafer surface to help reduce the effects of resist outgassing.

Warped Wafer Handling System

FEOL lithography tools have no solutions for warped wafer

handling which is a major challenge in packaging processes.

BEOL lithography systems must overcome the challenge of

handling warped wafer and substrates. Our current steppers

feature an advanced wafer handling system that steppers can

process wafers with more than 5 mm of warpage which

allows processing of reconstituted FOWLP wafers and

silicon interposers that often experience severe warpage and

distortion.

In fine pattern exposure, warpage of wafer reduces focus

margin and therefore it is necessary to flatten the warped

wafer prior to exposure. Figure 12 shows wafer flatness

measurement of a warped wafer prior to mounting to a

wafer chuck. Wafer flatness before chucking is 730 µm

and after chucking global wafer flatness reduced to 4.3 µm

and flatness within a 52 x 34 mm field is reduce to 1.6 µm.

Reducing the wafer flatness within each field maximizes

DoF and improves process margins.

Figure 12: Global wafer flatness can be reduced from

730 µm to 4.3 µm after chucking

Die Rotation Measurement And Compensation

One of the most challenging aspects of FOWLP processes

however is the requirement to compensate for die-shift

caused during bonding and molding processes [5].

In chip-first processes, large die shift and rotation errors can

occur during the die placement and molding processes.

Figure 10: Original FOWLP topography has > 20 µm

topography across the wafer

Figure 11: After focus compensation, FOWLP

topography can be reduced to < 10 µm across the wafer

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Wafer notch position is typically defined after molding and

position accuracy is generally poor and not necessarily

related to the actual die positions.

The typical wafer handling sequence includes a mechanical

pre-alignment step that positions the wafer relative to the

notch before loading to the wafer stage where more accurate

optical alignment steps are performed.

It is sometimes difficult to align FOWLP wafers exhibiting

poor notch accuracy which can lower system throughput. To

overcome this issue, we are developing a new Grid Pre-

alignment (Grid PA) function that references the wafer

notch and wafer chip layout a to improve pre-alignment

accuracy. An illustration of the Grid PA alignment system

is provided in Figure 13.

The grid prealignment sequence captures a wafer image

using 2 cameras positioned across the X axis with of the

wafer. Grid position measurements (Y position) are

performed on Left (L) and Right (R) positions and the

difference between the L/R Y values are calculated relative

to the span between the cameras. Grid prealignment

calculates and applies global compensation for chip rotation

relative to the notch reference, making it possible to reduce

FOWLP wafer process times as shown in Figure 14 [2]

Die-by-Die Overlay Compensation

Fine RDL patterns must align and accurately overlay the

underlying die. For non-distorted wafers, steppers typically

employ an Advanced Global Alignment (AGA) strategy that

samples the position of several fields on a wafer, and applies

overlay compensation to each field based on a linear

approximation based on the sample shot data.

For FOWLP wafers exhibiting extreme die-shift, overlay is

typically measured and compensated for on a die-by-die

basis during lithography processing to improve overlay and

FOWLP process yield. To correct for die-shift errors, our

steppers offer a variety of compensation functions including

the optional Enhanced Advanced Global Alignment

(EAGA) Function to enable die-by-die overlay

compensation to correct for die-shift errors inherent in

FOWLP applications.

To improve FOWLP overlay, die-by-die alignment (detailed

in Figure 15) involves the stepper using its internal

alignment system to measure and map out the position of

each die or field on a wafer prior to exposure. [6]

Compensation based on this direct measurement is applied

to the wafer during exposure to improve matching overlay

and compensate for die shift errors.

Figure 15 Die-by-die overlay process sequence applies

overlay compensation based on shot-by-shot

measurement data

Die-by-Die overlay compensation simulations have been

conducted to estimate the effect of applying shot-by-shot

compensation to severely distorted wafers exhibiting large

amounts of wafer and intra-field distortion. A comparison of

conventional linear overlay compensation and Die-by-Die

overlay performance is shown in Figure 16 The data

illustrates that die-by-die overlay compensation for distorted

wafers can reduce overlay error by more than 60% to meet

the accuracy level required for dense sub-micron RDL and

TSV fabrication [7].

X span

L

R

Figure 13: Grid-PA System Schematic

Figure 14: Grid PA reduces mark search and loading

error correction times

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Through-Silicon Alignment

Through-Silicon Alignment

Our steppers can also be equipped with a Through-Silicon

Alignment (TSA) System that can use infrared wavelength

light to illuminate overlay targets during fine wafer

alignment. Use of infrared light can enable the stepper

observe targets on the backside of standard thickness

silicon wafers. The optional infrared alignment system can

provide a variety of wavelength bandwidth ranges that can

be optimized to increase alignment accuracy. TSA system

concepts are illustrated in Figure 17.

Figure 17: Through Silicon Alignment (TSA) option

utilizes infrared light to view alignment targets on the

backside of wafers

Evaluation of infrared backside alignment overlay has been

performed and has been found to meet advanced TSV and

backside process requirements. Figure 18 illustrates the

front-to-back overlay results across a 300 mm wafer using a

26 x 33 mm field size and a 4X reduction stepper. The

silicon wafer thickness was 775 µm with backside alignmen

targets etched into the backside of the wafer. Infrared

backside overlay was performed and test results showed that

the 4X stepper achieved 112 nm 3-sigma overlay across the

wafer with is thought to be sufficient for advanced backside

processess.

Panel Handling (Under Study)

FOWLP process adopters are eager to ramp panel-based

Fan-out (FOPLP) processes as opposed to wafer-based

processes to improve productivity and overall costs [8].

We have studied panel handling technology supporting

high-resolution FOPLP including adaptation of the 0.24 NA

stepper and has developed limited (non-automated) panel

substrate handling system for R&D purposes, allowing

exposure of panels up 365 x 306.7 mm (approximately 1/6

of a Gen 4.5 panel). Modified 0.24 NA steppers have been

shown to provide a large DoF for 0.8 µm resolution on 365

x 306.7 mm rectangular panels as shown in Figure 19 and

We are continuing to study panel-based process

characteristics including slit coater photo resist materials

and the the effect of panel substrate flatness.

Our steppers provide special functions and performance

supporting fine RDL & FOPLP processes and we are

committed to continuing to collaborate and innovate with

our panel process partners.

CONCLUSION

We have developed a 0.24 NA stepper to meet the

requirements of sub-micron RDL for high-Performance

Computing, Heterogeneous Integration (HI), Fan-Out Wafer

Level Packaging (FOWLP) and high-density Redistribution

Layers (RDL) maximize system bandwidth and

performance.

Figure 16: EAGA shot-by-shot overlay compensation

can reduce overlay error by 60% vs. sampling and

linear overlay compensation

Figure 19: Exposed test panel

Figure 18: Backside overlay of 112 nm 3-sigma has been

achieved using 4X reduction high-resolution steppers

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Our steppers can be configured with an 0.24 NA High-

Resolution optics to enable 0.8 µm resolution on 300 mm

wafers and we will continue to develop solutions for the

unique challenges and requirements of sub-micron RDL and

advanced packaging applications. By applying years of

advanced FEOL and precision optical technology to support

development of a variety of original options for More-than-

Moore applications, we are able to overcome packaging

process challenges to enable mainstream adoption of these

advanced technologies. Canon remains committed to

continuing to innovate and enable the future generations of

high-yield and high-productivity advanced packaging

processes.

ACKNOWLEDGEMENTS

The authors would like to thank their Canon USA, Canon

Inc. and Canon ANELVA colleagues for their contributions

to this paper.

REFERENCES

[1] S. Iyer, Moore’s Law for Heterogeneous Integration, UCLA CHIPS Report 2017 (Oct. 2017)

[2] Ken-Ichiro Mori, Douglas Shelton, Yoshio Goto, Yasuo Hasegawa, Seiya Miura, Sub-micron RDL patterning for Advanced Packaging, ECTC 2019 (May 2019)

[3] Hiromi Suda, Photolithography Study For High-Density Integration Technologies, IWLPC 2015 (Oct. 2015)

[4] Doug Shelton, Tomii Kume, Sanjay Shinde Ph.D., Takaaki Tsunoda Canon Manufacturing Solutions for Advanced Heterogeneous Integration and Fan-Out Wafer & Panel Level Packaging Processes, IMAPS Microelectronics 2018 (Oct. 2018)

[5] D. Shelton Advanced Manufacturing Technology for Fan-Out Wafer Level Packaging, IMAPS Microelectronics 2015 (Oct. 2015)

[6] D. Shelton, C. Y. Wang, Advanced Stepper Through-Silicon Alignment (TSA) Evaluation and Overlay of Distorted Bonded Wafer Stacks, IMAPS Microelectronics 2012, (Oct. 2012)

[7] D. Shelton, Tomii Kume, Lithography Process Optimization for 3D and 2.5D Applications, IMAPS Microelectronics 2013 (Oct. 2013)

[8] C. Chu, R. Rice, FOPLP Standardization Survey Results, SEMI Standards, (Nov. 2017)

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