cascode mos circuit

Sheet 1 of 10

Cascode CMOS Circuit The cascode is a combination of a common-source device with a common-gate load. This has the effect of increasing the output impedance but minimises the Miller effect making it an ideal configuration for use at high frequencies. The circuit of the cascode amplifier is shown in Figure 1.

Vout

M2

I

Vin M1

VDD

VBIAS

Rload

Cgd1

Figure 1 Basic Cascode Amplifier Lets assume that FET M2 has a short between the drain and source terminals, the remaining circuit will be a common-source amplifier with a gain of:

1loadload

1LOAD1 gogo

gm1 Avspeakingstrictly ggm or .Rgm Av +==

Sheet 2 of 10

Now miller effect occurs when there is a large impedance applied to the drain of the common-source M1 in this case its RLOAD but it could also be an active load with an even higher resistance. This has the effect of applying a gate shunt capacitance which, has a value of the M1 gate-drain capacitance multiplied by the voltage gain of the amplifier:- ( )( )LOAD1gd1shunt-gate .Rgm1C C += Thus with a particular source impedance connected to the input of the amplifier the 3-dB break point will be:-

( )( )[ ]LOAD1gd1gs3 .Rgm1CC.Rs21 ++= dBf

If there is a load capacitor attached to the load then a second higher frequency pole will be introduced:

( )LOADLOADLOAD

M2M1D3

LOADLOAD

LOAD3

.C.2R1

.C2..I

then active is Go If .C2

Go

+=

=

dB

dB

f

f

The M1 device is a voltage controlled source and the small gate voltage (Vgs) creates a large current (Ids) through the RLOAD creating an output voltage (Vo) much greater than the input (Vgs) ie it has voltage gain. So if you could place a low impedance current buffer between M1 and the RLOAD you could greatly reduce the Miller effect and this is exactly what M2 biased into saturation does. The resistance looking into a source is pretty low:-

==

====

6-1E R 0.01 100uA, @ device typical a For

I g1

VgsgVgs

IV R

IN

M2DM11MIN

ININ

A practical cascode amplifier is shown in Figure 2. The device M2 acts as a low impedance current buffer, isolating the amplifying M1 with the load M3. Therefore, the gain of the cascode amplifier is approximately:-

3D1

1N1

13

1

3

1

..IL.W2.K- Av

gogogm Avspeakingstrictly

gogm Av

=

+==

Sheet 3 of 10

Vout

M2

I

Vin M1

VDD

VBIAS2

M3

VBIAS3

Figure 2 Cascode amplifier with active load

3D3OUT I

1 rds R = To be able to fully characterise the amplifier we need expressions in order to calculate output voltage swing and frequency response.

( )

LK.W Where

VT1VDD1

VT2VBIAS21VT3-VBIAS3VDD

2. V

VDS- VDDV

2

M2

M3OUTMIN

3SATOUTMAX

=

+=

=

Sheet 4 of 10

Example Determine the gain, output resistance, gate bias voltages, Vmax and Vmin of the cascode amplifier of Figure 2. Assume W=L=1um, KN=110uA/V2, KP=50uA/V2, = 0.05; VT = 0.7V, ID=100uA. The first step is to calculate the required bias voltages for each device. First set the correct current to 100uA, so we need to determine the correct vgs to apply to the N-type FET.

0.95V 0.7 - 1.65 V- V V

1.65V 110E100E 0.7

KI V Vgs

TGSSAT

6-

-6

N

REFT

===

=+=+=

So we set the amplifying device M1 to vgs = 1.65V and the second device to Vgs+VSAT =

2.6V.

And set the correct Vgs to apply to the P-type FET active source.

terminal) gate to4.3V 0.7-5(apply 0.72V 50E

100E 0.7 KI V Vgs 6-

-6

P

REFT ==++=+=

So we set the bias to M3 at 4.3V. Calculation of gain

16.5dB 6.63 .0.05.100E1E

.1E2.110E- ..IL.W2.K- Av

gogogm Avspeakingstrictly

gogm Av

6-6

6-6-

3D1

1N1

13

1

3

1

====

+==

Output Resistance

=== 200K .0.05100E

1 I1 rds R 6-

3D3OUT

Sheet 5 of 10

Output Voltage Swing

5V 0.02-5 V

0.02V 0.7-0.72 V- V VDS

VDS- VDDV

OUTMAX

T3GS33SAT

3SATOUTMAX

=

===

=

( )

( ) 0.116V1)(0.838)0.227.(0.6 7.05

17.035.2

10.7-9.35

1.1110E2.

1.150E

V

LK.W Where

VT1VDD1

VT2VBIAS21VT3-VBIAS3VDD

2.

V

2

6-

6-

OUTMIN

2

M2

M3OUTMIN

==

+=

=

+=

The ADS simulation of the example cascode is shown in Figure 4. The gain plot as a result of the simulation is shown in Figure 3.

DC.IDS.i 95.59uA

DC.VSAT_N 699.3mV

DC.vout 1.397 V

20 40 60 80 0 100

16.973

16.974

16.975

16.976

16.977

16.972

16.978

freq, MHz

dB(AC.vout)

Figure 3 Resulting Gain plot from the ADS simulation of the example Cascode Amplifier

Sheet 6 of 10

1.65 V

699 mVVSAT_N

2.35 V

1.40 Vvout

3.90 V

5 V

5 V

5 V

MOSFET_PMOSMOSFET2

Width=W umLength=L umModel=MOSFETM2

-95.6 uA

95.6 uA

3.61 pA0 A

V_ACSRC4

Freq=freqVac=1 VVdc=VGS1

0 A

ACAC1

Stop=100 MHzStart=0.1 MHz

AC

VARVAR2

L=1VGS1=1.65VDD=5VGS3=3.9VGS2=2.35W=1

EqnVar

LEVEL1_ModelMOSFETM1

Tox=24.7e-4Mjsw=0.38Cjsw=380e-12Mj=0.5Cj=770e-12Cgbo=700E-12Cgdo=220e-12Cgso=220e-12Lambda=0.05Phi=0.7Gamma=0.4Kp=110e-6Vto=0.7NMOS=yes

DCDC1

DC

MOSFET_NMOSMOSFET1


95.6 uA

-95.6 uA

0 A -719 fA

MOSFET_NMOSMOSFET3


95.6 uA

-95.6 uA

0 A -718 fA

V_DCVGS2Vdc=VGS3

0 A

V_DCVGS3Vdc=VGS2

0 A


Tox=24.7e-4Mjsw=0.35Cjsw=350e-12Mj=0.5Cj=560e-12Cgbo=700E-12Cgdo=220e-12Cgso=220e-12Lambda=0.05Phi=0.8Gamma=0.57Kp=50e-6Vto=0.7PMOS=yes

I_ProbeIDS

95.6 uAV_DCVDDVdc=VDD

-95.6 uA

Figure 4 ADS simulation setup for the example Cascode Amplifier A more practical circuit is shown in Figure 5. This circuit now includes the correct bias current mirrors and associated bias setting resistor. The left hand bias arm includes FETs configured as diodes such that the voltage across each source-drain is VSAT+VT. One advantage of doing

Sheet 7 of 10

this is that the voltage drop across the resistor is smaller and therefore requires a smaller bias resistor, in this case about 1K which can easily be formed from a Polysilicate printed resistor.

3.52 VVbias2

3.63 VVbias3

1.63 VVT_VSAT

3.63 VVout

5 V

5 V

5 V 5 V 5 V

5 V

5 V

0 V

1.62 VVbias1

DC DC1

DC



RR1R=1130 Ohm

100 uA

VAR VAR2

L=1 VDD=5 W=1

Eqn Var

LEVEL1_Model MOSFETM2

Tox=24.7e-4 Mjsw=0.35 Cjsw=350e-12 Mj=0.5 Cj=560e-12 Cgbo=700E-12 Cgdo=220e-12 Cgso=220e-12 Lambda=0.04 Phi=0.8 Gamma=0.57 Kp=50e-6 Vto=0.7 PMOS=yes

V_DC VDD Vdc=VDD

-200 uA

I_ProbeIDS

100 uA

MOSFET_NMOS MOSFET5

Width=W um Length=L um Model=MOSFETM1

100 uA

-100 uA

0 A-5.18 pA

MOSFET_PMOS MOSFET4


-100 uA

100 uA

1.38 pA 0 A

MOSFET_PMOS MOSFET2


-100 uA

100 uA

1.38 pA0 A

AC AC1

Stop=100 MHz Start=0.1 MHz

AC

DC_BlockDC_Block1

0 A

MOSFET_NMOS MOSFET1


100 uA

-100 uA

0 A -1.65 pA

MOSFET_NMOS MOSFET3


100 uA

-100 uA

0 A -5.30 pA

MOSFET_NMOS MOSFET6


100 uA

-100 uA

0 A-1.64 pA

V_AC SRC4

Freq=freq Vac=1 V Vdc=

0 A

Figure 5 Practical Cascode Amplifier design with added bias The resulting plot and table of bias voltages is shown in Figure 6.

Sheet 8 of 10

DC.IDS.i 99.97uA

DC.Vbias1 1.624 V

DC.Vbias23.518 V

DC.Vbias33.631 V

DC.Vout 3.631 V

DC.VT_VSAT1.625 V

10 20 30 40 50 60 70 80 90 0 100

16.2774

16.2776

16.2778

16.2780

16.2782

16.2772

16.2784

freq, MHz

dB(AC.Vout)

Figure 6 Resulting plot from the simulation of the circuit shown in Figure 5. Note that VT+VSAT = 1.625V and closely agrees with the 1.65V calculated earlier. We can obtain more gain from the cascode by adding a further active load as shown in Figure 7. The gain of the stage will now be:-

32dB 44 .0.05.100E1E

.1E2.110E- ..IL.W2.K- Av

..IL.W2.K- gainnew the Then

..IL.W2.K- Av As

gogm Av

then load the cascode weIf gogo

gm Avspeakingstrictly gogm Av

6-6

6-6-

3D1

1N1

3D1

1N1

3D1

1N1

2

3

1

13

1

3

1

===

==

+==

Sheet 9 of 10

Vbias2

Vout

Vbias3

Vbias4

VT_VSAT

Vbias1

VARVAR2

L=1VDD=7.5W=1

EqnVar

RR1R=9700 Ohm

MOSFET_PMOSMOSFET2


MOSFET_PMOSMOSFET4


V_DCVDDVdc=VDD

I_ProbeIDS

MOSFET_PMOSMOSFET8


MOSFET_PMOSMOSFET7




DCDC1

DC


Tox=24.7e-4Mjsw=0.35Cjsw=350e-12Mj=0.5Cj=560e-12Cgbo=700E-12Cgdo=220e-12Cgso=220e-12Lambda=0.04Phi=0.8Gamma=0.57Kp=50e-6Vto=0.7PMOS=yes

MOSFET_NMOSMOSFET5


ACAC1

Stop=100 MHzStart=0.1 MHz

AC

DC_BlockDC_Block1

MOSFET_NMOSMOSFET1


MOSFET_NMOSMOSFET3


MOSFET_NMOSMOSFET6


V_ACSRC4

Freq=freqVac=1 VVdc=

Figure 7 Addition of another active load to increase the gain of the cascode amplifier. Note however that the additional VT+VSAT has meant that to include the bias resistor the supply has been increased to 7.5V.

Sheet 10 of 10

DC.IDS.i 101.1uA

DC.Vbias1 1.628 V

DC.Vbias23.528 V

DC.Vbias34.508 V

DC.Vout4.498 V

DC.VT_VSAT 1.642 V

10 20 30 40 50 60 70 80 90 0 100

32.80

32.81

32.82

32.83

32.84

32.79

32.85

freq, MHz

dB(AC.Vout)

Figure 8 Increased gain cascode of Figure 7, the gain of 32dB agrees with the calculation performed earlier ie AV ~ (gm.Ro)2. Note one of the problems using cascode stages in that for each device we use the voltage drop across each device will be VT+VSAT. This equates to approximately 1.65V per device and with 4 devices this will cause a total voltage drop of 6.6V so we cant use our 5V rail !!!. In the example the voltage supply has been increased to 7.5V to allow for the additional device. This problem of increased voltage rail can be improved by using the folded cascode configuration, where the cascode is split between the active amp and active load and linked by another current load. Also we can greatly reduce VSAT by increasing the W/L ratio. The folded cascode is very popular in the design of low voltage Op-Amps and is subject to another tutorial.

Cascode CMOS CircuitExampleCalculation of gainOutput ResistanceOutput Voltage Swing

cascode mos circuit

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