ccc and tlu
DESCRIPTION
André Welker Lennart Adam, Bruno Bauss , Volker Büscher, Reinhold Degele , Karl Heinz Geib , Sascha Krause, Yong Liu, Lucia Masetti, Phi Chau , Uli Schäfer, Rouven Spreckels , Stefan Tapprogge , Rainer Wanke. CCC and TLU. AIDA Meeting Frascati , 11. April 2013. - PowerPoint PPT PresentationTRANSCRIPT
CCC and TLU
AIDA MeetingFrascati, 11. April 2013
André WelkerLennart Adam, Bruno Bauss, Volker Büscher, Reinhold Degele, Karl Heinz Geib, Sascha Krause, Yong
Liu, Lucia Masetti, Phi Chau, Uli Schäfer, Rouven Spreckels, Stefan Tapprogge, Rainer Wanke
Read-out-chain
André Welker, AIDA Meeting , Frascati, 11. April 2013
SiPMASICdetector interface
digitalanalogHBU
data-aggregator
(LDA)
clock- and control-card
(CCC)
SiPMASICdetector interface
digitalanalogHBU
controlclocktriggerdatabusy
DAQ PC
beam control
Ethernet
on-detector-electronicoff-detector-electronic
Ethernet control, trigger, clock, busy
2
Mainz-development:- firmware in VHDL- hardware- softwarefan-out
moreLDAs
Read-out-chain
SiPMASICdetector interface
digitalanalogHBU
data-aggregator
(LDA)
clock- and control-card
(CCC)
SiPMASICdetector interface
digitalanalogHBU
controlclocktriggerdatabusy
DAQ PC
beam control
Ethernet
on-detector-electronicoff-detector-electronic
Ethernet control, trigger, clock, busy
2
fan-out
moreLDAs
André Welker, AIDA Meeting , Frascati, 11. April 2013
Clock and Control Card(CCC)Requirements:
1. High clock stability in the whole detector
2. Configuration interface over Ethernet• manage different running modes• for feedback functions• for beam control
3
Status:
1. Built and tested for a lab setup and used in test beams 2012
2. Next step: Upgrade for bigger test beams (almost finished)
André Welker, AIDA Meeting , Frascati, 11. April 2013
2012 Clock and Control CardMezzanine on an Kintex 7 Evaluation-Board:
FPGA-controlled CCC board:
4
CCC at the testbeam (top):
CCC at the testbeam (front):
André Welker, AIDA Meeting , Frascati, 11. April 2013
5
First iteration with a Zynq-processor on a Zedboard for development:
New 2013 Clock and Control Card
Zedboard:- Evaluation Board from DigilentZynq:- ARM9 dual core processor (Linux)
+- FPGA
CCC Mezzaninefrom Mainz
André Welker, AIDA Meeting , Frascati, 11. April 2013
6
Final design for test beams:
Clock and Control Card(CCC)
6U-VME formfactorPeculiarity of the Mars-Modul:1. Zynq- ARM9 dual core- Linux + FPGA2. 512MB NAND/RAM
front: top:
SYNC
ASYNC
USER
TTL IN
TTL OUT
Micro-SDEthernet
Mars-ZX3 firm:EnclustraAndré Welker, AIDA Meeting , Frascati, 11. April 2013
CCC Fan-out same as in 2012 6U-VME Fan-out board:
Fan-out board layout:
7
Fan-out board at the testbeam:
André Welker, AIDA Meeting , Frascati, 11. April 2013
Four main modes and 13 commands:
signal:e.g. busy:
Running Modes
8
U
62 42
t
start acquisition with falling edge
stop acquisition with rising edge conditions: ASIC buffer full
André Welker, AIDA Meeting , Frascati, 11. April 2013
Read-out-chain
SiPMASICdetector interface
digitalanalogHBU
data-aggregator
(LDA)
clock- and control-card
(CCC)
SiPMASICdetector interface
digitalanalogHBU
busycontrol
DAQ PC
beam control
Ethernet
on-detector-electronicoff-detector-electronic
Ethernet busycontrol
9
fan-out
control
- stop acquisition- and start the detector read-out
buffer full
André Welker, AIDA Meeting , Frascati, 11. April 2013
Running ModesFour main modes and 13 commands:
signal:e.g. busy:
10
U
62 42
conditions: ASIC buffer full
t
extended commands: (backward compatible)
- manual trigger- listen on falling or rising edge- status- hard- and softreset- and many more
start acquisition with falling edge
stop acquisition with rising edge
André Welker, AIDA Meeting , Frascati, 11. April 2013
CCC and TLU ConfigurationProcessing Instruction Configurator (piconf) (by Rouven Spreckels)
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● Configures all devices● Configuration procedures are automated● Everything stored in one or multiple XML files● Self-explanatory, predefined XML tags● Interface independent:
- implemented: TCP/IP
André Welker, AIDA Meeting , Frascati, 11. April 2013
piconf example
12André Welker, AIDA Meeting , Frascati, 11. April 2013
CCC with a TLU
1. Baseline: Integrate the current TLU VHDL code Fallback: Integrate a hardware part for the Ethernet
2. Baseline: Integrate a hardware part for the EthernetFallback: Integrate an own TLU VHDL code
Both solutions depends on the timescale, less manpower until the May 2013 testbeam
13
Two possibilities:
André Welker, AIDA Meeting , Frascati, 11. April 2013
Status of CCC
1. One module physically exists
2. Hardware tested
3. Firmware almost done
CCC should be ready to go for the test beam in May 2013
14André Welker, AIDA Meeting , Frascati, 11. April 2013
Thank you for your
attention!
André Welker, AIDA Meeting , Frascati, 11. April 2013