ce amplifiers
TRANSCRIPT
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CE AMPLIFIERS
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CE AMPLIFIERS
• The first step is to set up an operating or ‘Q’ point using a suitable bias circuit.
• We will, by way of introduction, use a so called load line technique to see the interplay between the circuit and device constraints on voltage and current.
• This will provide a graphical analysis of amplifier behaviour.
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CE AMPLIFIERS
• The following (simple) bias circuit uses a single resistor RB to fix the base current.
• It is not very good since the emitter/collector currents and hence the operating point (IC, VCE) vary with β.
• This will be improved with stabilised bias circuits in due course.
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CE AMPLIFIER, Simple bias
RB RC
GND
+VCC
ICIB
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CE AMPLIFIER, Simple bias
RB RC
GND
+VCC
ICIB
VCE
VBE
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CE AMPLIFIER, Simple bias
• To enable us to look at a particular numerical example we choose the supply voltage VCC = 5V and RC = 2.5 kΩ
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CE AMPLIFIER, Simple bias
RB 2.5 x 103
GND
+5
IC
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CE AMPLIFIER, Simple bias
• In later discussions an a.c. signal (and an additional load resistor) will be coupled to the d.c. circuit using coupling capacitors.
• The capacitor values are chosen so that their impedance (1/ ωC) is negligibly small (zero) at the a.c.(signal) frequency (or over the operating frequency range).
• A capacitor acts as a short circuit for d.c. and the d.c. bias circuit can be designed independently of the a.c. source and any ‘a.c. load’.
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CE AMPLIFIER, Simple bias
RB 2.5 x 103
GND
+5
IC
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CE AMPLIFIER, Simple bias
0VIRV CECCCC =−−From Kirchhoff, for the output,
RC
GND
+VCC
IC
VCE
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CE AMPLIFIER, Simple bias
• Numerically, 5 - 2.5 x 103 IC-VCE =0
• Or, rearranging, IC = (5 – VCE )/ (2.5 x 103)
• A plot of IC against VCE is a straight line with slope (– 1/ 2.5 x 103)
• It is called a load line and represents the variation of IC with VCE imposed by the circuit or load.
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CE AMPLIFIER, Simple bias
• Another variation of IC with VCE is determined by the output characteristic.
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CE AMPLIFIER, Simple bias
• Another variation of IC with VCE is determined by the output characteristic.
• The two relationships can be solved graphically for IC and VCE.
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CE AMPLIFIER, Simple bias
• Thus we calculate three points on the load line IC = (5 – VCE )/ (2.5 x 103) as
IC =0, VCE =5V
IC = 1mA, VCE =2.5V
VCE =0V, IC =5/2500 A = 2mA.
• To enable us to plot it on the output characteristic.
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CE AMPLIFIER, Simple bias
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CE AMPLIFIER, Simple bias
• The region along the load line includes all points between saturation and cut-off.
• The base current IB should be chosen to maximise the output voltage swing in the linear region.
• Bearing in mind that VCE (Sat) ≈ 0.2 V and VCE Max = 5V choose the operating (Q) point at IB = 10 μA.
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CE AMPLIFIER, Simple bias
‘Operating’ or Q point set by d.c. bias.
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CE AMPLIFIER, Simple bias
• From Kirchhoff, for the input,
RB
GND
+VCC
IB
VBE
0VIRV BEBBCC =−−
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CE AMPLIFIER, Simple bias
• Remembering that VBE ~ 0.6 V (the base or input characteristic is that of a forward biased diode) we can find RB ~ 440 kΩ.
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CE AMPLIFIER, Simple bias
• A a.c. signal is superimposed on top of the d.c. bias level.
• We are interested in the voltage and current gains for this a.c. component.
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CE AMPLIFIER
VS
RS
VCC
GND
VCE
RLRB
IC
Signal outputSignal input
RC
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CE AMPLIFIER
• The Q (d.c. bias) value of VCE is about 2.5 V
• The maximum positive signal swing allowed is, therefore (5-2.5) V = 2.5 V (The total
• The maximum negative voltage swing allowed is (2.5 –0.2) V =2.3 V
• The maximum symmetric symmetric signal swing about the Q point is determined by the smaller of these, i.e. it is ±2.3 V.
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CE Amplifier
• To find the voltage and current gains using the load line method we must use the input and output characteristics.
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CE Amplifier
Diode dynamic resistance for signals = 1/slope at Q point! Defines transistor input impedance for signals
Remember we selected IB = 10 μA
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CE Amplifier
• From the input curve we estimate that as IB
changes by ±5μA about the bias level of 10μA then the corresponding change in VBE is about 0.025 V.
• When iB =5μA, vBE = 0.5875V; when iB
=15μA, vBE = 0.6125.
V 0.025 V BE =∆
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CE Amplifier
• From the output characteristic curve we move up and down the load line to estimate that as IB changes by ±5μA the corresponding change in VCE is about –2.5 V. (Note the negative sign!)
• When iB =5μA, vCE = 3.75V; when iB =15μA, vCE = 1.25V V 2.5- V CE =∆
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CE Amplifier
• From the input curve we estimate that as IB
changes by ±5μA about the bias level of 10μA then the corresponding change in VBE is about 0.025 V.
• When iB =5μA, vBE = 0.5875V; when iB
=15μA, vBE = 0.6125.
V 0.025 V BE =∆
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CE AMPLIFIER
‘Operating’ or Q point set by d.c. bias.
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CE Amplifier
• The CE small signal (a.c.) voltage gain is
100V 0.025
V 2.5-
V
V
BE
CE −==∆∆
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CE Amplifier
• From the output characteristic curve we also see that as we move up and down the load line a change in IB of ±5μA produces a corresponding change in IC of ±5mA.
• The a.c. signal current gain is 100.• This is consistent with the ideal
characteristic uniform line spacing, i.e. β = 100 = constant.
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CE AMPLIFIER
‘Operating’ or Q point set by d.c. bias.
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Ideal CE Amplifier Summary
• The CE voltage and current gains are high
• The voltage gain is negative, i.e. the output signal is inverted.
• The d.c. bias current sets the signal input impedance of the transistor through the dynamic resistance.
• IC = β IB ; iC = β iB.
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Ideal CE Amplifier Summary
• Two of these statements:• The d.c. bias current sets the signal input
impedance of the transistor through the dynamic resistance.
• IC = β IB ; iC = β iB.
will be used to derive our simplified small signal equivalent circuit of the BJT. (It is simplified because it is based on ideal BJTs)
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Additional a.c. Load
• Suppose an a.c. coupled load RL = 2.5 kΩ is added
vin
GND
vout
RL
RC
C
VCC
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Additional a.c. Load
• The ‘battery’ supplying the d.c. supply VCC has negligible impedance compared to the other resistors, in particular RC.
• It therefore presents an effective ‘short-circuit’ for a.c. signals.
• The effective a.c. load is the parallel combination of RC and RL . (From the collector C we can go through RC or RL to ground)
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Additional a.c. load
RC
GND
RL
a.c. short via d.c. supply
iC
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RC
GND
RL
iC
Additional a.c. load
vce
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Additional a.c. Load
• We now need to construct an a.c. load line on the output characteristic.
• This goes through the operating point Q and has slope
• This is hard to draw!
A/V1250
1
//RR
1
LC−=−
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Additional a.c. Load
a.c. load line, drawn with required slope through Q point.
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Additional a.c. Load
• The available voltage swing and the voltage gain are calculated using the a.c. loadline.
• Symmetric swing reduced to about ±1.25 V
• Voltage gain reduced to about –50.
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Stabilised Bias Circuits
• These seek to fix the emitter current independently of BJT parameter variations, principally in β.
• This is best achieved by introducing an emitter resistance and setting the base voltage via a resistor network (R1, R2) which acts as a potential divider (provided IB can be assumed small)
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Stabilised Bias Circuit
VS
RS
VCC
GND
vout
RCR1
R2 RE
Bias bit of the circuit, a.c. source and load capacitor coupled. RE is capacitor by-passed (shorted) for a.c. signals
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Stabilised Bias Circuit
• See handout for a detailed analysis of this bias circuit
• We will also look at a worked example of a transistor amplifier based on such a stabilised bias circuit once we have established an a.c. equivalent circuit for the transistor.
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Stabilised Bias Circuit
• Finally we give another circuit which provides bias stability using negative feedback from the collector voltage.
+VCC
GND
D.C collector voltage VC
RCRB
VBE =0.6 V
IB
IC
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Stabilised Bias Circuit
+VCC
GND
D.C collector voltage VC
RCRB
VBE =0.6 V
IB
IRC
,RI - V V C RCCCC =
IC
B CBRC I)(1I I I β+=+=
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Stabilised Bias Circuit
+VCC
GND
D.C collector voltage VC
RCRB
VBE =0.6 V
IB
IRC
B B B BBEC RI 0.6RI V V ++= ≈
IC
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Stabilised Bias Circuit• For example, increasing β, increases IC
which lowers the collector voltage VC and hence and IB and IC
+VCC
GND
D.C collector voltage VC
RCRB
VBE =0.6 V
IB
IC