ce439 cad algorithms for physical design - introduction · 2018. 3. 15. · s. k. lim, practical...
TRANSCRIPT
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CE439 – CAD Algorithms for
Physical Design - Introduction
Christos P Sotiriou
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Contents
TCL Library and C API
https://www.tcl.tk/
https://www.tcl.tk/man/tcl8.5/TclLib/contents.htm
GNU Readline API
http://www.gnu.org/software/readline/
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Recommended Texts
Recommended books
S. K. Lim, Practical Problems in VLSI Physical Design Automation,
Springer, 2008
C. J. Alpert, D. P. Mehta, S. S. Sapatnekar, Handbook of Algorithms
for Physical Design Automation, Auerbach Publications, 2008
S. M. Sait and H. Youssef, VLSI Physical Design Automation: Theory
and Practice, World Scientific, 1999.
Algorithm book
T. H. Cormen, C. E. Leiserson, R. L. Rivest, C. Stein Introduction to
Algorithms, MIT Press, 2009 (3rd edition)
Selected papers from the literature.
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Physical Design Problems to Algorithms
Identify Problem Formulation into an Algorithm
CAD Algorithms Physical Design Stages
Graph algorithms Partition
Graph algorithms
Combinatorial Algorithms
Mathematical programming
(QP, LP)
Placement
Shortest path
Mathematical programming
(LP)
Greedy algorithms
Static Timing Analysis
Routing
Graph Algorithms
Combinatorial Algorithms
Legalization
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Physical Design Structure
Devices
Transistors
Logic gates and cells
Function blocks
Interconnects
Local signals
Global signals
Clock signals
Power/ground nets
Pad Metal1 Via Metal2
I/O
Data Path
ROM/
RAM
PLA
A/D ConverterRandom
logic
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Physical Design Cycle
Large number of devices
Optimization requirements for high performance
Time-to-market competition
Power (and other) constraints
System
SpecificationChip
Manual
Automation
Large number of devices
Optimization requirements for high performance
Time-to-market competition
Power (and other) constraints
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Design Cycle – 1
System Specification
Functional Design
Logic Design
Circuit Design
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
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Design Cycle - 2
Physical Design
Fabrication
Packaging
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Physical Design Steps
Design Steps in More Detail
Partitioning/Clustering
Floorplanning
I/O Pin Assignnent
Placement
Clock Tree Synthesis
Global Routing
Detail Routing
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Physical Design Steps
Design Steps:Partition & ClusteringFloorplan & Placement
clk
clkclk
a
a
aPin AssignmentGlobal RoutingGlobal RoutingDetailed Routing
Methodology:Divide-and-Conquer
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Physical Design Steps
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Complexities of Physical Design
More than 100 million transistors
Performance driven designs
Power-constrained designs
Time-to-Market
PPA (Power-Performance-Area) is key metric
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Why is Physical Design Important?
Many existing solutions are still very suboptimal
E.g., placement
Interconnect dominates
No physical layout, no accurate interconnect
More new physical and manufacturing effects pop up
Crosstalk noise, …
OPC (manufacturability), etc.
More vertical integration needed
Physical design is the KEY linking step between higher
level planning/optimization and lower level modeling
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Technology Trends and Challenges
Interconnect determines the overall performance
In addition: noise, power => Design closure
Furthermore: manufacturability => Manufacturing closure
Source:
ITRS
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The Placement Problem
Placement, to large extend, determines the overall
interconnect
If it sucks, no matter how well you interconnect
optimization engine works, the design will suck
Placement is a very old problem, but got renewed interest
Mixed-size (large macro blocks and small standard cells)
Optimality study shows that placement still a bottleneck
Not even to mention performance driven, and coupled with
buffering, interconnect optimizations, and so on (all you name)
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Comparison with Optimal Solution
Capo: Based on recursive min-cut (UCLA-UMich)
Dragon: Recursive min-cut + SA refinement at each level (NWU-UCLA)
mPL: multi-level placer (UCLA)
There is significant room for improvement in placement algorithms: existing algorithms are 50-150% away from optimal!
0.00
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0 50000 100000 150000 200000 250000
#cells
Mu
ltip
le o
f O
pti
mal
dragon capo mPL
0
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15000
20000
25000
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0 50000 100000 150000 200000 250000
#cells
ru
nti
me(s
)
dragon capo mPL
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Optical Proximity Correction (OPC)
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OPC-Aware Routing
More OPC friendly
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Basic Design Rules
1. Size Rules
2. Separation Rules
3. Overlap Rules
Diffusion Region Width Polysilicon Region Width Diffusion-Diffusion Spacing Poly-Poly Spacing Polysilicon Gate Extension Contact Extension Metal Width
2
2
3
2
2
3
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Size, Separation and Overlap Rules
Incorrectly and
Correctly Formed ChannelsDiffusion
Short
Poly
Incorrectly formed
Channel
Correctly formed
Metal
Diffusion Poly Overlap Rules for
Contact Cuts
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Layout of Basic Devices
CMOS Inverter
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CMOS NAND Gate
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CMOS NOR Gates
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Additional Fabrication Issues
Scaling
Parasitic Effects
Yield Statistics and Fabrication Costs
Delay Computation
Noise and Crosstalk
Power Dissipation
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Design Styles
Complexity of
VLSI circuits
Full custom
Performance Size Cost Market time
Standard Cell Gate Array FPGA
Different design styles
Cost, Flexibility, Performance
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Full Custom Design Style
Pad Metal Via Metal 2
I/OData Path
ROM/RAM
PLA
A/D ConverterRandom logic
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Standard Cell Design Style
VDDMetal 1
CellMetal 2
FeedthroughGND
D C C B
A C C
D C D B
C C C B
Cell A
Cell C
Cell B
Cell DFeedthrough cell
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Gate Array Design Style
Structured ASICs (hot topics nowadays) are essentially gate array
A
B
C
A
B
C
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FPGA Design Style
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Design Styles Comparison
full-custom standard cell gate array FPGA
cell size variable fixed height * fixed fixed
cell type variable variable fixed programmable
cell placement variable in row fixed fixed
interconnections variable variable variable programmable
Area
Performance
Fabrication
layers
style
full-custom standard cell gate array FPGA
compact
high
compact
to moderatemoderate large
high
to moderatemoderate low
ALL ALL routing
layersnone
style
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History of Physical Design Tools
Year Design Tools
1950 - 1965 1965 - 1975 1975 - 1985 1985 – 1995 1995 – 2002 2002 - present
Manual Design
Layout editors Automatic routers( for PCB) Efficient partitioning algorithm Automatic placement tools Well Defined phases of design of circuits Significant theoretical development in all phases Performance driven placement and routing tools Parallel algorithms for physical design Significant development in underlying graph theory Combinatorial optimization problems for layout Interconnect layout optimization, Interconnect-centric design, physical-logical codesign Physical synthesis with more vertical integration for design closure (timing, noise, power, P/G/clock, manufacturability)
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Algorithms
To put devices/interconnects together into VLSI chips
Fundamental questions: How do you do it smartly?
Definition of algorithm in a board sense: A step-by-step
procedure for solving a problem. Examples:
Cooking a dish
Making a phone call
Sorting a hand of cards
Definition for computational problem: A well-defined
computational procedure that takes some value as input
and produces some value as output
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Some Algorithm Design Techniques
Greedy
Divide and Conquer
Dynamic Programming
Network Flow
Mathematical Programming (e.g., linear programming,
integer linear programming)
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Algorithm Analysis
There can be many different algorithms to solve the same
problem.
Need some way to compare 2 algorithms.
Usually run time is the most important criterion used
Space (memory) usage is of less concern now
However, difficult to compare since algorithms may be
implemented in different machines, use different
languages, etc.
Also, run time is input-dependent. Which input to use?
Big-O notation is widely used for asymptotic analysis
Ninf
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Big-O Notation
Consider run time for the worst input upper bound on run time.
Express run time as a function input size n.
Interested in the run time for large inputs.
Therefore, interested in the growth rate.
Ignore multiplicative constant.
Ignore lower order terms.
3n2+6n+2.7 is O(n2).
n1.1+10000000000n is O(n1.1).
n1.1 is also O(n2), but to be more precise, it is O(n1.1)
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Growth Rates of Some Functions
n
nnn
nn
ncc
nOnO
OOO
OnO
cOnO
nOnO
nOnOnnOnnO
nOnOnOnO
!
432
2
constant any for 2
loglog
loglog
2loglog
log
43
25.12
2
Exponential
Functio
ns
Polyn
om
ialFunctio
ns
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NP-Complete Problems
The class NP-Complete is the set of problems which we
believe there is no polynomial time algorithms.
Therefore, it is a class of hard problems.
NP-Hard is another class of problems containing the class
NP-Complete.
If we know a problem is in NP-Complete or NP-Hard,
there is no hope to solve it efficiently.
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Algorithm Solution Types
Polynomial time algorithms
Exponential time algorithms
Special case algorithms
Approximate algorithms
Heuristic algorithms
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