cell b
DESCRIPTION
cbTRANSCRIPT
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1
Brief Introduction of Cell-based Design
Ching-Da Chan CIC/DSD
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Design Abstraction Levels
n+ n+ S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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Full Custom V.S Cell based Design • Full custom design
Better patent protection
Lower power consumption
Smaller area
More flexibility
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4
Full Custom V.S Cell based Design (cont.) • Cell-based design
Less design time
Easer to implement large system
1X 2X 3X
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Prepare Standard Cell Library
1. Circuit design
• Equal height but different width.
• Cell unit is unit tile(ex. 2X, 3X, 4X…).
2. Cell Characterization
• Characterize all condition of input signal. • Extraction the cell view(abstract)
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6
Cell-Based IC Design Flow Overview
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
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General Design Process
Idea Design Verification Implementation Verification Implementation Verification Implementation … Verified Chip Layout
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Cell-Based IC Design Flow Overview
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
Frontend
Backend
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Partition of Design Flow
• Front end – System specification and architecture
– �HDL coding & behavioral simulation
– �Synthesis & gate level simulation
– �dynamic simulation and static analysis
• Back end – Placement and routing
– �DRC (Design Rule Check), LVS (Layout vs Schematic)
– �dynamic simulation and static analysis
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Cell-Based IC Design Flow - RTL Design
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
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Specification of Design Example
• Design Example Specification – Two 32-bit unsigned integer inputs are captured at the positive clock
edge and the sum outputs at the following positive edge clock edge • 32-bit unsigned integer inputs means input data Types
• Positive clock edge means input or output spec.
– The clock period is 10ns • Clock period is the distance of two clock edge.
• 10ns means the data must calculate finished at 10ns
– The power consumption should be less than 1mw
10ns
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RTL HDL Coding
REG ADDER REG in1
module MYADDER (clock, in1, in2, sum, cout); input clock; input [31:0] in1, in2; output [31:0] sum; output cout; reg [31:0] a, b; reg [31:0] sum; always @(posedge clock) begin a = in1; b = in2; {cout, sum} = a + b; end endmodule
in2
clock
a b {cout, sum}
• RTL = Register Transfer Level
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Basic Building Block: Modules
• Modules are the basic building blocks.
• Descriptions of circuit are placed inside modules.
• Modules can represent: – A physical block (ex. standard cell)
– A logic block (ex. ALU portion of a CPU design)
– The complete system
• Every module description starts with the keyword module, followed by a name, and ends with the keyword endmodule.
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Communication Interface: Module Ports
• Modules communicate with the outside world through ports.
• Module port types can be: input, output or inout(bidirectional)
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What's Inside the Module?
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Verilog Basis & Primitive Cell Supported
• Verilog Basis – parameter declarations – wire, wand, wor declarations – reg declarations – input, ouput, inout declarations – continuous assignments – module instantiations – gate instantiations – always blocks – task statements – function definitions – for, while loop
• Synthesizable Verilog primitives cells – and, or, not, nand, nor, xor, xnor – bufif0, bufif1, notif0, notif1
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HDL Compiler Unsupported • delay • initial • repeat • wait • fork … join • event • deassign • force • release • primitive -- User defined primitive • time • triand, trior, tri1, tri0, trireg • nmos, pmos, cmos, rnmos, rpmos, rcmos • pullup, pulldown • rtran, tranif0, tranif1, rtranif0, rtranif1
example: wire out=(!oe)? in : ’hz;
in out
oe
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Example for Error always syntax
module top(clk, a, b, out, …); output out; input a, b, clk; reg out; : : always @(posedge clk)begin if(en1) out=a+b; else out=a-b; end : : always @(posedge clk)begin if(en2) out=a*b; else out=a/b; end : endmodule
+
a b
-
a b
x
a b
÷
a b
Mux Mux
out X
unknow generator
Synthesis Unsupported
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RTL Verification
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
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RTL Verification
• RTL Simulation
module test; reg clock; reg [31:0] in1, in2; wire [31:0] sum; wire cout; MYADDER U1 (clock, in1, in2, sum, cout); always #5 clock = ~clock; initial begin clock = 0; in1 = 10; in2 = 15; @(negedge clock) in1 = 20; in2 = 25; @(negedge clock) $finish; end endmodule
Stimulus &
Control
Design Under Test
MYADDER Observe Outputs
10 20
15 25
25 45 0
in1 in2
sum
cout
0 10 5 15 10 20 15 25 30 35
10
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Cell-Based IC Design Flow - Logic Synthesis
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
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Logic Implementation
• Logic Synthesis
• Design for Testability (DFT) – Memory BIST
– Scan Insertion
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What is Synthesis? (1/2)
always @ (posedge clk) begin if (reset) begin a=0; …….. end else begin a=c+d*b; ……. end end
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
•Synthesis = translation + optimization
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What is Synthesis? (2/2)
•Synthesis is constraint driven •Technology independent
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Logic Synthesis
• Map RTL HDL to Gate-level HDL according to the design constraints and environment
Synthesizable RTL HDL
Cell Library
Design Environment
Design Constraints
Gate-level HDL
Translation Architecture Opt.
Generic Boolean
Technology Mapping Logic Opt.
Timing Constraints Area Constraints
Power Constraints Design Rule Constraints
Operating Conditions Wire Load Model System Interface
AND OR
INVERTER FLIP-FLOP
ADDER …
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Cell Library
A1àO 0.1nsA2àO 0.2ns
function NAND
symble
timing
layout
schematic
abstract
NOR
A1àO 0.1nsA2àO 0.2ns
XOR INV FFADD
A1àO 0.1pwA2àO 0.2pw
power A1àO 0.1pwA2àO 0.2pw
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Design Example
FF
FF
FF
FF
FF
FF
FF
FF
FF
FA
FA
FA
FA
FA
FF clock
Signal Delay < 10ns FF
FA
FF
FA
0.2ns
0.1ns
0.005mw
0.003mw
FF
FA
Flip-Flop
Full Adder
Total Power < 1mw
• Translation: Ripple Adder
• Technology Mapping: Meet timing & power constraints
Assume no interconnect parasitic
Timing Model
Power Model
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Clock Gating Reduces Both Power and Area
Clock gate reduces switching activity on the clock tree
d q q
q d q
q q d
en
clk
Clock Gating reduces power when en=0
d q
d q
d q
en
clk
No Clock Gating en=0 consumes power
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Clock Gating Coding Style
always@ (posedge clk) if (enable) Q <= D_in;
always@ (posedge clk) Q <=(enable)? D_in : Q;
always@ (posedge clk) case (enable) 1’b1: Q <= D_in; 1’b0: Q <= Q; endcase
always @ (posedge clk) if (enable) for (i=0; i<8; i=i+1) s[i] = a[i] ^ b[i];
If statement
If + Loop statement
Conditional Assignment
Case statement
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For Loop
• Provide a shorthand way of writing a series of statements
• In synthesis, for loops loops are “unrolled”, and then synthesized
• Example
always @(a or b) begin for( k=0; k<=3; k=k+1 ) begin out[k]=a[k]^b[k]; c=(a[k]|b[k])&c; end end
out[0] = a[0]^b[0]; out[1] = a[1]^b[1]; out[2] = a[2]^b[2]; out[3] = a[3]^b[3]; c = (a[0] | b[0]) & (a[1] | b[1]) & (a[2] | b[2]) & (a[3] | b[3]) & c
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Netlist after Synthesis
• RTL module MYADDER (clock, in1, in2, sum, cout); input clock; input [31:0] in1, in2; output [31:0] sum; output cout; reg [31:0] a, b; reg [31:0] sum; always @(posedge clock) begin a = in1; b = in2; {cout, sum} = a + b; end endmodule
module MYADDER (clock, in1, in2, sum, cout); input clock; input [31:0] in1, in2; output [31:0] sum; output cout; DFCNQD1 11_ (.CP ( cki ) , .D ( n_22 )) ; MOAI22D0 g301.A2 ( ck_down_12_ ) ) ; IND2D1 g300 ( ck_down_13_ ), .ZN ( n_25 ) ) ; DFCNQD1 ck_down_reg_12_(.D ( n_24 )) ; MOAI22D0 …
• Gate Level
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Pre-layout Gate-level Verification
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
Formal
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Pre-layout Gate-level Verification
• Function Verification – Pre-layout Gate-level Simulation
• Timing Verification – Pre-layout Gate-level Simulation
– Pre-layout Static Timing Analysis (STA)
• Power Verification – Power Analysis
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Pre-layout Gate-level Simulation
• SDF: Standard Delay Format
10 20
15 25
25 45 0
in1 in2
sum
cout
0 10 5 15 10 20 15 25 30 35
18
module test; reg clock; reg [31:0] in1, in2; wire [31:0] sum; wire cout; MYADDER U1 (clock, in1, in2, sum, cout); always #5 clock = ~clock; initial $sdf_annotate(“my.sdf",U1); initial begin clock = 0; in1 = 10; in2 = 15; @(negedge clock) in1 = 20; in2 = 25; @(negedge clock) $finish; end endmodule
Stimulus &
Control
Design Under Test
MYADDER Observe Outputs
SDF Simulation Model
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Cell-Based IC Design Flow - Place & Route
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
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Physical Implementation
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
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Physical Implementation
Data Preparation
Floorplan
Placement
Clock Tree Synthesis
Routing
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Data Preparation
• Verified Pre-layout Gate-level HDL
• Timing/Power Constraints – Similar to those for logic synthesis
• Layout Constraints – Chip Size / Aspect Ratio / IO Constraints
– Physical Partitions (Region / Group)
– Macro Positions…
• Cell Libraries
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Floorplan Area
Pad Area
Core Area
Core Area
Core Area
Pad Limit
Core Limit
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Floorplan - Parameters
Row (Area:1600 µm2)
Channel (Area:400 µm2)
Standard Cell (Area:800 µm2)
50µm
40µm
11µm
13µm
12µm
10µm
Aspect ratio: 40/50 = 0.8 Core Utilization: 800/2000 = 0.4 Core to Left: 10 Core To Right: 11 Core To Bottom: 12 Core To Top: 13
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macro
Floorplan - Power Mesh (Ring)
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Floorplan - Power Mesh (Strap)
without strap (or stripe) with strap (or stripe)
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“Place” the Standard Cell
•Timing driven
•Congestion driven
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Timing-Driven Placement
• Timing-driven placement tries to place cell along timing-critical path close together to reduce net RCs and meet setup timing
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Understanding the Congestion Calculation
Congestion map (heat map)
Routing tracks Global routing grid
29/28
28/28
39/35 40/35
Nets crossing the global routing cell (GRC) edge per available routing tracks
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One Problem with Congestion… • If congestion is not too severe, the
actual route can be detoured around the congested area
• However, the detoured nets will have worse RC delay.
Congestion hot spot
Congestion Map
≥2 ≥3 ≥4 ≥5 ≥6 ≥7
Detour
congestion area
detoured net
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What does Congestion-Driven Placement do?
Spreads apart cells that contribute to high congestion.
What happens to timing when the connected cells are moved apart?
≥2 ≥3 ≥4 ≥5 ≥6 ≥7
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Congestion vs. Timing Driven Placement
• Cells along timing critical paths can be spread apart to reduce congestion
• These paths may now violate timing
Path delay increased
≥2 ≥3 ≥4 ≥5 ≥6 ≥7
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Starting Point before CTS
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
Clock
All clock pins are driven by a single clock source.
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CTS for Design Example
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
Clock
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Grid-based Routing System
• Metal traces (routes) are built along, and centered upon routing tracks based on a grid.
• Each metal layer has its own grid and preferred routing direction:
VHV
M1: Vertical
M2: Horizontal, etc…
HVH
M1: Horizontal
M2: Vertical, etc…
Track
Pitch (based on DRC)
Grid Point
M1
Trace
M2
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Routing for Design Example • After three stage all of the net connection with metal.
Global Route Detail Route
Track Assignment
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Routing - Global Route
Global route Global route
Preroute Preroute
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Routing - Track Assignment
TA metal traces TA metal traces
Preroute Preroute
Jog reduces via count
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Routing - Detail Route
• Detail route attempts to clear DRC violations using a fixed size Sbox
Min Spacing
Thin&Fat Spacing
Notch Spacing
Notch Spacing
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DFM Problem: Gate Oxide Integrity • Metal wires (antennae) placed in an EM field generate voltage
gradients
• During the metal etch stage, strong EM fields are used to ionize the plasma etchant
Oxide Poly
Metal 1 Protective coating
Damaged Gate Oxide
Oscillating charges in Plasma Etch
![Page 57: Cell B](https://reader033.vdocument.in/reader033/viewer/2022051621/55cf9062550346703ba5643a/html5/thumbnails/57.jpg)
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Solution 1: Splitting Metal or Layer Jumping
After layer jumping, to meet Antenna rules
Before layer jumping
Acceptable antenna area
Unacceptable antenna area driver diffusion
gate poly metal 1
M1 blockage
metal 3
driver diffusion
gate poly metal 1
M1 blockage
metal 3 metal 3
M1 is split by jumping to M3 and back
M3 blockage
M3 blockage
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Solution 2: Inserting Diodes
During etch phase, the diode clamps the voltage swings.
Before inserting diodes
Diode Inhibits large voltage swings on metal tracks
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DFM Problem: Random Particle Defects
Center of conductive defects within critical area – causing shorts
Center of non-conductive defects within critical area – causing opens
• Random particle defects during manufacturing may cause shorts or opens during the fabrication process
Critical Areas
Metal 3
Center of conductive defects outside critical area – no shorts
Center of non-conductive defects outside critical area – no opens
+ +
+ + + + + +
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Solution: Wire Spreading + Widening
• Spread wires to reduce short critical area
• Widen wires to reduce open critical area
Wire Tracks Spreadingoff-track
Widening
![Page 61: Cell B](https://reader033.vdocument.in/reader033/viewer/2022051621/55cf9062550346703ba5643a/html5/thumbnails/61.jpg)
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Voids in Vias during Manufacturing
• Voids in vias is a serious issue in manufacturing
• Two solutions are available: Reduce via count: Add backup vias: known as redundant vias
Connection is okay even if one contact defective
Connection fails if contact defective
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Problem: Metal Over-Etching
• A metal wire in low metal density region receives a higher ratio of etchant can get over-etched
• Minimum metal density rules are used to control this
Plasma Etchant etches away un-protected metal
Less etchant per um2
of metal
Over-etching due to high
etchant density
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Solution: Metal Fill Insertion
• Fills empty tracks on all layers (default) with metal shapes to meet the minimum metal density rules
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Cell-Based IC Design Flow - Post-layout Verification
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
Formal
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Post-layout Gate-level Verification
• Function Verification – Post-layout Gate-level Simulation – Formal Equivalence Checking
• Pre-layout Gate-level HDL vs. Post-layout Gate-level HDL
• Timing Verification – Post-layout Gate-level Simulation – Post-layout Static Timing Analysis (STA)
• Power Verification – Power Analysis
Estimated Interconnect Parasitic => Real Interconnect Parasitic
![Page 66: Cell B](https://reader033.vdocument.in/reader033/viewer/2022051621/55cf9062550346703ba5643a/html5/thumbnails/66.jpg)
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Power Analysis
Total Power=
Dynamic Power + Static Power
• Switching power (dynamic): Charging output load
• Internal power (dynamic) Short circuit
Charging internal load
• Leakage power (static) Stable state
In Out
Vdd
Gnd
Cload
Cload
P
N
Vdd
Isw
Ileak
Isht
Out
Cint
P
N
Iintsw Isht
Ileak
In
Gnd
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Power Analysis
I
![Page 68: Cell B](https://reader033.vdocument.in/reader033/viewer/2022051621/55cf9062550346703ba5643a/html5/thumbnails/68.jpg)
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Rail Analysis I
IR power graph
![Page 69: Cell B](https://reader033.vdocument.in/reader033/viewer/2022051621/55cf9062550346703ba5643a/html5/thumbnails/69.jpg)
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Cell-Based IC Design Flow - Physical Verification
Logic synthesis
Place&Route
Gate-Level netlist
Post layout Gate-Level netlist
GDS layout
always @ (posedge clk) if (in1==1) a=c+d else a=c-d
RTL code
Formal
Formal
LVS
RTL SimulationLint check
code coverage analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Gate level SimulationStatic Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level SimulationTransistor-level STA
Power Analysis
Implenentation Verification
![Page 70: Cell B](https://reader033.vdocument.in/reader033/viewer/2022051621/55cf9062550346703ba5643a/html5/thumbnails/70.jpg)
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Physical Verification
• For geometrical verification – Design Rule Check (DRC)
• For topological verification – Layout versus Schematic (LVS)
![Page 71: Cell B](https://reader033.vdocument.in/reader033/viewer/2022051621/55cf9062550346703ba5643a/html5/thumbnails/71.jpg)
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Design Rule Check
M1
M1
M1
M1
CO C1
C2
W
S1S1S2
S2
![Page 72: Cell B](https://reader033.vdocument.in/reader033/viewer/2022051621/55cf9062550346703ba5643a/html5/thumbnails/72.jpg)
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Black Box LVS
t1
GND
VDD
t1i1
t2
i2
z t1i1 z
GND
VDD
i2
nd02d1
U2
inv0d1
U1
i1
i2
t1z
t2
A Y A
B
Y
inv0d1
nd02d1
i1
i2nd02d1
t1
z
inv0d1
U1
U2
A Y
A
BY
BlackBox
BlackBox
LVS Black-box LVS
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73 73
THE END