ceng 4480 l08 memory 2byu/ceng4480/2016fall/l08_memory2.pdf · ceng4480 l08. memory-2 storage based...

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Reference:• Chapter 11 Memories• CMOS VLSI Design—A Circuits and Systems Perspective

• by H.E.Weste and D.M.Harris

CENG 4480L08 Memory 2

Bei Yu

L08. Memory-2CENG4480

CENG4480 v.s. CENG3420

• CENG3420:✦ architecture perspective✦ memory coherent✦ data address

• CENG4480: more details on how data is stored

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Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory(CAM)

Read/Write Memory(RAM)

(Volatile)

Read Only Memory(ROM)

(Nonvolatile)

Static RAM(SRAM)

Dynamic RAM(DRAM)

Shift Registers Queues

First InFirst Out(FIFO)

Last InFirst Out(LIFO)

Serial InParallel Out

(SIPO)

Parallel InSerial Out

(PISO)

Mask ROM ProgrammableROM

(PROM)

ErasableProgrammable

ROM(EPROM)

ElectricallyErasable

ProgrammableROM

(EEPROM)

Flash ROM

Memory Arrays

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Storage based on Feedback• What if we add feedback to a pair of inverters?

• Usually drawn as a ring of cross-coupled inverters

• Stable way to store one bit of information (w. power)

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0 01

1

1 0

0


How to change the value stored?• Replace inverter with NAND gate

• RS Latch

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A B A nand B0 0 10 1 11 0 11 1 0

S

R

Q

Q̄

1

1 0

0


12T SRAM Cell• Basic building block: SRAM Cell

✦ Holds one bit of information, like a latch✦ Must be read and written

• 12-transistor (12T) SRAM cell✦ Use a simple latch connected to bitline✦ 46 x 75 λ unit cell

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bit

write

write_b

read

read_b


nMOS, pMOS, Inverter

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• nMOS:✦ Gate = 1, transistor is ON✦ Then electric current path

• pMOS:✦ Gate = 0, transistor is ON✦ Then electric current path

• Inverter:✦ Q = NOT (A)


6T SRAM Cell• Used in most commercial chips

• A pair of weak cross-coupled inverters

• Data stored in cross-coupled inverters

• Compared with 12T SRAM, 6T SRAM:✦ (+) reduce area✦ (-) much more complex control

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bit bit_b

word


6T SRAM Read

• Precharge both bitlines high

• Then turn on wordline

• One of the two bitlines

will be pulled down by the cell

• Read stability– A must not flip– N1 >> N2

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bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word

0.0

0.5

1.0

1.5

0 100 200 300 400 500 600time (ps)

word bit

A

A_b bit_b


EX: 6T SRAM Read• Question 1: A = 0, A_b = 1, discuss the behavior:

• Question 2: At least how many bit lines to finish read?

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bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word


6T SRAM Write• Drive one bitline high, the other low

• Then turn on wordline

• Bitlines overpower cell with new value

• Writability– Must overpower feedback inverter– N4 >> P2– N2 >> P1 (symmetry)

11time (ps)

word

A

A_b

bit_b

0.0

0.5

1.0

1.5

0 100 200 300 400 500 600 700

bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word


EX: 6T SRAM Write• Question 1: A = 0, A_b = 1, discuss the behavior:

• Question 2: At least how many bit lines to finish write?

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bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word


6T SRAM Sizing

• High bitlines must not overpower inverters during reads

• But low bitlines must write new value into cell

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bit bit_b

med

A

weak

strong

med

A_b

word


Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory(CAM)

Read/Write Memory(RAM)

(Volatile)

Read Only Memory(ROM)

(Nonvolatile)

Static RAM(SRAM)

Dynamic RAM(DRAM)

Shift Registers Queues

First InFirst Out(FIFO)

Last InFirst Out(LIFO)

Serial InParallel Out

(SIPO)

Parallel InSerial Out

(PISO)

Mask ROM ProgrammableROM

(PROM)

ErasableProgrammable

ROM(EPROM)

ElectricallyErasable

ProgrammableROM

(EEPROM)

Flash ROM

Memory Arrays

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Dynamic RAM (DRAM)

• Basic Principle: Storage of information on capacitors

• Charge & discharge of capacitor to change stored value

• Use of transistor as “switch” to:✦ Store charge✦ Charge or discharge

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4T DRAM Cell

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Data must be refreshed regularlyDynamic cells must be designed very carefullyData stored as charge on gate capacitors (complementary nodes)

Remove the twop-MOS transistors from static RAM cell,to get a four-transistordynamic RAM cell.


3T DRAM CellNo constraints on device ratios

Reads are non-destructive

Value stored at node X when writing a “1” = VDD-VT

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VDD-VT


3T DRAM Layout

• 576 λ 3T DRAM v.s. 1092 λ 6T SRAM

• Further simplified

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[1970: Intel 1003]


1T DRAM Cell

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(a) (c)

(f) (g)

Select

B TC

DRAM cell

To Pump

(b)

(d) (e)

Stored 1 Stored 0

Write 1 Write 0

Read 1 Read 0

• Need sense amp helping reading


• Read:✦ Pre-charge large tank to VDD/2✦ If Ts = 0, for large tank : VDD/2 - V1✦ If Ts = 1, for large tank: VDD/2 + V1✦ V1 is very insignificant✦ Need sense amp

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(a) (c)

(f) (g)

Select

B TC

DRAM cell

To Pump

(b)

(d) (e)

Stored 1 Stored 0

Write 1 Write 0

Read 1 Read 0


1T DRAM CellWrite: Cs is charged or discharged by asserting WL and BL

Read: Charge redistribution takes place between bit line and storage capacitance

Voltage swing is small; typically around 250 mV

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Trench-capacitor cell [Mano87]


EX. 1T DRAM Cell• Question: VDD=4V, CS=100pF, CBL=1000pF. What’s

the voltage swing value?

• Note:

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�V = VDD2 · CS

CS+CBL


SRAM v.s. DRAMStatic (SRAM) • Data stored as long as supply is applied • Large (6 transistors/cell) • Fast • Compatible with current CMOS manufacturing

Dynamic (DRAM) • Periodic refresh required• Small (1-3 transistors/cell) • Slower • Require additional process for trench capacitance

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Array Architecture• 2^n words of 2^m bits each

• Good regularity – easy to design

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•••

k ="2nlocations

m bits


SRAM Memory Structure

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n

D D D.$.$.

D D D.$.$.

D D D.$.$.

.$.$.

m

Memory$Data$Out

mMemory$Data$In

Read$Address$Decoder

Memory$Read$Address

n

Write$Address$Decoder

Memory$WriteAddress

GatedD8latch

D Q

WERead$bitlines

Write$bitlines

Write$word$line

Read$word$line

.$.$.

.$.$.

WE

• Latch based memory


Array Architecture• 2^n words of 2^m bits each

• How to design if n >> m?

• Fold by 2k into fewer rows of more columns

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row decoder

columndecoder

n

n-kk

2m bits

columncircuitry

bitline conditioning

memory cells:2n-k rows x2m+k columns

bitlines

wordlines


Decoders• n:2n decoder consists of 2n n-input AND gates

– One needed for each row of memory– Build AND with NAND or NOR gates

Static CMOS Using NOR gates

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word0

word1

word2

word3

A0A1

word0

word1

word2

word3


EX. Decoder• Question: AND gates => NAND gate structure

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word0

word1

word2

word3

A0A1


Large Decoders• For n > 4, NAND gates become slow

– Break large gates into multiple smaller gates

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word0

word1

word2

word3

word15

A0A1A2A3


Predecoding• Many of these gates are redundant

– Factor out common gates– => Predecoder– Saves area– Same path effort

• Question: How many NANDs can be saved?

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A0

A1

A2

A3

word1

word2

word3

word15

word0

1 of 4 hotpredecoded lines

predecoders


Decoder Layout• Decoders must be pitch-matched to SRAM cell

– Requires very skinny gates

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GND

VDD

word

buffer inverterNAND gate

A0A0A1A2A3 A2A3 A1


Column Circuitry• Some circuitry is required for each column

– Bitline conditioning– Column multiplexing– *Sense amplifiers (DRAM)

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row decoder

columndecoder

n

n-kk

2m bits

columncircuitry

bitline conditioning

memory cells:2n-k rows x2m+k columns

bitlines

wordlines


SRAM from ARM

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Bitline Conditioning• Precharge bitlines high before reads

• Equalize bitlines to minimize voltage difference when using sense amplifiers

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φbit bit_b

φ

bit bit_b


Twisted Bitlines• Sense amplifiers also amplify noise

– Coupling noise is severe in modern processes– Try to couple equally onto bit and bit_b– Done by twisting bitlines

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b0 b0_b b1 b1_b b2 b2_b b3 b3_b


SRAM Column Example

Read Write

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H H

SRAM Cell

word_q1

bit_v1f

bit_b_v1f

out_v1rout_b_v1r

φ1

φ2

word_q1

bit_v1f

out_v1r

φ2

MoreCells

Bitline Conditioning

φ2

MoreCells

SRAM Cell

word_q1

bit_v1f

bit_b_v1f

data_s1

write_q1

Bitline Conditioning


Column Multiplexing

• Recall that array may be folded for good aspect ratio

• Ex: 2 kword x 16 folded into 256 rows x 128 columns– Must select 16 output bits from the 128

columns– Requires 16 8:1 column multiplexers

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Ex: 2-way Muxed SRAM

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MoreCells

word_q1

write0_q1

φ2

MoreCells

A0

A0

φ2

data_v1

write1_q1

14. Memories

Tree Decoder Mux• Column mux can use pass transistors

– Use nMOS only, precharge outputs• One design is to use k series transistors for 2k:1 mux

– No external decoder logic needed

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B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7A0

A0

A1

A1

A2

A2

Y Yto sense amps and write circuits


*Sense Amplifiers (DRAM)• Bitlines have many cells attached

– Ex: 32-kbit SRAM has 256 rows x 128 cols– 256 cells on each bitline

• tpd ∝ (C/I) ΔV– Even with shared diffusion contacts, 64C of diffusion

capacitance (big C)– Discharged slowly through small transistors (small I)

• Sense amplifiers are triggered on small voltage swing (reduce ΔV)

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*Differential Pair Amp• Differential pair requires no clock

• But always dissipates static power

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bit bit_bsense_b sense

N1 N2

N3

P1 P2


*Clocked Sense Amp• Clocked sense amp saves power

• Requires sense_clk after enough bitline swing

• Isolation transistors cut off large bitline capacitance

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bit_bbit

sense sense_b

sense_clk isolationtransistors

regenerativefeedback


*Sense Amp Operation for 1T DRAM

• 1T DRAM read is destructive

• Read and refresh for 1T DRAM

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Thank You :-)

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ceng 4480 l08 memory 2byu/ceng4480/2016fall/l08_memory2.pdf · ceng4480 l08. memory-2 storage based...

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