central control for eniac by adele k. goldstine, july 10,...

Central Control for ENIAC

By Adele K. Goldstine, July 10, 1947

2014 Edition from www.EniacInAction.com Edited by Mark Priestley and Thomas Haigh

During 1947 and 1948 a collaborative group designed and implemented a new programming system for ENIAC. The group included John von Neumann, Herman Goldstine, Nick Metropolis, Adele Goldstine, Klara von Neumann, members of the staff of the Ballistic Research Laboratory where ENIAC was housed, and a team of contractors at the Moore School led by Jean Bartik. ENIAC became the first computer to implement what we call the modern code paradigm introduced in von Neumann’s seminal First Draft of a Report on the EDVAC in 1945. We described this process in T. Haigh, M. Priestley, and C. Rope, "Engineering 'The Miracle of the ENIAC': Implementing the Modern Code Paradigm," IEEE Annals of the History of Computing, vol. 36, no. 2, Jan-Mar 2014, pp. 41-59.

Before their eventual implementation in March 1948 by Nick Metropolis and Klara von Neumann the plans went through a succession of revisions. One intermediate plan, for a “60 order code” (i.e. a set of 60 instructions) was published in a technical report and so has been relatively widely cited. R. F. Clippinger, A Logical Coding Scheme Applied to the ENIAC (BRL Report No. 673). Aberdeen, MD: Aberdeen Proving Ground, 1948.

During the course of our research we uncovered what seems to be the first detailed plan for the conversion. This described a set of 51 instructions, and so is generally called the “51 order code.” As described in our paper the report is in the handwriting of Adele Goldstine and contemporary letters suggest that it was produced in July 1947. This followed a series of meetings between von Neumann, members of the BRL staff, and Bartik’s group held in Princeton. So while the document is Goldstine’s, the design it describes undoubtedly includes ideas shaped in this collaborative discussion.

The report is interesting in showing that the basic approach taken to the conversion was fixed early in the process and remained largely unchanged through the end of ENIAC’s career in 1955. Unlike the later 60- and 100-order codes this one required no additions to ENIAC’s original hardware. It would have worked more slowly and offered a more restricted range of instructions but the basic structure of accumulators and instructions changed only slightly.

We did not locate the original copy of this document, but a photocopy was submitted by Herman Goldstine during a legal deposition connected to the landmark Honeywell vs. Sperry Rand trial. That became plaintiff exhibit 5988 and remains in CBI 1: Honeywell vs. Sperry Rand Records at the Charles Babbage Institute in Minneapolis. This copy was duplicated in turn for a

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“Central Control for ENIAC” by Adele K. Goldstine, July 1947. www.EniacInAction.com

reproduction in the personal papers of Herman H. Goldstine at the American Philosophical Society in Philadelphia (Series X, Box 3) and the microfilm copies of the ENIAC trial records at the Hagley Museum and Library and in the University of Pennsylvania Archives. Our thanks go to Arvid Nelsen, CBI archivist, for providing a scan of the document more legible than these microfilm reproductions.

Editorial Notes

Small portions of the text are illegible, or have been reconstructed from their context. These are marked in the transcription by being printed in red. The original does not have numbered pages, so the pagination and numbering used here is

Table 3 gives details of the ENIAC set-up for the main control sequence, and also for instructions 48 – 51. We have only transcribed the portion of this table relating to the control sequence: Goldstine describes this in detail in section III of comments C–3, “Blow-by-Blow Description of Control Process”. That section is reproduced without transcription.

The set-up in Table 3 uses the notation that Goldstine explains in section II of comments C–3. There are also a number of informal comments and markings on the table. To aid the reader, we have reproduced this informal material in blue to distinguish it from the official notation.

This edition is edited by Mark Priestley and Thomas Haigh, with transcription assistance from Ann Graf.


Central Control for ENIAC

Table 1 – 51 order vocabulary (& C-1)

Table 2 – Digit Connections for Control System (& C-2)

Table 3 – Set up for Control Process (& C-3)


7/10/47 Table – 1

51 order vocabulary

Acc. 1 2 4 5 7 9 10 11 12 13 14 16 17 18 19 20

Acc. __, AO to acc. 15 Code Symbol 01 02 03 04 05 06 11 12 13 14 15 16 21 22 23 24

T Order # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Clear acc. __ and receive from Code Symbol 25 26 31 32 33 34 35 36 41 42 43 44 45 46 51 52

acc. 15 AC. L Order # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

C. S.

Order # Instruction C.

S. Order

# Instruction

53 33 Dummy. Clear for acc. 15. D 75 38 +1 shift to left

71 34 MULTIPLY X 1) clear 12 & 15 AC→12 76 39 -1

2) Mult., 10 places ier, NRO (not rounded off), leave prod. 81 40 +5

in 15 and do not clear ier & icand 82 41 -5

72 35 SUBTRACT – take S complement of no. in acc. 15.

83 42 F.T.3 Numeric {

Clear 11 A(11) & A(6)-A(1) →acc. 11 B(11) & B(6)-B(1) → acc. 13

73 36 DIVIDE ÷ 84 43 CONSTANT TRANSMITTER, ABC 1) Clear acc. 7 & 15 AC→7 85 44 “ “ DEF 2) Clear 12 & 4 AC→12 86 45 “ “ GH 3) 9 AC→15 91 46 Read

4) ÷, RO. to 10 places, NI (no interlock). 92 47 Print hold denom. & remainder 93 48 NEXT TWO DIGITS – send N2D from numerator next instruc. From 6 to 15, places 1,2.

5) Acc. 15 AC→ 9 94 49 SUBSTITUTION -- SU

Acc. 4 AC→ 15 Acc. 12 AC→ 4

1) Clear acc. 8L. 2) transmit FTSG from A(11) & B(11)

74 37 SQUARE ROOT √ & next instruc. to 8L 1) Clear acc. 5 & 15 AC→ 5 95 50 U.T. 1) Clear acc. 8R 2) Clear 12 & 7 AC→12 2) transmit FTSG & next instruc. to 8R 3) 9 AC → 15 3) Clear acc. 6 4) √, RO 10 places, NI. 96 51 C.T. 1) Transmit PM from 15→ 8 hold remainder 2) Discriminate 5) 15 AC → 9 3) If M, continue to next instruc. 7AC 2√ 5 times → 15 If P, clear 6 and send 8L→ 8R 12 AC → 7


Comments for Table 1 C-1

I Special purpose accumulators

A. For Control System 1) Acc. 3

a) Shifts instructions (Ij+4, Ij+3, Ij+2, Ij+1, Ij) stored in acc. 6. b) Performs discrimination to determine whether code symbol is to be interpreted

by master programmer steppers B-G or by H-K. c) Sends code symbol to steppers H-K. d) Holds the contents of acc. 8, future control argument, αfβf, (for conditional

transfer +) with its function table selection group, xx, and the current control argument, αcβc, with its FTSG during the magnitude discrimination of a conditional transfer.

e) Builds up argument and function table selection group for substitution order and unconditional transfer.

2) Acc. 6 a) Store 5 instructions (i.e. 5 pairs of code symbols). b) Performs discrimination to determine whether or not a new line of instructions

is to be read from the function tables. c) Sends code symbol to steppers B-G. d) transmits future control argument to acc. 3 in substitution order, new current

control argument to acc. 3 in unconditional transfer, and 2 digit constant to acc. 15 in the “next two digits” order.

3) Acc. 8 a) Stores the current control argument in the first two counters at the right, the

function table selection group for the current arg. in the 3rd and 4th counters from the right, the future control argument and associated FTSG in the next 4 counters, and the 6th instruction of a function table line in the remaining two decade counters.

b) Performs the magnitude discrimination of a conditional transfer. c) Shifts the future control argument with its FTSG into the position of the current

argument & FTSG in case C.T. +. B. For the Arithmetic system.

1) Accumulator 4 – builds up quotient which it then transmits with clearing to acc. 15 at end of division.

2) Acc. 5 – holds numerator during division or radicand (clear & receive radicand from acc. 15 is part of √ order) during square rooting. Programming for division & √ will be


such that remainder is retained at end of ÷ & √ in case operations with 10k digits are performed.

3) Acc. 7 – holds denominator (clear & receive denom. from acc. 15 is part of ÷ order) in ÷ and builds up twice the square root in √. Programming for √ includes instructions to send twice the square root to acc. 15. five times so as to avoid the necessity for halving.

4) Acc. 9 – shifts the remainder from the numerator or radicand when overdraft occurs in ÷ or √.

5) Acc. 11 a) Holds the multiplier in multiplication. b) Clears and then receives a sign and 6 of the 12 digits emitted by the function

table in the F.T.3 numeric order (the other sign & 6 digits from the function table are simultaneously received in acc. 15).

6) Acc. 12 a) Clears and then receives the multiplicand (icand) from acc. 15 as part of the

multiplication order. b) Provides temporary storage for numbers from acc. 4 or 7 during ÷ or √

respectively. 7) Acc. 13 – this accumulator follows the usual rule for accs. that it clear before

receiving but not in conjunction with transmission with the exceptions noted below in 7a & 7b. a) Holds the left hand partial products during multiplication & transmits them (with

clearing) to acc. 15 as the final step in multiplication. N.B. no provision is made to clear 13 before a multiplication is performed. This provides a simple method for forming ax+b when a & b both come from the function table or when b requires shifting before addition to ax. As an illustration, consider the case when a & b both originate in the F.T. The required orders are:

① FT3 numeric order (this puts a in acc. 11, b in acc. 15) ② 15 → 13 ③ x → 15 ④ multiply. (x goes to acc. 12 & ax+b results in acc. 15)

b) Participates in the subtract and shift (+1, -1, +5, -5 where + indicates to the right & the numeral, the no. of places) orders. In these orders, 15 holds the number to be operated on. Acc. 13 clears and then receives the operand and finally transmits the no. with clearing back to acc. 15.

8) Acc. 15 – central arithmetic and transfer organ. a) Communicates with all non-control accs. as follows: all non-control accs. can

transmit with holding to acc. 15 which does not clear on reception and acc. 15


can transmit (& simultaneously clear) to any non-control accumulator with the receiving accumulator clearing before reception).

b) Provides communication with the divider, multiplier, function tables, and constant transmitter as follows: i) in division – acc. 15 sends the denom. to acc. 7, provides temporary storage

for a no. previously stored in acc. 9, and at the end of ÷, stores the quotient. ii) in square rooting – acc. 15 sends the radicand to acc. 5, provides temporary

storage for a no. previously stored in acc. 9, and at the end of √, stores the square root.

iii) in F.T. numeric order – receives 6 (of the 12) digits and 1 (of the 2) signs emitted by the F.T. (also see 5b).

iv) in the constant transmitter orders (43, 44, 45) accumulator 15 successively receives the signed 10 digit nos. specified by the letters in the order with return to the control after each reception and with sufficient delay interspersed between successive receptions to allow execution of one of the orders 1 – 33 (see table 1).

v) receives from acc. 6 the pair of digits in the position of the next instruction in the “next two digits” order. These are received in the counters at the far right of acc. 15, the positions most convenient for the argument for the function tables.

vi) stores product in multiplication. Also transmits icand to acc. 12 at beginning of multiplication.

II Input & Output. A. Reading – the read order causes the IBM reader to read the next card in its input hopper

& store this information in the relays of the constant transmitter. The constant transmitter orders (43 – 45) produce this information for the ENIAC’s use. Incidentally, computation ceases when the cards in the reader input hopper have been exhausted.

B. Printing – the static outputs of the counters of accs. 1, 2, 15, 16, 17, 18, 19, & 20 are connected to the ENIAC printer. When the print instruction is given, any information in these accumulators is delivered to the printer relays & thence, to the IBM card punch. Computation is terminated also when the input hopper for the punch runs out of cards.


7/10/47 Digit Connections for Control System – Table 2

Lead of

Digit Term Digit Terminal

Acc. 3 Acc. 6 Acc. 8

11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1

α D I I II II II II I I I I I II II II II I I I I I I I II II III III III III III III III III

1 2 1 8 7 6 5 6 5 4 3 11 8 7 6 5 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1

β I I I I I I I I I I I I I I III III III III III III III III _ _ _ III III III III III III II II 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

γ I I I _ _ _ _ I I I I I _ _ I I I I _ _ _ _ _ I I _ _ _ _ I I _ _

11 10 9 4 3 2 1 11 8 7 6 5 11 11

4 3

δ _ _ _ IV III _ _ _ _ _ _ _ II II _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ III III III III 11 11 10 9

8 7 6 5

ε _ _ _ I I I I I I I I I III III III III III III III III II II _ _ _ II II I I III III III III

8 7 6 5 4 3 2 1 11 8 7 6 5 4 3 2 1 10 9

6 5 6 5 8 7 6 5

A D II II III III III III III III III III D II II II II I I I I I I D I I I I I I I I I I

3 10 9 8 7 6 5 4 3 2 1 1 8 7 6 5 6 5 4 3 2 1 5 10 9 8 7 6 5 4 3 2 1

S D I I _ _ _ _ _ _ _ _ D _ _ _ _ _ _ _ _ I I D _ _ _ _ _ _ D D _ _ 4 5 4 2

6 5 6

7 8

Function Tables:

Entry A11 A6 A5 A4 A3 A2 A1* B6 B5 B4 B3 B2 B1

** B11 F. T. Argument Input

Connected to digit line

IV 11

II 10

II 9

II 8

II 7

II 6

II 5

I 6

I 5

I 4

I 3

I 2

I 1

III 11 Lead

F.T. 2 1 F.T. #1 III2 III1 F.T. #2

I2 I1 F.T. #3

<Illegible –cf comment III re Subtract-

Correct switch>

Information held

FTSG digit one

0 or 9 I6 I5 I4 I3 I2 I1

FTSG digit two

0 or 9

Information sent as 9 or 0 99 – I6 99 – I5 99 – I4 99 – I3 99 – I2 100 – I1 9 or 0

Input

standard

Output


Comments for Table 2 – C−2

I Notation for Counters, Digit Terminals, & Trunk Lines. Each of the 20 accumulators has ten decade counters and a binary counter for sign indication + (P) or – (M). The decade counters are numbered one to ten from right to left. The sign counter is referred to as the eleventh counter.

Each acc. has 5 terminals for the input of digital information & 2 for the output. The digit input terminals are designated by the letters α, β, ϒ, δ, ε; the output terminals, by the letters A (for transmission of the contents) & S (for transmission of the complement). Each digit terminal has 11 leads numbered to correspond to the counters (see previous paragraph).

Trunk lines consisting of 11 wires are used for the communication of digit and program pulses. The wires of a trunk bear the same nos. as do the leads of the accumulator digit terminals to which they are connected by ordinary digit cables (see II, C-2).

Ordinarily, I designate the different digit trunk lines by a Roman numeral and the program trunks by capital letters or Arabic numerals. The trunk line designation is then followed by a dash and an Arabic numeral for the wire no. For example, 40-3 represents the 3 line in the 40th program trunk. Because of space limitations in table 2, however, I used subscripts instead of the dash followed by an Arabic numeral for wires in a trunk.

II Special Digit Connections It is simple to construct specially wired plug & socket assemblies (called adaptors) to make non-standard connections between the wires in a trunk & a digit terminal. Adaptors can be used to delete the pulses in certain places, to shift, or for any other special purpose. Table 2 describes the adaptors to be used for the control system. Only the β terminal of acc. 3 uses a standard connection; all others call for an adaptor.

III Function Table Storage & transmission. Each of the 3 function tables stores digital information consisting of 12 digits & two signs for each of 102 values of an independent variable. 6 digits & one sign are delivered to one output terminal, designated by A, & the remaining digits & sign to the other terminal, designated by B. The leads of these terminals are numbered to correspond to the trunk wires to which they are connected by standard digit cables.

The function tables can be instructed to transmit either the number stored on a given line or its complement (the latter transmission is referred to as S transmission).

I plan to store 6 instructions on each line, with each instruction consisting of a pair of coded symbols. The pair of sign switches on each line are to store the function table selection


group required for a substitution or an unconditional transfer order (see C-1, I A 3). The discrimination to determine when a new line of orders must be read is easily handled if the negatives of the orders are stored in an accumulator, so I plan to send instructions out of the F.T. subtractively. Ordinarily, the F.T. sends out complements with respect to nine, but a complement with respect to ten in a given place can be obtained by setting the Subtract-Correct corresponding to that place at Subtract. I plan to set the Subtract-Correct switch corresponding to position B1 at subtract, & all others at off. This accounts for the fact, that the F.T. transmits 100-I1 but 99-I2 thru 99-I6.


ENIAC Set up for Control Process and Orders 48 – 51 Table 3 page 1

Add. Time Master Programmer Acc. 3 Acc. 6 Acc. 8

Accumulator Dummy Function Table Constant <illegible> 15 Programs #1 #2 #3 Trans.

C-1 is D of

either M(99-I6)(99-I5)…(99-I3)(100-I2) or P 010 <illegible> P 02, xxαfβf, xxαcβc CONTROL PROCESS # ##

1 L-1

αO1 M(100−I2)(99−I6)…(99−I3) C-1 ASO1 A(11) → D-1

S(11) → D-2 D-1

001 R-1

D-1 002 or

D-2 001

S-1

D-2 001

L-9

# 2 R-1

αO1 R-2

M(153−I2)(99−I6)…(99−I3)

#

I1 > 53 *

L-8 **

I1 ≤ 53 R-1

KR L-14

P0853

3

X-1 is D of R-2

ASO1 C-2

A(11) → D-3 S(11) → D-4

L-8 γO1 P 99, xxαfβf, xxαcβc D-3

001 X-1

D-3 001

L-5

D-4 001 L-18

D-4 002

D-4 002

L-14 JL

M05

* 4 C-2

clear direct input of A – K

I-6 to A di

L-16 γO1 M(129−I2)(99−I6)…(99−I3)

L-5 OC1

*

X-4

C-3

X-1 KL

X-2 M76005

5 I-5

B – G di

I-4 H – K

di

X-2 SO1

C-3

S(10) → I-5 S(9) → I-4

X-2 002

X-2 001

L-2

X-2 001 L-14

6 C-3 Ai

6

C-5

L-2 βO1

P(129−I2)(99−I6)…(99−I3)

X-4

L-14 JL

M05

7 C-5 G i

4,

C-6

5,

C-7

or 6

C-8

L-3 AC1

X-4 is D of X-4 βO1

L-9 M 02, (99−I6) … (99−I3)

X-4 002

X-4 002

X-4 001

L-2

X-4 002

X-4 JL

M05

8 C-6 H i C-7 J i C-8 K i

H 1, 2, … or K 6 operation pulse

71, 72, … 96

L-2 βO1

P 99, xxαfβf, xxαcβc

L-9 AC1

X-6

L-3

L-6

9 operation begins in this add time

L-3 AC1

L-6

δC1 M 99, (99−I6) … (100−I3) X-6

βO1 P 02, xxαfβf, xxαcβc

** 4’ I-6 to A di I-5 to B – G di

X-4 is D of

L-18 SC1

S(2) → I-6 S(1) → I-5

**

X-4

C-3

5’ C-3 1, 2, … or 6

A i C-11 C-12 … C-16

C-3 AC1

X-4 βO1

L-9 M 02, (99−I6) … (99−I3)

X-4 002

X-4 002

X-4 001

L-2

X-4 002

X-4 JL

M05

6’ C-11 Bi C-12 Ci C-16 Gi

B 1, 2, … or G 3 oper. pulse 01, 02, … 53

L-2 βO1


L-9 AC1

X-6

L-3

L-6

7’ operation begins in this add time

L-3 AC1

L-6

δC1 M 99, (99−I6) … (100−I3) X-6

βO1 P 02, xxαfβf, xxαcβc

## 1’’ S-1 is D of L-2

βO1

P 02, xxαfβf, xxαcβc L-9

AC1

## If 99, then FT1 alone

S-1 001

L-4

S-1 003

S-1 SONC 1

NC → D-11

2’’ L-4

AO1

D-11 is D of ?-?

αO1 M 02, xxαfβf, xx αcβc If 09, then FT1 followed

by FT2

D-11 JL L-11

M05

3’’

?-?

SC1 S(4) → D-7 S(3) → D-8

If 90,

then FT1 followed by FT3

D-7 002

D-8 002

S-2

4’’ S-2 is D of L-3

AC1

S-2 αO1 P 02, xxαfβf, xxαcβc

E-2

F-3

S-2 001

L-1

5’’ L-1

αO1 P(100−I1)(99−I5)…(99−I2)

L-1

αO1 P (99–I6), xxαfβf, xxαcβc case B

S-3

E-2 SONC 1

NC → D-15

F-3 SONC 1

NC → D-15

6’’ D-15

OC1 D-16

D-15 AO1

S-3 003

7’’ case B D-16

εO1 L-3


D-16

AC1

8’’ L-3

AC1

L-3 βO1 P 02, xxαfβf, xxαcβc

S-4


7/10/47

Table 3

Add. Time

Master Programmer

Acc. 3

Acc. 6

Acc. 8

Accumulator 15

Dummy Programs

Function Tables Constant Trans. #1 #2 #3

or (case B)

P(100−I1)(99−I5)…(99−I2) P 010

or

(case B)

P (99–I6), xxαfβf, xxαcβc


S-4

9’’ S-4 is D of

or

L-1 αO1

(case B)

P(100−I1)(99−I5)…(99−I2)

P(100-I’1)(99-I’5)…(99-I’2)

where Jk = Ik or I’k S-4 αC1

S-5

P (99–I6), xxαfβf, xxαcβc

or (case B) P (99-I’6), xxαfβf, xxαc(βc+1)

case B

10’’ S-5

AO1 L-2

S-5

εO1 S-6

P(99−J5)(99−J4)…(100-J1)

S-5 OO1 L-14

11’’ L-2

βO1 M(100−J1)(99−J5)…(99-J2) S-6

αO1 R-1

M(99−J5)(99−J4)…(100-J1)

L-14 JL M05

Continue with # on p 1


COMMENTS FOR TABLE 3 − C−3

I General comments on notation Programming in Table 3 is described by listing in a column the events which take place in a given unit and on a horizontal line, the events which take place in a given addition time. Accumulator columns have 2 divisions. The one on the left carries information about the order performed and the one on the right, indicates the number which the accumulator stores as a result of executing the order. When a magnitude discrimination takes place, the output lead or leads which figure in the discrimination are indicated in the contents part of the acc. column. An order is said to be executed by a program control. A program control consists of a transceiver (with program terminals for input and output pulses) or receiver (with only a program pulse input terminal) and switches appropriate to the unit for specifying program options. In table 3, orders are described by symbols written on 3 levels: 1) trunk & line which carries program input pulse, 2) program switch setting, & 3) trunk & line to which the program output pulse is delivered. In the control system, I found myself running out of accumulator & constant transmitter program controls. In order to be able to use the same program control on different occasions when different program pulses were available as program input pulses, I used buffer (or pulse amplifier) units. When trunks A, B, & C are connected by buffer units as indicated in the diagram below, the following properties obtain:

1) a pulse carried on wire w of trunk C is available also on wire w of trunk A 2) a pulse carried on wire w of trunk B is available also on wire w of trunk A 3) a pulse carried on wire w of trunk A is available only on wire w of trunk A. Lines B-w & C-w are referred to as the duals of A-w.

II Comments on Notation for Specific Units A. Master Programmer

1) Ten steppers (A−K omitting I)

A

B

C

Buffer

Buffer


2) Inputs ordinary (i) – receives pulse, causes stepper to transmit program output pulse. direct input (di) – receives pulses which cause stepper to advance one stage per

pulse – no output pulse transmitted. clear direct input (cdi) – receives pulse which clears stepper to first stage.

3) Outputs – each stepper has 6 outputs, each corresponding to a stage of the stepper. Output terminal corresponding to stage k is designated by k. Program line to

which k delivers program output pulse appears below k. B. Accumulator program switches

1) 1st symbol operation switch setting = operation A, S, or AS = transmit add, subtract, or both resp. α, β, γ, δ, or ε = receive thru designated terminal O = neither receive nor transmit

2) 2nd symbol = clear switch setting C = clear when preceded by A, S, or O

= when preceded by α - ε increase by 1 in counter 1 on each repetition 3) 3rd symbol = repeat switch setting (only for transceivers)

1, 2, …, 9 = no. of times operation specified by 1st 2 symbols is successively repeated

C. Function tables 1) First symbol specifies Additive or Subtractive transmission 2) Second symbol (-2, -1, 0, 1, 2) transmission of line corresponding to argument (0), of

previous line (-1), of succeeding line (+1), etc. 3) Third symbol (C, NC, O) specifies whether function table is to transmit pulse calling

for transmission of argument out of the C or NC terminal or not at all (O). 4) Fourth symbol (1, 2, …, 9) specifies how many times the information specified by the

1st two symbols is to be successively transmitted. N.B. F.T. begins to transmit in the 5th add. time.

D. Constant transmitter Capital letter (A … K) designates the 10 digit group called for & subscripts L & R refer to the left and right hand signed 5 digit subgroups of that group. Groups A – H are read from IBM card. Groups J & K are hand set on switches. The contents column for the constant transmitter indicates the number stored in the designated constant transmitter group.


III Blow by Blow Description of Control Process

At the beginning of this operation, accumulator 6 holds the complements of 5

instructions. At the top of page 1, the instructions are designated by I2, …, I6. Actually they are Ij, …, Ij+4 where j = 1, 2, …, 6.* Each instruction is a pair of digits. An instruction still to be executed is represented by one of the pair of digits in column C.S. of Table 1. An executed instruction is represented by the digits 00. For expository purposes, I will speak of accumulator as being divided into 5 subsidiary accumulators, each consisting of a pair of counters. Hence, the complements are written as complements with respect to 99 or 100. The instructions are to be executed in the order of ascending subscripts (i.e. the complement of the current order appears in the right most pair of counters of acc. 6.)

*See bottom of table 2.

Add. Time Event

1 Send instructions to acc. 3 & discriminate to determine whether or not to read a

new line of orders from F.T. If at least one instruction in acc. 6 is greater than 00, sign counter of acc. 6 registers M. If all instructions in acc. are 00, sign counter registers P. In case sign is M, continue with line 2; in case sign is P, continue with line 1’’.

2 & 3 Discriminate to determine whether instruction is one of first 33 or last 18. If one of last 18 continue to line 4, otherwise to line 4’. Also, clear all master programmer steppers. Also, in add. time 3, receive 99 at far left of acc. 8. This will serve as 99−I7.

4 Send 5 digit pulses to stepper A (so as to send stepper A to stage 6) from C.T. M76005.

5 Send tens digit of (I2−3) to steppers B−G & units digit of I2 to steppers H−K. 6 – 9 Return instructions I3−I6 from acc. 3 to acc. 6 shifted two places to the right. Also

send I7 from acc. 8 to 3 & then to far left of 6, deleting I7 from acc. 8. During add times 6−8, moreover, a program pulse is routed thru stepper A, to stepper G, and then to one of the steppers H−K to yield the operation pulse specified by I2.

4’ In case, I2 is one of the first 33 instructions. Acc. 6 sends the tens place of I2 to

stepper A & the units place of I2 to steppers B−G. 5’ – 7’ Acc. 3 sends instructions back to acc. 6 shifted two places to right and acc. 8 sends

I7 to acc. 3 & then to the far left of acc. 6. I7 is deleted from the left of acc. 8 in the process. During add. times 5’ & 6’, moreover, a program pulse is routed thru stepper A to one of the steppers B−G to yield the operation pulse specified by I2.


1’’ – 2’’ F.T. 1 is stimulated to send a new line of instructions and receives current argument from acc. 1.

3’’ Acc. 8 carries out discrimination on F.T.S.G. to determine whether FT 2 or FT 3 or neither are specified by FTSG.

4’’ Current & future arguments are restored to acc. 8. 5’’ Line of instructions is emitted by F.T. 1. Complements of I1−I5 are received in acc. 3

& complement of I6 is received at extreme left of acc. 8. 6’’ – 8’’ Performed only if F.T. 2 or F.T. 3 are stimulated as result of events in add. time 3’’.

In 6’’−8’’, I1−I5 are cleared out of acc. 6 & I6 is cleared out of acc. 8. 9’’ Acc. 3 receives I1−I5 & acc. 8, I6 in case FT 2 or FT 3 have been stimulated;

otherwise, nothing. Also, the current argument is increased by 1. 10’’ & 11’’ Acc. 3 sends instructions to acc. 6 so that accs 3, 6, 8 have contents required to

continue control process from add. time 2, page 1.

central control for eniac by adele k. goldstine, july 10,...

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