Central Reference Design

Ray XuJuly 25, 2019

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Outline

• Overview of Central Reference

• Overview of Existing BGP

– Modifications

• Overview of RDAC

• Overview of BGP-to-1.1V Amplifier

• Overview of Output Section

• Overall Results

• Design Concerns

• Summary

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Overview of Central Reference

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Overview of Central Reference

• Three main blocks

– (Modified) BGP

– RDAC’s

– BGP-to-1.1V amplifier

• Main modes of operation

– VREFN = BGP, VREFP=BGP (good PSRR, good noise)

– VREFN = RDAC, VREFP = RDAC (bad PSRR, good noise)

– VREFN&VREFP = overridden off-chip

• Operational redundancy in mind

• Output impedance of VREF’s: 40 kOhms

– Open-loop (replica) output4

Overview of BGP

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Overview of BGP

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Overview of BGP

• Any internal modification = redesign

• Ground-referenced, single-ended

– Original designers have output decoupled to GND

– PMOS VDSAT is 300mV: cannot obtain 1.1V

• IP from Italian group

• Three modifications to BGP (by bringing out specific wires)

– External startup

– External current source

– BGP adjustability

• LVS & DRE errors due to use of donut transistors

– Understood and will be waived7

BGP External Startup

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BGP External Startup

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BGP startup circuit disconnected, only for sim purposes

BGP startup circuit disconnected, only for sim purposes

Startup pulse

100 mV nominal

3x “surge”

Simulated across all BGP options and 5 corners

BGP Current Source

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BGP Current Source

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PMOS mirror internal to BGP

PMOS mirror outside of BGP

BGP Current Source

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Nominal: 50uA

Green: Full (+8 steps) up Adjustment

Red: neutral adjustment

Yellow: Full (-8 steps) down Adjustment

X-axis: corner

BGP Adjustability

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Nominal: 100 mV

Green: Full (+8 steps) up Adjustment

Red: neutral adjustment

Yellow: Full (-8 steps) down Adjustment

X-axis: corner

Overview of RDAC

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Alternative to BGP VREFN and VREFP using off-chip bias current

Example of low-side RDAC used to obtain RDAC_VREFN and RDAC_VCM.

Binary-weighted resistor string w/ 50uA DC bias.

High-side complement used to obtain RDAC_VREFP

This is how on-chip VCM is obtained in all cases.

RDAC current source may be derived from external bias or bandgap current source.

Overview of RDAC

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Resistor string, distributed by common centroid per segment

Switches (200u/60n each)

Wire matrix

Overview of RDAC

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Low-side RDAC sweep of digital code versus BGP adjustment and corners

Nominal: 100mV and 600mV

Step size: about 20mV per digital code

Overview of RDAC

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High-side RDAC sweep of digital code versus BGP adjustment and corners

Nominal: 1100 mV

Step size: about 20mV per digital code

Overview of Amplifier

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Amplifier core

Gain-boosted folded cascode

Re-used, with minor changes, from amplifier in CV2 test structures; proven silicon

80 dB open loop gain

Optimized for low-VCM input

Overview of Amplifier

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Output stage of amplifier

Replica common-source w/ 90 Ohm high-side resistor.

Resistive load allows output to go all the way to positive rail

Gain adjustable in ~ 20mV output steps using binary-weighted resistor string

Replica output to have an open-loop output; mitigates stability issues

Overview of Amplifier

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Programmable gain resistor string

Amplifier core

Output Stage

Output stage wiring, poly resistor, and power mesh oversized above electromigration standards in case of misconfigured state

(Low/misconfigured Vout pulls up to 13 mA thru 90 Ohm resistor)

Power mesh

Overview of Amplifier

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Sweep of VREFP across gain code and corners, BGP adjustment

VREFP output step: approx 20mV per digital code

Nominal: 1100 mV. Phase margin: 65 ~ 75 deg across corners

Overview of Output Section

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Similar structure for VREFP outputSelection switch: VREFN={BGP or RDAC} or high-Z; Amplifier input={BGP or RDAC}VREFP={Amp or RDAC} or high-ZVCM=RDACOutput resistor: 44 kOhm needed to filter noise in combo with capacitor

VREFP-VREFN PSRR

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BGP → Amplifier. No external cap (worst case). VREFP Single-endedAC diff sources: VDD and GND; AC diff probe: VREFP-VREFNSchematic, TT

< -40dB systematic differential PSRR!(-20 dB in layout)

Includes both contributions from VDD and GND

Summed Noise (1Hz→10GHz)

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VREFN: BGP VCM: RDAC VREFP: BGP→Amplifier

Dominant noise source is 1/f noise of BGPRelies on external cap (bondwire is modeled; ideal ext cap)

Schematic, TT (+/- 10uVrms max across corners)

External cap→ None

(6pF pad+pkg)100pF 1nF 10nF 100nF 1uF

VREFN10.60

(uVrms)10.36 9.34 8.68 7.90 7.39

VCM 71.73 (no off-chip filtering)

VREFP 102.2 92.04 77.27 61.83 38.96 11.14

VREFP-VCM 97.77 90.68 85.32 81.44 75.99 72.3

VCM-VREFN 72.08 71.64 70.87 70.06 69.19 68.91

VREFP-VREFN 95.62 86.25 72.63 58.31 37.25 13.03

Design Concerns

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• Leakage current

– Output of all VREF’s are high impedance (40 kOhm)

– Outputs can only be connected to mosfet gate and metal capacitors only! (to name a few)

– Outputs cannot be directly connected to MOS decap nor resistive loads

• Differential stability

– Ensure caps to ground >> caps between VREFP&N

– Bulk capacitance will be placed off-chip as well

– High-impedance of BGP output + amplifier topology makes differential decap look like a weak feedback loop

Design Concerns

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• Kickback

– Please place as much metal capacitors in the channel to bypass VREFP,N to GND to mitigate kickback effect coming from reference buffers

• PSRR

– Ensure PSRR of VREFP and VREFN reference buffers are near equal to ensure PSRR of (VREFP-VREFN) does not worsen

Summary

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• Central reference block provides VREFP,N,CM and bias currents

• Multiple ways to tune BGP

• Multiple ways to get VREFP,N from BGP and/or bias current

• All else fails: external bias current, over-ride voltages directly from off-chip

• Off-chip option to receive and distribute bias current

• All controls are independent of each other