CEO Perspective –– Delivering the Fifth Wave of Computing Simon Segars, Chief Executive Officer, Arm

With any journey you know two things: Where you’ll start and where you’ll end up. The latter is always a hope rather than a certainty though and is fully dependent on your ability to get from Point A to Point B. For us as technology innovators. Point A is today, Point B is the ultimate conclusion of the Fifth Wave of Computing – built on Artificial Intelligence (AI) the Internet of Things (IoT) and 5G. So, what will make this a successful journey?

The vehicle for getting us from A to B is the chip technology enhancement that is driving the performance and efficiency uplifts necessary for Fifth Wave technologies and applications to reach maturity

and scale. Those applications include autonomous cars, next generation Augmented and Virtual Reality tools and a host of other AI-powered devices in the consumer, industrial, and business markets.

Here is where the work that the semiconductor industry is doing now is so critical as foundries refine processes and push advances improving power, performance, and area (PPA), while reducing costs.

Advanced thinking, advanced processes

Silicon foundries are straining the limits of Moore’s law with the introduction of the most cutting-edge process nodes—7nm, 5nm, 4nm, and even 3nm set for production by 2021. Innovations in extreme ultraviolet (EUV) lithography are in early deployment and set to scale into high-volume use by 2020. And next-generation device structures, such as gate-all-around (GAA) FET and nanosheets, continue to show promise in allowing further scaling beyond today’s transistor designs.

In current mainstream technology, I am also seeing activities around FDSOI picking up at the 28nm, 22nm and 18nm nodes where device body biasing offers a unique differentiation in wide performance-power/leakage dynamic range. Products based on this technology are already available from Arm’s partners including NXP and ST.

Additionally, foundries are introducing special planar process variants at 22nm, which are gaining strong momentum among designers. The addition of new features, such as RF and embedded non-volatile memory, further extends the value of improvements in process technology for new use cases in applications including 5G, AI and automotive.

We are also seeing significant development significant advances outside of process technology, often referred to as More than Moore, especially the area of advanced packaging. Heterogenous integration is become more prevalent and the overall concept of system-level PPA optimization is becoming even more critical in extracting the greatest value from silicon technologies.

As part of Arm’s commitment to developing optimized solutions ranging from physical IP to processor cores (including CPU, GPU, NPU), we are studying every dimension of the design process and collaborating with foundries around the world to get the best from their innovation. This collaboration begins as early as possible so we can help ensure a successful, timely product roll out for our partners, and ensure they have access to the best IP in the industry.

The next wave of computing, the Fifth Wave, is already starting to make an impact, but ultimate success will depend on delivery of the most advanced geometries, performance and power scaling and device enhancements. This foundry-level innovation will be a vital part of us making the journey from Point A to Point B successful.

If you want to learn more about how that journey is progressing you should visit ES Design West, co-located with SEMICON West 2019 in San Francisco, July 9 — 11, 2019. For anyone interested in chip technology advances, this is the place where you’ll find the answers.

Welcome to ES Design West –– Where Design Meets Manufacturing Bob Smith, Executive Director, ESD Alliance, A SEMI Strategic Association Partner

It’s a pleasure to welcome you to ES Design West and SEMICON West on behalf of the ESD Alliance, a SEMI Strategic Association Partner!

The ES Design West goal is to enable and accelerate conversations, information exchange and collaboration to address common issues, challenges and opportunities that move new electronic products from concept to consumer. We invite you to help us meet that goal as we proudly highlight commercial achievements of electronic system design, including IP, EDA, embedded software, design services and infrastructure including design in the cloud through an assortment of presentations and panel discussions.

As you walk the exhibit floor, meet colleagues and friends, and hear keynote speakers and other presenters, expect to talk about the growing links between electronic system and semiconductor design with the electronic product manufacturing and supply chain. It’s happening and it’s real.

Take advantage of our varied, three-day program featuring six “Meet the Experts” sessions Tuesday through Thursday in our SMART Design Pavilion that analyze chip design, system hardware and software and system integration … now and in the future.

With so many relevant talks related to electronic system and semiconductor design and the connections to manufacturing, we took over a second stage –– TechTalk Stage South –– for one fascinating afternoon. “TechTALK: Applied AI in Design-to-Manufacturing” will be held Tuesday from 2 p.m. until 4 p.m.

Your ES Design West badge will enable you to attend nine SEMICON West keynote talks at the Blue Shield of California Theater over the three-day conference. Keynote presenters include Gary Dickerson, president and CEO of Applied Materials, AMD President and CEO Lisa Su, Aart de Geus, Synopsys chairman and co-CEO, and Bob Pearson, author and senior Advisor at W2O Group. Other keynote speakers are Dean Kamen, founder of DEKA Research & Development Corporation and founder of FIRST® (For Inspiration and Recognition of Science and Technology), and Jeffrey Welser, vice president and lab director of IBM Research-Almaden.

Of course, ES Design West needs a party to celebrate our achievements in the evening hours. That means the HOT Party! The Heart of Technology (HOT) fundraising party will happen Tuesday evening, July 9, featuring three bands, drinks and food. Sponsored by Jim Hogan, with the help of a large group of co-sponsors, it will be held at the John Colins Lounge in San Francisco from 5:30 p.m. until 10 p.m. Show your ES Design West or SEMICON West badge to be admitted. We suggest a minimum tax-deductible $20 donation. Non-conference guests can attend for a tax-deductible donation of $50.

This year’s beneficiary is the SEMI Foundation supporting Science, Technology, Engineering and Mathematics (STEM) education and career awareness in high technology. All proceeds from the event will be contributed to the SEMI Foundation. Event co-sponsors are ESD Alliance, Team Hogan, SEMI, eSilicon, Burr & Forman, LLP, Sage Design Automation, Harvest Management Partners, LLC, Breker, Pulsic, OneSpin Solutions, Methodics, Silvaco and Kathy Pesic, the owner of Silvaco, Big Kahuna Productions and Mod Marketing.

ES Design West took careful planning and assistance from a host of the electronic system and semiconductor design ecosystem’s most well-connected and energetic members. Our enthusiastic Advisory Council developed a rich and comprehensive conference experience to shine the spotlight on electronic system design at its best through its business achievements, commercial technological accomplishments and role in the broader electronics manufacturing supply chain. We are grateful to their support and hard work.

Chaired by Julie Rogers, director of marketing, SEMI Americas, and director of marketing and operations, ESD Alliance, Advisory Council members are:

• Dennis Brophy, director of strategic business development from Mentor, a Siemens Business • Rick Carlson, vice president of sales at Verific • Dave Kelf, Breker Verification Systems’ chief marketing officer • Stan Kroliwkoski, Cadence fellow, standards • Vic Kulkarni, vice president and chief strategist at Ansys • Ramond Rodriguez, Intel’s manager of EDA Suppliers • Herta Schreiner, vice president of corporate marketing at Synopsys • Elan Tanzer, technical content director from Arm • Jan Willis, executive advisor from Calibra

Thank you one and all for making ES Design West –– Where Design Meets Manufacturing –– a success. Enjoy the show!

Committee Updates

Export (Larry Disenhof, Cadence Design Systems). The Export Committee continues to monitor government activities and rulings that might have a significant impact on your business.

You know it’s an interesting time when family dinner conversations turn to discussions about international trade. At a recent open meeting, the Deputy Undersecretary at the Bureau of Industry and Security (BIS) stated “If you want to know what’s going on at BIS, read the press.” This is good advice; those of us whose jobs focus on trade issues are spending our days reading the news since we’re getting our information there more quickly than from the agencies.

Not widely reported is the BIS review of “Emerging” and “Foundational” technologies, a requirement of the Export Control Reform Act of 2018 passed last August. The initial review began in November when BIS issued an Advance Notice of Proposed Rulemaking (“ANPRM”) on Emerging Technology, requesting feedback on their list of new technology not currently subject to the export regulations. Several hundred responses to the ANPRM were received and still being reviewed.

BIS expects to issue an ANPRM on Foundational technologies as early as July 1st. Foundational technologies is defined as items currently subject to export controls. Their review is to determine if current controls are sufficient. We will plan an appropriate response once this ANPRM is published. Actual changes to the regulations resulting from these ANPRM reviews will take many months. If there are proposed changes that affect the EDA community, we will keep the membership informed.

License Management & Anti-Piracy (LMA) (Sashi Subramanian, Cadence Design Systems). The LMA committee continued to hold regular meetings to discuss matters of common interest. We made progress getting the Joint Development Agreement finalized for the Machine Certification project. The document is currently being reviewed by the legal team from each Development Partner. The committee has also been actively engaged with Flexera on improving the license server capacity to support large transaction volumes, currently a limitation for the FlexNet license server.

The CELUG event for 2019 was co-located at DAC and a few committee members attended the event. It was a fruitful event where we heard challenges faced by our customers in managing their licenses and the licensing environment. The LMA committee held its annual face-to-face meeting on the sidelines of DAC as well. We had Flexera talk in detail about the license server capacity roadmap. In the meeting, the committee also discussed constraints around the various Machine Certification approaches.

Interoperability (Richard Paw, Amazon Web Services). As the Electronic Systems Design market continues to evolve, the Interoperability Committee continues to explore factors that could impact the operation or the interoperability of electronic system design tools or IP.

The ESD Alliance OS Roadmap represents industry guidelines regarding operating system versions that EDA vendors should publish against and customers should start their designs on. The "Max version for vendors" indicate the latest OS version vendors should release the software on. "Min version for users" indicates the oldest OS version that customers should start new designs on.

Following our annual OS vendor review, the committee has decided to mark SLES 11 as "deprecated." This indicates that SLES 11 support is expected to end soon and customers are urged to not start new designs on SLES 11. Customers should consider starting new designs on SLES 12 instead. We expect to remove SLES 11 from the OS roadmap at the beginning of 2020.

As always, you can find the latest OS Roadmap on the ESD Alliance website, esd-alliance.org.

Market Statistics Service (MSS): (Paul Cohen, SEMI). The ESD Alliance’s MSS report captures EDA, semiconductor IP and services revenue data reported in complete confidence by companies providing these products and services and organizes it into a published report available to members. The most recent report, covering through Q1, 2019, shows quarterly industry

revenue up 16.3% compared to Q1, 2018 on revenues of $2.6 billion, with the 4-quarter moving average up 6.1% The report includes historical revenue data by quarter organized by detailed product categories (chart) and geographic regions. The report provides valuable data to help guide member companies’ business decisions. Additional information including the MSS Newsletter is available at esd-alliance.org.

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Emerging Companies (Julie Rogers, SEMI). The Emerging Companies Committee continues to hold informative events on topics of interest to the system and semiconductor design ecosystem.

The ESD Alliance held two events this spring, both at SEMI in Milpitas. The first event April 10 was Jim Hogan’s “Fireside Chat with Paul Cunningham.” Jim is the managing partner at Vista Ventures; Paul is corporate vice president and general manager of the system verification group at Cadence Design Systems. After an informal dinner Jim and Paul spoke about Paul’s experiences in EDA, including starting Azuro (acquired by Cadence), and his views on the challenges ahead.

The second event was the annual CEO Outlook, held May 23. Recognizing the focus on the entire electronic product design and manufacturing chain, we included two CEOs from the ESD Alliance membership and two with expertise in other aspects of the chain. The panel, moderated by Semiconductor Engineering’s Ed Sperling, included John Chong (Kionix), Jack Harding (eSilicon), John Kibarian (PDF Solutions) and Wally Rhines (Mentor, a Siemens Business).

Additional information and photos from these events are in the newsletter supplement. Recordings of these and other past events are available in the ESD Alliance Resource Center.

We’re busy working on a schedule of educational and networking events for the fall! Check the ESD Alliance website, esd-alliance.org, for details as they become available.

Tradeshow (Bob Smith, SEMI). The committee represents the interests of ESD Alliance companies at ES Design West, Design Automation and Test Europe (DATE), SEMICON West, SEMICON China, and others.

ES Design West, co-located with SEMICON West is the flagship U.S. event for connecting the electronic system and semiconductor design ecosystem.

Themed BEYOND SMART, SEMICON West 2019 sets it sights on the growing impact of cognitive learning technologies and other industry disruptors with programs and new Pavilions including ES Design West. ES Design West features a dedicated Meet the Experts Theater with an intimate setting for attendees to engage informally

with industry thought leaders. In addition to the Meet the Experts Theater in the Smart Design Pavilion, attendees can attend a session on the future of design in the TechTALK theater. Also of interest to designers, Aart de Geus, Chairman and co-CEO of Synopsys, Inc., will deliver the a keynote address on Tuesday in the “AI Design Forum™: The Future of Computing – from Materials to Systems.”

Now that the ESD Alliance is a SEMI Strategic Association Partner, we are planning new events at other SEMICON shows around the world. Stay tuned as information about these new events becomes available!

The ESD Alliance –– Where Electronics Begins The ESD Alliance newsletter is a publication of the ESD Alliance, a SEMI Strategic Association Partner. For more information, visit: esd-alliance.org Q1 2019. Volume 6, Number 2 Electronic System Design Alliance, 673 South Milpitas Blvd., Milpitas, CA 95035. Phone (408) 287-3322 Editor: Paul Cohen Contributors Paul Cohen, SEMI Nanette Collins, Nanette V. Collins Marketing & PR

Executive Director: Bob Smith Larry Disenhof, Cadence Design Systems Richard Paw, Rescale Julie Rogers, SEMI

Bob Smith, ESD Alliance Sashi Subramanian, Cadence Design Systems

Governing Council Raik Brinkmann, OneSpin Aart de Geus, Synopsys Dean Drako, IC Manage

David Dutton, Silvaco John Kibarian, PDF Solutions Prakash Narain, Real Intent

Walden C. Rhines, Mentor, a Siemens Business Simon Segars, ARM (Chair) Lip-Bu Tan, Cadence Design Systems

Follow us at: Website: esd-alliance.org ESD Alliance Bridging the Frontier blog: http://bit.ly/2oJUVzl

Twitter: @ESDAlliance LinkedIn: https://www.linkedin.com/groups/8424092 Facebook: https://www.facebook.com/ESDAlliance

 

Paul McLellan, Simon Matthews, Graham Bell and Bob Smith enjoy dinner before the Fireside Chat. 

Jim talks with Paul Cunningham and Maheen Hamid before the chat 

Jim and Paul covered a range of topics during the informative Fireside Chat. 

The audience learning about Paul’s experiences developing EDA tools and companies, and his views on challenges ahead. 

 

Jim Hogan’s Fireside Chat with Paul Cunningham  

On April 10, 2019, Jim Hogan and Cadence’s Paul Cunningham held a Fireside Chat that swept through topics from the startup experience, artificial intelligence, concurrent physical optimization to system functional verification and open source architectures. 

Jim, managing partner of Vista Ventures, LLC., and Paul, corporate vice president and general manager of the system verification group at Cadence Design Systems, had plenty to talk about. It started with Paul’s experience working in artificial intelligence before it was an industry trend, founding Azuro and the subsequent acquisition by Cadence in 2011 to managing Cadence’s system verification group. 

Attendees learned about Paul’s move 18 months ago from managing physical design tools development to system functional verification and the challenges ahead. Other topics of widespread interest that were discussed included open source architectures and the necessary development platforms.  

For more information about these and other ESD Alliance events, visit the Resource Center at esd‐alliance.org. 

 

 

 

           

 

 

 

 

 

 

 

 

  

  

Simon Matthews, Fumiko Suzuki, Manoj Jha and Dave Graubart enjoy dinner before the CEO Outlook. 

Bob Smith introduces the panelists, Jack Harding, Wally Rhines, John Chong and John Kibarian. 

The audience learned about major trends in the industry and potential opportunities. 

Panel moderator Ed Sperling with panelists Wally Rhines, John Chong, John Kibarian and Jack Harding. 

ESD Alliance 2019 CEO Outlook 

The ESD Alliance 2019 CEO Outlook was held May 23, at SEMI in Milpitas, Calif. Our moderator, Ed Sperling, editor in chief of Semiconductor Engineering, led a discussion with our panelists John Chong, vice president of product and business development for Kionix, Jack Harding, president and CEO of eSilicon, John Kibarian, PDF Solutions’ president and CEO, and Wally Rhines, CEO emeritus of Mentor, a Siemens Business. 

Recognizing that the ESD Alliance is now part of SEMI where our collective focus is on the broader electronic product design and manufacturing chain, this year’s CEO Outlook included two panelists from the ESD Alliance and two panelists who have experience and expertise in other aspects of the chain. 

The distinguished panel discussed major new trends they see, with the potential opportunities they anticipate. For more information about these and other ESD Alliance events, visit the Resource Center at esd‐alliance.org.